Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responding to the amendment filed on 1/14/2026.
Claims 1-20 are pending in the application.
The rejection under 35 U.S.C. 101 is withdrawn due to the amendment to the claim 19.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Pope et al. (US20200344180, hereafter Pope) in view of Peterson et al. (US10601732, hereafter Peterson).
Per claim 1:
Pope teaches:
1. A method comprising: compiling, by a compiler, a received program to provide a compiler output for configuring hardware to implement the received program, said received program relating to packets of data in a memory, said compiling comprising defining by the compiler output (Pope, see at least [0026]; [0119]; [0159]; [0160] performing a compilation process to compile a first function to be performed by a second circuitry of a network interface device; prior to completion of the compilation process, sending a first instruction to cause a first circuitry of the network interface device to perform the first function with respect to data packets received at a first interface of the network interface device; and sending a second instruction to cause the second circuitry to, following completion of the compilation process, begin performing the first function with respect to data packets received at the first interface);
a plurality of computational units in the hardware, each of the computational units being configured to receive a packet of data as a stream of words; and between a first computational unit and a second computation unit of the plurality of computational units, a first buffer configured to store words of a packet produced by the first computation unit (Pope, see at least [0400] Each of them supports a streaming packet interface allowing packets traversing the slice to be streamed in and out of the component- Note that a stream is a continuous flow of words [0407]; [0234]; [0239], [0235] the data may be written to a buffer 107 in the host system 101. The data may then be retrieved from the buffer 107 by the network interface device and transmitted over the network 103; [0231] The application 105 can send and receive TCP/IP messages by opening a socket and reading and writing data to and from the socket-Note that ; [0236] In both of these cases, data is temporarily stored in one or more buffers prior to transmission over the network. Data sent over the network could be returned to the host (in a lookback); [0075] the first interface being configured to receive a plurality of data packets; a configurable hardware module comprising a plurality of processing units, each processing unit being associated with a predefined type of operation executable in a single step, wherein at least some of said plurality of processing units are associated with different predefined types of operation, wherein the hardware module is configurable to interconnect at least some of said plurality of said processing units to provide a first data processing pipeline for processing one or more of said plurality of data packets to perform a first function with respect to said one or more of said plurality of data packets).
Pope does not explicitly teach a second buffer, separate from the first buffer configured to store non-packet data produced by first computational unit, the non-packet data comprising one or more of metadata, user data, or program data, wherein communication from the first buffer and the second buffer define separate, parallel communication paths from the first computational unit to the second computational unit, and wherein, during operation of the configured hardware, the second computational unit concurrently receives packet words from the first buffer and non-packet data from the second buffer as separate inputs. However, Peterson teaches between a first computational unit and a second computation unit of the plurality of computational units, a first buffer configured to store words of packet produced by the first computational unit and a second buffer, separate from the first buffer configured to store non-packet data produced by first computational unit, the non-packet data comprising one or more of metadata, user data, or program data, wherein communication from the first buffer and the second buffer define separate, parallel communication paths from the first computational unit to the second computational unit, and wherein, during operation of the configured hardware, the second computational unit concurrently receives packet words from the first buffer and non-packet data from the second buffer as separate inputs (Peterson, see at least fig. 6 and associated texts, If the pipeline has an ingress packet to process, the process 600 determines (at 610) whether any internally-generated non-packet data is available to send to the match-action unit with the packet. In some embodiments, if the MAU resources will be used for processing an ingress packet, the parser will always include the next set of non-packet data (if any is available) along with the ingress packet. With the non-packet data paralleling the packet data (as opposed to being transmitted as a special type of ingress packet), the processing of actual received data packets is not delayed; figs 9-11, claim 12 and associated texts, In the first stage 905 (showing a clock cycle T1), the parser 900 receives a first packet 915 as well as a piece of stateful internally-generated non-packet data 920. This non-packet data 920 provides the current (or at least recent) state of queue 2. In this case, the parser 900 does not have a built-up input queue for either packets or non-packet data, and thus can process this data right away. The parser 900 also keeps track of an indicator bit 925, which is currently set to 0. This indicator bit alternates, in some embodiments, each time non-packet data is sent into the pipeline in a PHV container; If a read operation is to be performed, the process 1200 stores (at 1215) the received non-packet data to the copy of the table identified by the received indicator bit, while simultaneously reading from the other copy of the table. On the other hand, if no read operation is required for the current clock cycle, the process stores (at 1220) the received non-packet data to the copy of the table identified by the received indicator bit without performing a read operation from the table). It would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to have combined Peterson’s buffering technique for parallel processing with Pope’s compilation to modify Pope’s system to combine the separate buffering as taught by Peterson, with a reasonable expectation of success, since they are analogous art because they are from the same field of endeavor related to data processing. Combining Peterson’s functionality with that of Pope results in a system that allows separate buffering for packet and non-packet data. The modification would be obvious because one having ordinary skill in the art would be motivated to make this combination to achieve concurrent data flow of different data types (Peterson, see at least fig. 6 and associated texts, If the pipeline has an ingress packet to process, the process 600 determines (at 610) whether any internally-generated non-packet data is available to send to the match-action unit with the packet. In some embodiments, if the MAU resources will be used for processing an ingress packet, the parser will always include the next set of non-packet data (if any is available) along with the ingress packet. With the non-packet data paralleling the packet data (as opposed to being transmitted as a special type of ingress packet), the processing of actual received data packets is not delayed; figs 9-11, claim 12 and associated texts, In the first stage 905 (showing a clock cycle T1), the parser 900 receives a first packet 915 as well as a piece of stateful internally-generated non-packet data 920. This non-packet data 920 provides the current (or at least recent) state of queue 2. In this case, the parser 900 does not have a built-up input queue for either packets or non-packet data, and thus can process this data right away. The parser 900 also keeps track of an indicator bit 925, which is currently set to 0. This indicator bit alternates, in some embodiments, each time non-packet data is sent into the pipeline in a PHV container; If a read operation is to be performed, the process 1200 stores (at 1215) the received non-packet data to the copy of the table identified by the received indicator bit, while simultaneously reading from the other copy of the table. On the other hand, if no read operation is required for the current clock cycle, the process stores (at 1220) the received non-packet data to the copy of the table identified by the received indicator bit without performing a read operation from the table).
2. The method as claimed in claim 1, wherein the data output from the first computational unit comprises data resulting from one or more actions performed by the first computational unit (Pope, see at least [0006] The bit file description may comprise for at least one of said plurality of processing units routing information indicating at least one of: to which one or more other processing units data can be output; and from which one or more other processing units data can be received; [0123]; [0136]; [0018] The bit file description may comprise for at least one of said plurality of processing units routing information indicating at least one of: to which one or more other processing units data can be output; and from which one or more other processing units data can be received).
3. The method as claimed in claim 1, wherein the concurrent receipt of the packet words and the non-packet data is performed for a same packet being processed by the second computational unit. (Peterson, see at least; fig. 1 and associated texts describing the queuing and buffering system for parallel processing col.2 right col., With the non-packet data paralleling the packet data…is not delayed; fig. 6 and associated texts, If the pipeline has an ingress packet to process, the process 600 determines (at 610) whether any internally-generated non-packet data is available to send to the match-action unit with the packet. In some embodiments, if the MAU resources will be used for processing an ingress packet, the parser will always include the next set of non-packet data (if any is available) along with the ingress packet. With the non-packet data paralleling the packet data (as opposed to being transmitted as a special type of ingress packet), the processing of actual received data packets is not delayed; figs 9-11, claim 12 and associated texts, Note that parsing the packet to store header fields of the packet in the first set of data containers and storing the received non-packet data generated by the network forwarding IC I the second set of containers are for the same packet passing through the pipeline and processed in parallel threads simultaneously. The packet thread can read non-packet/control data belonging to the same packet because at least one data container of the second set of data containers is also accessed by the first thread).
16. The method as claimed in claim 1, wherein the compiling comprises compiling the received program to an intermediate representation and compiling the intermediate representation to provide the compiler output (Pope, see at least [0456] The compiler flow will now be described. The front end of the compiler receives an eBPF program. The eBPF program may be written in any suitable language. For example, the eBPF program may be written in a C type language. The compiler is configured at the front end to convert the program to an intermediate representation IR. In some embodiments the IR may be a LLVM-IR or any other suitable IR; [0458] It should be appreciated, that in some embodiments, an optimization of the IR may be performed by the compiler; 0254] The eBPF language can be executed efficiently on an x86 processor and JIT (Just in Time) compilation techniques enable eBPF programs to be compiled to native machine code).
17. The method as claimed in claim 1, wherein the received program is an EBPF program (Pope, see at least [0013] The program may comprise one of an eBPF program and a P4 program).
Per claim 18:
Pope further discloses: a third computational unit; a third buffer; and a fourth buffer, wherein the third buffer and the fourth buffer are between the second and the third computational units, wherein the third buffer configured to store words of a packet while the fourth buffer stores data output by the second computational unit of the plurality of computational units (Pope, see at least [0400] Each of them supports a streaming packet interface allowing packets traversing the slice to be streamed in and out of the component; [0407]; [0234]; [0235] the data may be written to a buffer 107 in the host system 101. The data may then be retrieved from the buffer 107 by the network interface device and transmitted over the network 103; [0236] In both of these cases, data is temporarily stored in one or more buffers prior to transmission over the network. Data sent over the network could be returned to the host (in a lookback); [0075] the first interface being configured to receive a plurality of data packets; a configurable hardware module comprising a plurality of processing units, each processing unit being associated with a predefined type of operation executable in a single step, wherein at least some of said plurality of processing units are associated with different predefined types of operation, wherein the hardware module is configurable to interconnect at least some of said plurality of said processing units to provide a first data processing pipeline for processing one or more of said plurality of data packets to perform a first function with respect to said one or more of said plurality of data packets).
Pope does not explicitly wherein communication from the third buffer and the fourth buffer to the third computational unit is carried out at the same time. However, Peterson teaches wherein communication from the third buffer and the fourth buffer to the third computational unit is carried out at the same time (Peterson, see at least fig. 6 and associated texts, If the pipeline has an ingress packet to process, the process 600 determines (at 610) whether any internally-generated non-packet data is available to send to the match-action unit with the packet. In some embodiments, if the MAU resources will be used for processing an ingress packet, the parser will always include the next set of non-packet data (if any is available) along with the ingress packet. With the non-packet data paralleling the packet data (as opposed to being transmitted as a special type of ingress packet), the processing of actual received data packets is not delayed; figs 9-11, claim 12 and associated texts, while simultaneously reading from the other copy of the table. On the other hand, if no read operation is required for the current clock cycle, the process stores (at 1220) the received non-packet data to the copy of the table identified by the received indicator bit without performing a read operation from the table). It would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to have combined Peterson’s buffering technique for parallel processing with Pope’s compilation to modify Pope’s system to combine the separate buffering as taught by Peterson, with a reasonable expectation of success, since they are analogous art because they are from the same field of endeavor related to data processing. Combining Peterson’s functionality with that of Pope results in a system that allows separate buffering for packet and non-packet data. The modification would be obvious because one having ordinary skill in the art would be motivated to make this combination to achieve concurrent data flow of different data types (Peterson, see at least fig. 6 and associated texts, If the pipeline has an ingress packet to process, the process 600 determines (at 610) whether any internally-generated non-packet data is available to send to the match-action unit with the packet. In some embodiments, if the MAU resources will be used for processing an ingress packet, the parser will always include the next set of non-packet data (if any is available) along with the ingress packet. With the non-packet data paralleling the packet data (as opposed to being transmitted as a special type of ingress packet), the processing of actual received data packets is not delayed; figs 9-11, claim 12 and associated texts, In the first stage 905 (showing a clock cycle T1), the parser 900 receives a first packet 915 as well as a piece of stateful internally-generated non-packet data 920. This non-packet data 920 provides the current (or at least recent) state of queue 2. In this case, the parser 900 does not have a built-up input queue for either packets or non-packet data, and thus can process this data right away. The parser 900 also keeps track of an indicator bit 925, which is currently set to 0. This indicator bit alternates, in some embodiments, each time non-packet data is sent into the pipeline in a PHV container; If a read operation is to be performed, the process 1200 stores (at 1215) the received non-packet data to the copy of the table identified by the received indicator bit, while simultaneously reading from the other copy of the table. On the other hand, if no read operation is required for the current clock cycle, the process stores (at 1220) the received non-packet data to the copy of the table identified by the received indicator bit without performing a read operation from the table).
Per claims 19 and 20, they are the apparatus and medium versions of claim 1 respectively, and are rejected for the same reasons set forth in connection with the rejection of claim 1 above.
Claims 4-9 are rejected under 35 U.S.C. 103 as being unpatentable over Pope in view of Peterson and Zhu et al. (US20230353455, hereafter Zhu).
Per claim 4:
Pope does not explicitly teach wherein the compiling comprises determining a plurality of accesses in the received program and converging two or more common accesses to provide a single converged access for two or more instructions, wherein the received program when run will execute one but not other of the two or more instructions. Zhu teaches determining a plurality of accesses in the received program and converging two or more common accesses to provide a single converged access for two or more instructions, wherein the received program when run will execute one but not other of the two or more instructions (Zhu, see at least [0019] combine multiple access networks or select the best one to improve quality of experience (QoE) for a user and improve overall network utilization and efficiency …flexible combination of access and core network paths based on defined policies … for improving network utilization and efficiency and enhanced QoE for user applications (apps); [0045] MPTCP is reused as the “MX Convergence Sublayer” protocol, and multiple access networks are combined into a single MPTCP connection …to manage traffic steering and aggregation over multiple delivery connection; [0046] GRE is reused as the “MX Convergence sub-layer” protocol, and multiple access networks are combined into a single GRE connection; [0345] per-packet aggregation allows a single IP flow to use the combined bandwidth of the two connections; [0346] GMA is usually used when multiple access network connections are used, but may also be used when only a single access network connection is used). It would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to have combined Zhu’s accesses in a program and converging them with Pope’s compilation to modify Pope’s system combined with Peterson’s packet processing technique to combine the converged access as taught by Zhu, with a reasonable expectation of success, since they are analogous art because they are from the same field of endeavor related to data processing. Combining Zhu’s functionality with that of Pope and Peterson results in a system that allows a converged access. The modification would be obvious because one having ordinary skill in the art would be motivated to make this combination to improve overall data access utilization (Zhu, see at least [0019] combine multiple access networks or select the best one to improve quality of experience (QoE) for a user and improve overall network utilization and efficiency …flexible combination of access and core network paths based on defined policies … for improving network utilization and efficiency and enhanced QoE for user applications (apps); [0045] MPTCP is reused as the “MX Convergence Sublayer” protocol, and multiple access networks are combined into a single MPTCP connection …to manage traffic steering and aggregation over multiple delivery connection; [0046] GRE is reused as the “MX Convergence sub-layer” protocol, and multiple access networks are combined into a single GRE connection; [0345] per-packet aggregation allows a single IP flow to use the combined bandwidth of the two connections; [0346] GMA is usually used when multiple access network connections are used, but may also be used when only a single access network connection is used).
5. The method as claimed in claim 4, wherein the compiling comprises defining a respective computational unit in the hardware to perform the respective single converged access (Zhu, see at least [0019] combine multiple access networks or select the best one to improve quality of experience (QoE) for a user and improve overall network utilization and efficiency …flexible combination of access and core network paths based on defined policies … for improving network utilization and efficiency and enhanced QoE for user applications (apps); [0045] MPTCP is reused as the “MX Convergence Sublayer” protocol, and multiple access networks are combined into a single MPTCP connection …to manage traffic steering and aggregation over multiple delivery connection; [0046] GRE is reused as the “MX Convergence sub-layer” protocol, and multiple access networks are combined into a single GRE connection; [0345] per-packet aggregation allows a single IP flow to use the combined bandwidth of the two connections; [0346] GMA is usually used when multiple access network connections are used, but may also be used when only a single access network connection is used).
6. The method as claimed in claim 4, wherein the compiling further comprises determining an order of the plurality of accesses and when converging the two or more common accesses, maintaining the order of the plurality of accesses (Zhu, see at least [0056] The NCM 236 also acts as a common MA gateway for network policy input and interface to application platforms; [0071] placed at a separate network element like a common UP gateway across the multiple networks; (Zhu, see at least [0019] combine multiple access networks or select the best one to improve quality of experience (QoE) for a user and improve overall network utilization and efficiency …flexible combination of access and core network paths based on defined policies … for improving network utilization and efficiency and enhanced QoE for user applications (apps); [0045] MPTCP is reused as the “MX Convergence Sublayer” protocol, and multiple access networks are combined into a single MPTCP connection …to manage traffic steering and aggregation over multiple delivery connection; [0046] GRE is reused as the “MX Convergence sub-layer” protocol, and multiple access networks are combined into a single GRE connection; [0345] per-packet aggregation allows a single IP flow to use the combined bandwidth of the two connections; [0346] GMA is usually used when multiple access network connections are used, but may also be used when only a single access network connection is used).
7. The method as claimed in claim 4, wherein the compiling further comprises inserting a first converge instruction before the single converged access and/or a second converge instruction after the single converged access (Zhu, see at least [0019] combine multiple access networks or select the best one to improve quality of experience (QoE) for a user and improve overall network utilization and efficiency …flexible combination of access and core network paths based on defined policies … for improving network utilization and efficiency and enhanced QoE for user applications (apps); [0045] MPTCP is reused as the “MX Convergence Sublayer” protocol, and multiple access networks are combined into a single MPTCP connection …to manage traffic steering and aggregation over multiple delivery connection; [0046] GRE is reused as the “MX Convergence sub-layer” protocol, and multiple access networks are combined into a single GRE connection; [0345] per-packet aggregation allows a single IP flow to use the combined bandwidth of the two connections; [0346] GMA is usually used when multiple access network connections are used, but may also be used when only a single access network connection is used).
8. The method as claimed in claim 4, wherein the plurality of accesses comprise map accesses (Pope, see at least [0313], A map access stage; Zhu, see at least [0019] combine multiple access networks or select the best one to improve quality of experience (QoE) for a user and improve overall network utilization and efficiency …flexible combination of access and core network paths based on defined policies … for improving network utilization and efficiency and enhanced QoE for user applications (apps); [0045] MPTCP is reused as the “MX Convergence Sublayer” protocol, and multiple access networks are combined into a single MPTCP connection …to manage traffic steering and aggregation over multiple delivery connection; [0041] a source NAT at the client with inverse mapping at the server 140 and/or Network Multi Access Data Proxy (N-MADP) 237 of FIG. 2); [0283] Connection Information: This data type provides the mapping of connection ID and connection type; [0453] Each tag is mapped into a specific UE 920 in the MNO's system; [0466] In a first implementation, a UPF of the 5GS is mapped into the MEC architecture 900 as the MEC data plane 924).
9. The method as claimed in claim 4, wherein the plurality of accesses comprise packet accesses (Pope, see at least [0038], access the first data packet; [0310], perform packet access operations; Zhu, see at least [0057] distribution of data packets over the multiple available access paths 221-1 to 221-n, delivery paths 222-1 to 222-n, and/or core network paths; [0012]; [0022]).
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Pope in view of Peterson and Waskiewicz et al. (US11743367, hereafter Waskiewicz).
Per claim 10:
Pope does not explicitly teach adding packet modifying commands in a data stream, said packet modifying commands comprises at least one of adding data to or removing data from a packet. Waskiewicz teaches adding packet modifying commands in a data stream, said packet modifying commands comprises at least one of adding data to or removing data from a packet (Waskiewicz, see at least fig. 1 and 2 and associated text, the NIC 132 performs packet modification such as dropping a packet). It would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to have combined Waskiewicz’s packet modification with Pope’s compilation to modify Pope’s system and Peterson’s packet processing technique to combine the packet modification as taught by Waskiewicz, with a reasonable expectation of success, since they are analogous art because they are from the same field of endeavor related to data processing. Combining Waskiewicz’s functionality with that of Pope and Peterson results in a system that allows packet modification. The modification would be obvious because one having ordinary skill in the art would be motivated to make this combination to achieve packet processing efficiency (Waskiewicz, see at least fig. 1 and 2 and associated text, the NIC 132 performs packet modification such as dropping a packet).
11. The method as claimed in claim 10, wherein the compiling further comprises providing tracking logic in one or more of the plurality of computational units to track the adding or removing of data from a packet (Waskiewicz, see at least fig. 1 and 2 and associated text, The eBPF program 214 may make a packet processing action determination (e.g., drop, forward, modify, etc.) based on the contents of the metadata) and the NIC 132 performs packet modification such as dropping a packet).
Claims 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Pope in view of Peterson and Reid (US20130080737).
Per claim 12:
Pope does not explicitly teach determining that two or more accesses to different memory locations are to be combined in a single access operation when the two or more accesses are within a given range to a same set of memory locations. Reid teaches determining that two or more accesses to different memory locations are to be combined in a single access operation when the two or more accesses are within a given range to a same set of memory locations (Reid, see at least [0199] When the checked address mode flag is set, accesses from the first and second VMU are combined into a single cache access; [0026], treat a multiple bank memory as a single data store while in others each bank is treated independently; 0028] When treating the banks independently then the constraints on accesses between different banks are not applied while the constraints are still applied to accesses to a same bank; [0036], in a same clock cycle are to a same cache line and in response to determining they are combining said data accesses such that they are performed as a same data access; [0037], Accessing a cache is expensive in power and if a same cache line is to be accessed by two data access requests, then it would be advantageous if these accesses could be combined to form a single access; [0141], accesses to the same bank can be coalesced into a single access; [0148], coalescing is typically performed within a single vector access to exploit locality within a vector but it is common for there to be significant locality between corresponding element positions in two vector accesses). It would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to have combined Reid’s single access in a program and converging them with Pope’s compilation to modify Pope’s system combined with Peterson’s packet processing technique to combine the converged access as taught by Reid, with a reasonable expectation of success, since they are analogous art because they are from the same field of endeavor related to data processing. Combining Reid’s functionality with that of Pope and Peterson results in a system that allows a combined access. The modification would be obvious because one having ordinary skill in the art would be motivated to make this combination to achieve cost effective memory utilization (Reid, see at least [0199] When the checked address mode flag is set, accesses from the first and second VMU are combined into a single cache access; [0026], treat a multiple bank memory as a single data store while in others each bank is treated independently; [0037], Accessing a cache is expensive in power and if a same cache line is to be accessed by two data access requests, then it would be advantageous if these accesses could be combined to form a single access; [0141], accesses to the same bank can be coalesced into a single access; [0148], coalescing is typically performed within a single vector access to exploit locality within a vector but it is common for there to be significant locality between corresponding element positions in two vector accesses).
Per claim 13:
Pope does not explicitly teach determining that two or more accesses to different memory locations are to be combined in a single access operation when the two or accesses associated with a common computed variable address are within a given range. Reid teaches determining that two or more accesses to different memory locations are to be combined in a single access operation when the two or accesses associated with a common computed variable address are within a given range (Reid, see at least [0199] When the checked address mode flag is set, accesses from the first and second VMU are combined into a single cache access; [0026], treat a multiple bank memory as a single data store while in others each bank is treated independently; [0037], Accessing a cache is expensive in power and if a same cache line is to be accessed by two data access requests, then it would be advantageous if these accesses could be combined to form a single access; [0141], accesses to the same bank can be coalesced into a single access; [0148], coalescing is typically performed within a single vector access to exploit locality within a vector but it is common for there to be significant locality between corresponding element positions in two vector accesses). It would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to have combined Reid’s single access in a program and converging them with Pope’s compilation to modify Pope’s system and Peterson’s packet processing technique to combine the converged access as taught by Reid, with a reasonable expectation of success, since they are analogous art because they are from the same field of endeavor related to data processing. Combining Reid’s functionality with that of Pope and Peterson results in a system that allows a combined access. The modification would be obvious because one having ordinary skill in the art would be motivated to make this combination to achieve cost effective memory utilization (Reid, see at least [0199] When the checked address mode flag is set, accesses from the first and second VMU are combined into a single cache access; [0026], treat a multiple bank memory as a single data store while in others each bank is treated independently; [0037], Accessing a cache is expensive in power and if a same cache line is to be accessed by two data access requests, then it would be advantageous if these accesses could be combined to form a single access; [0141], accesses to the same bank can be coalesced into a single access; [0148], coalescing is typically performed within a single vector access to exploit locality within a vector but it is common for there to be significant locality between corresponding element positions in two vector accesses).
Per claim 14:
Pope does not explicitly teach determining that a single memory access is to two or more different sets of memory locations and splitting the single memory access into a plurality of different memory accesses each to a respective set of memory locations. Reid teaches determining that a single memory access is to two or more different sets of memory locations and splitting the single memory access into a plurality of different memory accesses each to a respective set of memory locations (Reid, see at least [0108] accessing data stored in a plurality of memory banks. In this regard programs with gather scatter vector memory access instructions can have a high address bandwidth (i.e., many addresses are presented to the memory system per cycle) and therefore benefit from a memory system that can perform multiple accesses per cycle. This is frequently implemented by splitting the memory system into a number of independently accessible banks and arranging the address map such that a vector memory access will typically access multiple banks--allowing the accesses to be performed in parallel with each other; [0210]). It would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to have combined Reid’s splitting memory access with Pope’s compilation to modify Pope’s system combined with Peterson’s packet processing technique to combine memory access splitting as taught by Reid, with a reasonable expectation of success, since they are analogous art because they are from the same field of endeavor related to data processing. Combining Reid’s functionality with that of Pope and Peterson results in a system that allows to split memory access. The modification would be obvious because one having ordinary skill in the art would be motivated to make this combination to independently access memory banks for parallel process (Reid, see at least [0108] accessing data stored in a plurality of memory banks. In this regard programs with gather scatter vector memory access instructions can have a high address bandwidth (i.e., many addresses are presented to the memory system per cycle) and therefore benefit from a memory system that can perform multiple accesses per cycle. This is frequently implemented by splitting the memory system into a number of independently accessible banks and arranging the address map such that a vector memory access will typically access multiple banks--allowing the accesses to be performed in parallel with each other; [0210]).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Pope in view of Peterson and Quan et al. (US20080127140, hereafter Quan).
Per claim 15:
Pope does not explicitly teach determining a number of program branches in the received program and reducing the number of program branches following one another by combining two or more program branches into a switch. Quan teaches determining a number of program branches in the received program and reducing the number of program branches following one another by combining two or more program branches into a switch (Quan, see at least [0020] These subsets are each merged into a result instruction, and these results are folded together with a switch on the runtime program index, with each branch being the result of one of the subset merges. This switch is the final result of the overall merge. At function/call boundaries, the call is augmented with the runtime program index, so that it will call the augmented (merged) version of the function; [0023] which will eliminate the use of the program index for branches of the code which are wholly invariant, and dead function elimination, which will remove the original, duplicated versions of the merged functions). It would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to have combined merging branches into a switch with Pope’s compilation to modify Pope’s system combined with Peterson’s packet processing technique to combine the merging as taught by Quan, with a reasonable expectation of success, since they are analogous art because they are from the same field of endeavor related to data processing. Combining Quan’s functionality with that of Pope and Peterson results in a system that allows merging branches. The modification would be obvious because one having ordinary skill in the art would be motivated to make this combination to reduce duplicate code (Quan, see at least [0020] These subsets are each merged into a result instruction, and these results are folded together with a switch on the runtime program index, with each branch being the result of one of the subset merges. This switch is the final result of the overall merge. At function/call boundaries, the call is augmented with the runtime program index, so that it will call the augmented (merged) version of the function; [0023] which will eliminate the use of the program index for branches of the code which are wholly invariant, and dead function elimination, which will remove the original, duplicated versions of the merged functions).
Examiner’s Note
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply. Applicant, in preparing the response, should consider fully the entire reference as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/INSUN KANG/Primary Examiner, Art Unit 2193
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