Prosecution Insights
Last updated: October 02, 2026
Application No. 18/073,371

DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF

Final Rejection §103§112
Filed
Dec 01, 2022
Priority
Dec 22, 2021 — RE 10-2021-0184851
Examiner
MANDALA, MICHELLE
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
LG Display Co., Ltd.
OA Round
4 (Final)
91%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
924 granted / 1015 resolved
+23.0% vs TC avg
Moderate +8% lift
Without
With
+7.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
22 currently pending
Career history
1027
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
51.5%
+11.5% vs TC avg
§102
31.6%
-8.4% vs TC avg
§112
10.1%
-29.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1015 resolved cases

Office Action

§103 §112
DETAILED ACTION Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1-14 and 29 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. There is no description in the specification as originally filed of “an upper surface of the insulating layer is exposed in at least a portion of the first transmission area from layers disposed between the upper surface of the insulating layer and an upper surface of the second electrode in the first optical area”. There is only seen description of a first encapsulation layer (PAS1) and a second encapsulation layer (PCL) disposed in the insulating layer (PLN2) as shown in Fig 6 and paragraphs [213]-[214] of the specification. Any further rejection on art is based on the Examiner’s broadest interpretation of the claims. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-4, 8, 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (2022/0165984) in view of Lee et al. (2021/0249490). Re claim 1, Choi et al. disclose (Fig. 9) a display area (DA2) comprising a first optical area (PA2) and a normal area (WA) located outside of the first optical area, the first optical area comprising a light emitting area (PA2) and a first transmission area (TA); a first electrode (191) located in the first optical area; a bank (350) located on the first electrode; a spacer (SP) located along a boundary of the first transmission area (TA) ([0175]), and located on the bank (350); and a second electrode (270) located on the spacer (SP) and opened in the first transmission area (TA), and an insulating layer (161/143/162/170/180) disposed between the bank (350) and a gate electrode (GE2) of a transistor (TR2) disposed on a substrate (SB) on which the first optical area is defined, wherein the insulating layer (161/143/162/170/180) contacts a lower surface of the bank and extends to the first transmission area (TA), and wherein the bank (350) is not disposed inside of the first transmission area in a plan view. Choi et al. does not disclose an upper surface of the insulating layer is exposed in at least a portion of the first transmission area from layers disposed between the upper surface of the insulating layer and an upper surface of the second electrode (270) in the first optical area. Lee et al. disclose wherein an upper surface of the insulating layer (111) is exposed in at least a portion of the first transmission area (TA) from layers disposed between the upper surface of the insulating layer (111) and an upper surface of the second electrode (230) in the first optical area. It would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Choi et al. and Lee et al. to enable the insulating layer of Choi et al. to be exposed as taught in Lee et al. to prevent crosstalk and mechanical stress damage. Re claim 2, Choi et al. disclose wherein the first electrode (191) is located in the light emitting area (PA2) located outside of the first transmission area (TA). Re claim 3, Choi et al. disclose wherein opposing portions of an opening of the bank (350) are located near respective outer edge of the first transmission area (TA). Re claim 4, Choi et al. disclose wherein the bank (350) partially overlaps the spacer (SP) and partially overlaps the first electrode (191) (Fig. 9). Re claim 8, Choi et al. disclose further comprising an emission layer (370) disposed between the spacer and the second electrode (270) (Fig. 9). Re claim 13, Choi et al. disclose (Fig. 9) a display area (DA2) comprising a first optical area (PA2) and a normal area (WA) located outside of the first optical area, the first optical area comprising a light emitting area (PA2) and a first transmission area (TA); a first electrode (191) located in the first optical area; a bank (350) located on the first electrode; a spacer (SP) located along a boundary of the first transmission area (TA) ([0175]), and located on the bank (350); and a second electrode (270) located on the spacer (SP) and opened in the first transmission area (TA), wherein the first transmission area (TA) includes a transmittance improvement structure (610/620) (the first encapsulation layer 610 and the second encapsulation layer 620 included in the encapsulation layer 600 have a transmittance improvement structure). Re claim 14, Choi et al. disclose further comprising a plurality of insulating layers, wherein a first planarization layer (170) and a passivation layer (180) of the plurality of insulating layers overlapping with each other, each has a depressed portion that extend downward from respective surface, as the transmittance improvement structure (Fig. 9). Claim(s) 5-7, 9, 10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. in view of Lee et al. as applied to claims 1-4, 8, 13 and 14 above, and further in view of Park et al. (2018/0190731). Re claim 5, the combination does not disclose wherein the spacer has a shape that becomes gradually wider as the spacer moves away from the bank and that becomes gradually narrower as it moves toward the bank. Park et al. disclose wherein the spacer (151) has a shape that becomes gradually wider as the spacer moves away from the bank and that becomes gradually narrower as it moves toward the bank (150) (Fig. 3 [0071]). It would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Choi et al., Lee et al. and Park et al. to enable the bank shape of Choi et al. to be design as taught in Park et al. device because one of ordinary skill in the art would have been motivated to look to alternative suitable shape and dimensions for the disclosed bank shape of Choi et al. and art recognized suitability for an intended purpose has been recognized to be motivation to combine. See MPEP 2144.07. Re claim 6, Park et al. disclose wherein the spacer (151) has a reverse tapered shape (Fig. 3). Re claim 7, Park et al. disclose wherein an end of the second electrode (120) is aligned with two ends or edges of the spacer (151) or an end or edge of the spacer (Fig. 3). Re claim 9, Park et al. disclose wherein the emission layer (115) includes an opening, the opening being formed by cutting along two ends or edges of the spacer (151) or an end or edge of the spacer (Fig. 3). Re claim 10, Park et al. disclose wherein an end of the emission layer (115) is aligned with two ends or edges of the spacer (151) or an end or edge of the spacer (Fig. 3). Re claim 19, Choi et al. disclose further comprising an emission layer (370) disposed between the first electrode (191) and the second electrode (270). Choi et al. does not disclose wherein an end or edge of the spacer, an end or edge of the emission layer, and an end or edge of the second electrode are aligned with each other. However, it would have been an obvious matter of design choice bounded by well known manufacturing constraints and ascertainable by routine experimentation and optimization to choose the particular alignment because applicant has not disclosed that the alignment is for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another alignment. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Claim(s) 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. in view Lee et al. as applied to claims 1-4, 8, 13 and 14 above, and further in view of Jeon et al. (2021/0036070). Re claim 11, the combination does not clearly disclose further comprising a light shield layer located outside of the first transmission area. Jeon et al. disclose further comprising a light shield layer located outside of the first transmission area ([0086]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine Choi et al., Lee et al. and Jeon et al. to provide the light shield layer as taught in Jeon to improve image quality by preventing light leakage in Choi et al. Re claim 12, it is well known in the art before the effective filing date of the invention to provide a light shielding layer that overlaps the entire area of the light emitting area and extends from the light area up to the first transmission area. Therefore, it would have been obvious to one of ordinary skill in the art to use the known light shielding layer in order to block unwanted light from reaching sensitive areas, preventing interference signal and maintaining performance. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHELLE MANDALA whose telephone number is (571)272-1858. The examiner can normally be reached 8:00-5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHELLE MANDALA/Primary Examiner, Art Unit 2893 July 27, 2026
Read full office action

Prosecution Timeline

Show 1 earlier event
Aug 29, 2025
Non-Final Rejection mailed — §103, §112
Nov 27, 2025
Response Filed
Jan 29, 2026
Final Rejection mailed — §103, §112
Mar 18, 2026
Request for Continued Examination
Mar 25, 2026
Response after Non-Final Action
Apr 06, 2026
Non-Final Rejection mailed — §103, §112
Jun 25, 2026
Response Filed
Jul 30, 2026
Final Rejection mailed — §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12751148
LIGHT EMITTING DISPLAY APPARATUS
3y 2m to grant Granted Sep 29, 2026
Patent 12733182
MEMORY DEVICE
3y 1m to grant Granted Sep 08, 2026
Patent 12727389
METHODS OF MANUFACTURING A MAGNETIC FIELD SENSOR
3y 4m to grant Granted Sep 01, 2026
Patent 12727197
THIN FILM TRANSISTOR AND ELECTRONIC DEVICE THEREOF
2y 9m to grant Granted Sep 01, 2026
Patent 12727500
CHIP MODULE AND METHOD OF FORMING SAME
2y 8m to grant Granted Sep 01, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

5-6
Expected OA Rounds
91%
Grant Probability
99%
With Interview (+7.9%)
2y 2m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 1015 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month