DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/18/26 has been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 8, 13 and 14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Choi et al. (2022/0165984).
Re claim 1, Choi et al. disclose (Fig. 9) a display area (DA2) comprising a first optical area (PA2) and a normal area (WA) located outside of the first optical area, the first optical area comprising a light emitting area (PA2) and a first transmission area (TA); a first electrode (191) located in the first optical area; a bank (350) located on the first electrode; a spacer (SP) located along a boundary of the first transmission area (TA) ([0175]), and located on the bank (350); and a second electrode (270) located on the spacer (SP) and opened in the first transmission area (TA), and an insulating layer (161/143/162/170/180) disposed between the bank (350) and a gate electrode (GE2) of a transistor (TR2) disposed on a substrate (SB) on which the first optical area is defined, wherein the insulating layer extends (161/143/162/170/180) to the first transmission area (TA), and is exposed in at least a portion of the first transmission area from layers disposed between a lower surface of the first electrode (191) and an upper surface of the second electrode (270) in the first optical area, and wherein the bank (350) is not disposed inside of the first transmission area in a plan view.
Re claim 2, Choi et al. disclose wherein the first electrode (191) is located in the light emitting area (PA2) located outside of the first transmission area (TA).
Re claim 3, Choi et al. disclose wherein opposing portions of an opening of the bank (350) are located near respective outer edge of the first transmission area (TA).
Re claim 4, Choi et al. disclose wherein the bank (350) partially overlaps the spacer (SP) and partially overlaps the first electrode (191) (Fig. 9).
Re claim 8, Choi et al. disclose further comprising an emission layer (370) disposed between the spacer and the second electrode (270) (Fig. 9).
Re claim 13, Choi et al. disclose (Fig. 9) a display area (DA2) comprising a first optical area (PA2) and a normal area (WA) located outside of the first optical area, the first optical area comprising a light emitting area (PA2) and a first transmission area (TA); a first electrode (191) located in the first optical area; a bank (350) located on the first electrode; a spacer (SP) located along a boundary of the first transmission area (TA) ([0175]), and located on the bank (350); and a second electrode (270) located on the spacer (SP) and opened in the first transmission area (TA), wherein the first transmission area (TA) includes a transmittance improvement structure (610/620) (the first encapsulation layer 610 and the second encapsulation layer 620 included in the encapsulation layer 600 have a transmittance improvement structure).
Re claim 14, Choi et al. disclose further comprising a plurality of insulating layers, wherein a first planarization layer (170) and a passivation layer (180) of the plurality of insulating layers overlapping with each other, each has a depressed portion that extend downward from respective surface, as the transmittance improvement structure (Fig. 9).
Claim(s) 5-7, 9, 10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. as applied to claims 1-4, 8, 13 and 14 above, and further in view of Park et al. (2018/0190731).
Re claim 5, Choi et al. does not disclose wherein the spacer has a shape that becomes gradually wider as the spacer moves away from the bank and that becomes gradually narrower as it moves toward the bank.
Park et al. disclose wherein the spacer (151) has a shape that becomes gradually wider as the spacer moves away from the bank and that becomes gradually narrower as it moves toward the bank (150) (Fig. 3 [0071]).
It would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Choi et al. and Park et al. to enable the bank shape of Choi et al. to be design as taught in Park et al. device because one of ordinary skill in the art would have been motivated to look to alternative suitable shape and dimensions for the disclosed bank shape of Choi et al. and art recognized suitability for an intended purpose has been recognized to be motivation to combine. See MPEP 2144.07.
Re claim 6, Park et al. disclose wherein the spacer (151) has a reverse tapered shape (Fig. 3).
Re claim 7, Park et al. disclose wherein an end of the second electrode (120) is aligned with two ends or edges of the spacer (151) or an end or edge of the spacer (Fig. 3).
Re claim 9, Park et al. disclose wherein the emission layer (115) includes an opening, the opening being formed by cutting along two ends or edges of the spacer (151) or an end or edge of the spacer (Fig. 3).
Re claim 10, Park et al. disclose wherein an end of the emission layer (115) is aligned with two ends or edges of the spacer (151) or an end or edge of the spacer (Fig. 3).
Re claim 19, Choi et al. disclose further comprising an emission layer (370) disposed between the first electrode (191) and the second electrode (270).
Choi et al. does not disclose wherein an end or edge of the spacer, an end or edge of the emission layer, and an end or edge of the second electrode are aligned with each other.
However, it would have been an obvious matter of design choice bounded by well known manufacturing constraints and ascertainable by routine experimentation and optimization to choose the particular alignment because applicant has not disclosed that the alignment is for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another alignment. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Claim(s) 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. as applied to claims 1-4, 8, 13 and 14 above, and further in view of Jeon et al. (2021/0036070).
Re claim 11, Choi et al. does not clearly disclose further comprising a light shield layer located outside of the first transmission area.
Jeon et al. disclose further comprising a light shield layer located outside of the first transmission area ([0086]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine Choi et al. and Jeon et al. to provide the light shield layer as taught in Jeon to improve image quality by preventing light leakage in Choi et al.
Re claim 12, it is well known in the art before the effective filing date of the invention to provide a light shielding layer that overlaps the entire area of the light emitting area and extends from the light area up to the first transmission area. Therefore, it would have been obvious to one of ordinary skill in the art to use the known light shielding layer in order to block unwanted light from reaching sensitive areas, preventing interference signal and maintaining performance.
Conclusion
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/MICHELLE MANDALA/Primary Examiner, Art Unit 2893 April 2, 2026