Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s response filed on 1/14/2026 has been entered. Claim 1, 5, 10 are amended. Claims 1 – 11 remain pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Meguro ( Pub. No. US 20170033002 A1 ), hereinafter Meguro, in view of Lysáček ( U: Lysáček, D. et al. “Structural changes of polycrystalline silicon layers during high temperature annealing.” (2008) ), hereinafter Lysáček, in view of Gao ( Pub. No. CN 102709158 A ), hereinafter Gao.
Regarding Independent Claim 1 ( Original ), Meguro teaches a process for forming a semiconductor substrate comprising the following steps:
S1: providing an initial semiconductor substrate, wherein the initial semiconductor substrate comprises a first surface oxide layer ( Meguro, Abstract, depositing the polycrystalline silicon layer further includes a stage for previously forming an oxide film on the surface of the base wafer on which the polycrystalline silicon layer is deposited ) thereon;
S2: forming a first polysilicon layer ( Meguro, Abstract, depositing a polycrystalline silicon layer ) on the first surface oxide layer at a first temperature ( Meguro, [0025], the polycrystalline silicon layer is deposited at a temperature of 900° C or more ) to form a semiconductor substrate I;
S3: the first temperature ( Meguro, [0025], the polycrystalline silicon layer is deposited at a temperature of 900° C or more );
S4: the first temperature ( Meguro, [0025], the polycrystalline silicon layer is deposited at a temperature of 900° C or more ),
S5: conducting an oxidation treatment to the first polysilicon layer to decrease the thickness of the first polysilicon layer and form a second surface oxide layer ( Meguro, [0060], the thickness of the oxide film to be formed is preferably thinner, for example, the thickness of 0.3 nm or more and 10 nm or less is preferable, since the interposed oxide film 20 between the base wafer 11 and the polycrystalline silicon layer 12 can influence property of an RF device );
S6: forming a second polysilicon layer ( Meguro, Abstract, depositing a polycrystalline silicon layer ) on the second surface oxide layer at a third temperature ( Meguro, [0025], the polycrystalline silicon layer is deposited at a temperature of 900° C or more ) to form a semiconductor substrate II;
S7: the third temperature ( Meguro, [0025], the polycrystalline silicon layer is deposited at a temperature of 900° C or more );
S8: the third temperature ( Meguro, [0025], the polycrystalline silicon layer is deposited at a temperature of 900° C or more ).
Meguro fails to teach:
S3: increasing the first temperature to a second temperature, and conducting an isothermal annealing treatment to the semiconductor substrate I at the second temperature;
S4: the second temperature,
S7: increasing the third temperature to a fourth temperature, and conducting an isothermal annealing treatment to the semiconductor substrate II at the fourth temperature;
S8: the fourth temperature.
However, Lysáček teaches:
S3: increasing the first temperature to a second temperature ( Lysáček, page 3, line 9, Significant increase in the grain size was observed after annealing at 1050°C and 1150°C ), and conducting an isothermal annealing treatment ( Lysáček, Abstract, The polycrystalline silicon films deposited at 640°C are stable upon annealing to temperatures up to approximately 900°C. Primary recrystallization has been observed between 900°C and 1150°C ) to the semiconductor substrate I at the second temperature ( Lysáček, page 3, line 9, Significant increase in the grain size was observed after annealing at 1050°C and 1150°C );
S4: the second temperature ( Lysáček, page 3, line 9, Significant increase in the grain size was observed after annealing at 1050°C and 1150°C ),
S7: increasing the third temperature to a fourth temperature( Lysáček, page 3, line 9, Significant increase in the grain size was observed after annealing at 1050°C and 1150°C ), and conducting an isothermal annealing treatment ( Lysáček, Abstract, The polycrystalline silicon films deposited at 640°C are stable upon annealing to temperatures up to approximately 900°C. Primary recrystallization has been observed between 900°C and 1150°C ) to the semiconductor substrate II at the fourth temperature;
S8: the fourth temperature ( Lysáček, page 3, line 9, Significant increase in the grain size was observed after annealing at 1050°C and 1150°C ).
Meguro and Lysáček are both considered to be analogous to the claimed invention because they are forming a semiconductor substrate. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Meguro ( polycrystalline silicon layer is deposited at a temperature of 900° C or more ), to incorporate the teachings of Lysáček ( Significant increase in the grain size was observed after annealing at 1050°C and 1150°C ), to introduce the second temperature and conducting an isothermal annealing treatment. Doing so would provide significant increase in the grain size, and therefore the performance and conductivity of polycrystalline silicon layer can be improved.
Meguro and Lysáček fails to disclose:
S4: conducting a first reduction of temperature from the second temperature to the first temperature in a CVD reaction chamber, then transferring the semiconductor substrate I to an ambient environment and conducting a first natural cooling to the semiconductor substrate I while the first temperature is achieved, wherein the first reduction of temperature has a reduction rate smaller than that of the first natural cooling;
S8: conducting a second reduction of temperature from the fourth temperature to the third temperature in the CVD reaction chamber, then transferring the semiconductor substrate II to the ambient environment and conducting a second natural cooling to the semiconductor substrate II while the third temperature is achieved, wherein the second reduction of temperature has a reduction rate smaller than that of the second natural cooling.
However, Gao teaches:
S4: conducting a first reduction of temperature ( Gao, Abstract: (2) annealing: the preparing of silicon wafer in a reaction chamber, the preserving temperature at 650-1050 °C centigrade for 10-30min; 10-15 minutes cooling to less than or equal to 300 °C, taking out the silicon epitaxial reaction chamber; claim 3, wherein the annealing temperature in step (2) is 850-950 degrees centigrade ) from the second temperature to the first temperature in a CVD reaction chamber, then transferring the semiconductor substrate I to an ambient environment and conducting a first natural cooling to the semiconductor substrate I while the first temperature is achieved, wherein the first reduction of temperature ( Gao, Abstract: (2) annealing: the preparing of silicon wafer in a reaction chamber, the preserving temperature at 650-1050 °C centigrade for 10-30min; 10-15 minutes cooling to less than or equal to 300 °C, taking out the silicon epitaxial reaction chamber; claim 3, wherein the annealing temperature in step (2) is 850-950 degrees centigrade ) has a reduction rate smaller than that of the first natural cooling ( Based on information from Gao ( Abstract and claim 3 ): the cooling rate from 650 °C to 300 °C in 10 mins is 0.58 °C / s; the cooling rate from 1050 °C to 300 °C in 10 mins is 1.25 °C / s; the cooling rate from 900 °C to 300 °C in 10 mins is 1 °C / s );
S8: conducting a second reduction of temperature ( Gao, Abstract: (2) annealing: the preparing of silicon wafer in a reaction chamber, the preserving temperature at 650-1050 °C centigrade for 10-30min; 10-15 minutes cooling to less than or equal to 300 °C, taking out the silicon epitaxial reaction chamber; claim 3, wherein the annealing temperature in step (2) is 850-950 degrees centigrade ) from the fourth temperature to the third temperature in the CVD reaction chamber, then transferring the semiconductor substrate II to the ambient environment and conducting a second natural cooling to the semiconductor substrate II while the third temperature is achieved, wherein the second reduction of temperature ( Gao, Abstract: (2) annealing: the preparing of silicon wafer in a reaction chamber, the preserving temperature at 650-1050 °C centigrade for 10-30min; 10-15 minutes cooling to less than or equal to 300 °C, taking out the silicon epitaxial reaction chamber; claim 3, wherein the annealing temperature in step (2) is 850-950 degrees centigrade ) has a reduction rate smaller than that of the second natural cooling ( Based on information from Gao ( Abstract and claim 3 ): the cooling rate from 650 °C to 300 °C in 10 mins is 0.58 °C / s; the cooling rate from 1050 °C to 300 °C in 10 mins is 1.25 °C / s; the cooling rate from 900 °C to 300 °C in 10 mins is 1 °C / s ).
Meguro and Lysáček and Gao are all considered to be analogous to the claimed invention because they are forming a semiconductor substrate. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Meguro and Lysáček ( first temperature, second temperature and conducting an isothermal annealing treatment ), to incorporate the teachings of Gao ( annealing: the preparing of silicon wafer in a reaction chamber, the preserving temperature at 650-1050 °C centigrade for 10-30min; 10-15 minutes cooling to less than or equal to 300 °C; taking out the silicon epitaxial reaction chamber ), to implement a first reduction of temperature from the second temperature to the first temperature, and a second reduction of temperature from the fourth temperature to the third temperature, and the first / second reduction of temperature has a reduction rate smaller than that of the first / second natural cooling. Doing so would provide specific slow rate of cooling from the second / fourth temperature to the first / third temperature, and therefore the warpage quality ( Gao, Abstract, The method of the invention can make the warpage (WARP) silicon epitaxial wafer is not qualified after the annealing treatment to be qualified, and can be compatible with the epitaxial process, effectively improving the warpage of the silicon epitaxial wafer ) of polycrystalline silicon layer can be improved.
Claims 2 –11 are rejected under 35 U.S.C. 103 as being unpatentable over Meguro, in view of Lysáček, in view of Gao, and further in view of Wada ( Pub. No. US 20120104565 A1 ), hereinafter Wada.
Regarding Claim 2 ( Original ), Meguro and Lysáček and Gao teach the process as claimed in claim 1, on which this claim is dependent, Meguro further teaches:
wherein the step S2 comprises:
feeding the initial semiconductor substrate to a CVD reaction chamber, and
conducting a first heating to achieve the first temperature ( Meguro, [0025], the polycrystalline silicon layer is deposited at a temperature of 900° C or more );
at the first temperature ( Meguro, [0025], the polycrystalline silicon layer is deposited at a temperature of 900° C or more ), growing the first polysilicon layer on the first surface
oxide layer by atmospheric pressure chemical vapor deposition; and
while the first temperature ( Meguro, [0025], the polycrystalline silicon layer is deposited at a temperature of 900° C or more ) is achieved.
Meguro and Lysáček and Gao fail to teach:
wherein the first heating is under an atmosphere of hydrogen, and the atmosphere is converted to a mixed gas containing hydrogen and trichlorosilane while the first temperature is achieved.
However, Wada teaches:
wherein the first heating is under an atmosphere of hydrogen( Wada, [0164], flow rate of carrier gas is appropriately adjusted within a range of 40 to 80 slm; Table 1, Carrier ( H2 ) Flow Rate ( slm ) is 85 ), and the atmosphere is converted to a mixed gas containing hydrogen ( Wada, [0164], flow rate of carrier gas is appropriately adjusted within a range of 40 to 80 slm; Table 1, Carrier ( H2 ) Flow Rate ( slm ) is 85 ) and trichlorosilane ( Wada, [0102], trichlorosilane (source gas flow rate to CVD reactor: 10 slm) while the first temperature is achieved.
Meguro, Lysáček, Gao and Wada are all considered to be analogous to the claimed invention because they are forming a semiconductor substrate. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Meguro, Lysáček, Gao ( first temperature, second temperature and conducting an isothermal annealing treatment, specific slow rate of cooling from the second temperature to the first temperature ), to incorporate the teachings of Wada ( a mixed gas containing hydrogen and trichlorosilane with specific flow rates ), to implement the flatness of polycrystalline silicon layer. Doing so would provide specific composition and flow rate of carrier gases, and therefore the flatness of polycrystalline silicon layer can be improved.
Regarding Claim 3 ( Original ), Meguro, Lysáček, Gao, and Wada teach the process as claimed in claim 2, on which this claim is depend, Meguro and Wada further teach:
wherein the hydrogen has a gas flow of 40 slm- 80 slm ( Wada, [0164], flow rate of carrier gas is appropriately adjusted within a range of 40 to 80 slm; Table 1, Carrier ( H2 ) Flow Rate ( slm ) is 85 ), the mixed gas has the hydrogen gas flow of 40 slm- 80 slm ( Wada, [0164], flow rate of carrier gas is appropriately adjusted within a range of 40 to 80 slm; Table 1, Carrier ( H2 ) Flow Rate ( slm ) is 85 ) and the trichlorosilane gas flow of 3 slm- 12 slm ( Wada, [0102], trichlorosilane (source gas flow rate to CVD reactor: 10 slm) … flow rate: trichlorosilane 5 slm …), and the first temperature is 900°C-1000°C ( Meguro, [0025], the polycrystalline silicon layer is deposited at a temperature of 900° C or more ).
Regarding Claim 4 ( Original ), Meguro, Lysáček, Gao, and Wada teach the process as claimed in claim 2, on which this claim is depend, Lysáček further teaches:
wherein the step S3 comprises:
conducting a second heating and simultaneously converting the atmosphere to hydrogen gas;
while the second temperature ( Lysáček, page 3, line 9, Significant increase in the grain size was observed after annealing at 1050°C and 1150°C ) is achieved, conducting the isothermal annealing treatment ( Lysáček, Abstract, The polycrystalline silicon films deposited at 640°C are stable upon annealing to temperatures up to approximately 900°C. Primary recrystallization has been observed between 900°C and 1150°C ) to the semiconductor substrate I, wherein the second temperature is 1050°C-1200°C ( Lysáček, page 3, line 9, Significant increase in the grain size was observed after annealing at 1050°C and 1150°C ).
Regarding Claim 5 ( Currently Amended ), Meguro, Lysáček, and Gao teach the process as claimed in claim 1, on which this claim is depend, Meguro and Gao further teach:
wherein the step S4 comprises:
conducting the first reduction of temperature ( Gao, Abstract: (2) annealing: the preparing of silicon wafer in a reaction chamber, the preserving temperature at 650-1050 °C centigrade for 10-30min; 10-15 minutes cooling to less than or equal to 300 °C, taking out the silicon epitaxial reaction chamber; claim 3, wherein the annealing temperature in step (2) is 850-950 degrees centigrade ) while maintaining the atmosphere of hydrogen in the CVD reaction chamber; and
conducting the first natural cooling to the semiconductor substrate I under ambient environment, wherein the first natural cooling has a cooling rate of 0.5°C/s - 3°C/s ( Based on information from Gao ( Abstract and claim 3 ): the cooling rate from 650 °C to 300 °C in 10 mins is 0.58 °C / s; the cooling rate from 1050 °C to 300 °C in 10 mins is 1.25 °C / s; the cooling rate from 900 °C to 300 °C in 10 mins is 1 °C / s. Therefore, in average, the cooling rate is smaller than the first natural cooling rate ).
Regarding Claim 6 ( Original ), Meguro, Lysáček, and Gao teach the process as claimed in claim 1, on which this claim is depend, Meguro further teaches:
wherein the step S5 comprises:
reducing the thickness of the first polysilicon layer by a natural placement, and
forming the second surface oxide layer on the first polysilicon layer, wherein the second surface oxide layer has a thickness of 1 nm - 1.5 nm ( Meguro, [0060], the thickness of the oxide film to be formed is preferably thinner, for example, the thickness of 0.3 nm or more and 10 nm or less is preferable, since the interposed oxide film 20 between the base wafer 11 and the polycrystalline silicon layer 12 can influence property of an RF device ); or
reducing the thickness of the first polysilicon layer by an oxidation step under an atmosphere of dry oxygen and/or wet oxygen, and forming the second surface oxide layer on the first polysilicon layer, wherein the first polysilicon layer has a reduced thickness of 1 nm - 1.5 nm ( Meguro, [0060], the thickness of the oxide film to be formed is preferably thinner, for example, the thickness of 0.3 nm or more and 10 nm or less is preferable, since the interposed oxide film 20 between the base wafer 11 and the polycrystalline silicon layer 12 can influence property of an RF device ).
Regarding Claim 7 ( Original ), Meguro, Lysáček, and Gao teach the process as claimed in claim 1, on which this claim is depend, Meguro further teaches:
the step S6 comprises:
transferring the semiconductor substrate I into the CVD reaction chamber, and
conducting a third heating to achieve the third temperature ( Meguro, [0025], the polycrystalline silicon layer is deposited at a temperature of 900° C or more );
at the third temperature, growing the second polysilicon layer on the surface oxide layer by atmospheric pressure chemical vapor deposition to form the semiconductor substrate II; and
wherein the third heating is under hydrogen atmosphere, and the atmosphere is converted to a mixed gas containing hydrogen and trichlorosilane while the third temperature is achieved ( Meguro, [0025], the polycrystalline silicon layer is deposited at a temperature of 900° C or more ).
Regarding Claim 8 ( Original ), Meguro, Lysáček, and Gao teach the process as claimed in claim 7, on which this claim is depend, Meguro further teaches:
the third temperature is 900°C-1000°C ( Meguro, [0025], the polycrystalline silicon layer is deposited at a temperature of 900° C or more ).
Meguro fails to teach:
wherein the hydrogen has a gas flow of 40 slm- 80 slm, the mixed gas has the hydrogen gas flow of 40 slm- 80 slm and the trichlorosilane gas flow of 3 slm- 12 slm,
However, Wada teaches:
wherein the hydrogen has a gas flow of 40 slm- 80 slm ( Wada, [0164], flow rate of carrier gas is appropriately adjusted within a range of 40 to 80 slm; Table 1, Carrier ( H2 ) Flow Rate ( slm ) is 85 ), the mixed gas has the hydrogen gas flow of 40 slm- 80 slm ( Wada, [0164], flow rate of carrier gas is appropriately adjusted within a range of 40 to 80 slm; Table 1, Carrier ( H2 ) Flow Rate ( slm ) is 85 ) and the trichlorosilane gas flow of 3 slm- 12 slm ( Wada, [0102], trichlorosilane (source gas flow rate to CVD reactor: 10 slm) … flow rate: trichlorosilane 5 slm …),
Meguro, Lysáček, Gao and Wada are all considered to be analogous to the claimed invention because they are forming a semiconductor substrate. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Meguro, Lysáček, Gao ( first temperature, second temperature and conducting an isothermal annealing treatment, specific slow rate of cooling from the second temperature to the first temperature ), to incorporate the teachings of Wada ( a mixed gas containing hydrogen and trichlorosilane with specific flow rates ), to implement the flatness of polycrystalline silicon layer. Doing so would provide specific composition and flow rate of carrier gases, and therefore the flatness of polycrystalline silicon layer can be improved.
Regarding Claim 9 ( Original ), Meguro, Lysáček, and Gao teach the process as claimed in claim 7, on which this claim is depend, Lysáček further teaches:
wherein the step S7 comprises:
conducting a fourth heating and simultaneously converting the atmosphere to hydrogen gas;
while the fourth temperature is achieved, conducting the isothermal annealing treatment ( Lysáček, Abstract, The polycrystalline silicon films deposited at 640°C are stable upon annealing to temperatures up to approximately 900°C. Primary recrystallization has been observed between 900°C and 1150°C ) to the semiconductor substrate II, wherein the fourth temperature is 1050°C-1200°C ( Lysáček, page 3, line 9, Significant increase in the grain size was observed after annealing at 1050°C and 1150°C ).
Regarding Claim 10 ( Currently Amended ), Meguro, Lysáček, and Gao teach the process as claimed in claim 1, on which this claim is depend, Gao further teaches:
wherein the step S8 comprises:
conducting the second reduction of temperature ( Gao, Abstract: (2) annealing: the preparing of silicon wafer in a reaction chamber, the preserving temperature at 650-1050 °C centigrade for 10-30min; 10-15 minutes cooling to less than or equal to 300 °C, taking out the silicon epitaxial reaction chamber; claim 3, wherein the annealing temperature in step (2) is 850-950 degrees centigrade ) while maintaining the atmosphere of hydrogen in the CVD reaction chamber; and
conducting the second natural cooling to the semiconductor substrate II under ambient environment, wherein the second natural cooling has a cooling rate of 0.5°C/s - 3°C/s ( Based on information from Gao ( Abstract and claim 3 ): the cooling rate from 650 °C to 300 °C in 10 mins is 0.58 °C / s; the cooling rate from 1050 °C to 300 °C in 10 mins is 1.25 °C / s; the cooling rate from 900 °C to 300 °C in 10 mins is 1 °C / s. Therefore, in average, the cooling rate is smaller than the first natural cooling rate ).
Regarding Claim 11 ( Original ), Meguro, Lysáček, and Gao teach the process as claimed in claim 1, on which this claim is depend, Meguro, Lysáček, and Gao further teach:
a semiconductor substrate characterized by: the semiconductor substrate is prepared by claim 1 ( As shown above in claim 1 ).
Response to Arguments
Applicant’s argument for claim 1: page 6, line 7 from bottom, cited “ the present invention provides a distinct concept, which is to form plural polysilicon layers instead of the conventional single polysilicon layer. ”
Examiner’s response: please refer to claim 1 in Claim Rejections - 35 USC § 103 of this office action, Meguro teaches “ S2: forming a first polysilicon layer ( Meguro, Abstract, depositing a polycrystalline silicon layer ) on the first surface oxide layer at a first temperature ( Meguro, [0025], the polycrystalline silicon layer is deposited at a temperature of 900° C or more ) to form a semiconductor substrate I; ”. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to repeat the same or similar process if multiple polysilicon layers are required, as shown in claim 1, cited “ S6: forming a second polysilicon layer ( Meguro, Abstract, depositing a polycrystalline silicon layer ) on the second surface oxide layer at a third temperature ( Meguro, [0025], the polycrystalline silicon layer is deposited at a temperature of 900° C or more ) to form a semiconductor substrate II; ”.
Applicant’s argument for claim 1: page 6, line 4 from bottom, cited “ It should be emphasized that the process of the present application is not merely and simply repeating the conventional formation steps of polysilicon layer. Specifically, in the present application, the process comprises at least two complete cycles to form at least two polysilicon layers, and each polysilicon layer is formed by a complete cycle of the epitaxy growth step, the isothermal annealing step, the specific cooling step, the natural cooling step and the oxidation treatment. In the amended claim 1 of the present application, the cooling step is further defined in S4 and S8 that "the specific cooling step" is conducted in a CVD reaction chamber and "the natural cooling step" is conducted in an ambient environment. Such cooling arrangements can reduce thermal mismatch between the layers. ”
Examiner’s response: please refer to claim 1 in Claim Rejections - 35 USC § 103 of this office action. First, since Meguro, Lysáček, and Gao teach “ S1 to S4 ” in claim 1, therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to duplicate the teachings of Meguro, Lysáček, and Gao for “ S1 to S4 ” to be the teachings for “ S5 to S8 ” in claim 1, if multiple polysilicon layers are required.
Second, “ the specific cooling step, the natural cooling step ” are mapped by Gao, claim 1, cited “ However, Gao teaches:
S4: conducting a first reduction of temperature ( Gao, Abstract: (2) annealing: the preparing of silicon wafer in a reaction chamber, the preserving temperature at 650-1050 °C centigrade for 10-30min; 10-15 minutes cooling to less than or equal to 300 °C, taking out the silicon epitaxial reaction chamber; claim 3, wherein the annealing temperature in step (2) is 850-950 degrees centigrade ) from the second temperature to the first temperature in a CVD reaction chamber, then transferring the semiconductor substrate I to an ambient environment and conducting a first natural cooling to the semiconductor substrate I while the first temperature is achieved, wherein the first reduction of temperature ( … ) has a reduction rate smaller than that of the first natural cooling ( Based on information from Gao ( Abstract and claim 3 ): the cooling rate from 650 °C to 300 °C in 10 mins is 0.58 °C / s; the cooling rate from 1050 °C to 300 °C in 10 mins is 1.25 °C / s; the cooling rate from 900 °C to 300 °C in 10 mins is 1 °C / s ); ”. Therefore, “ the specific cooling step ” is from 650-1050 °C to 300 °C in a reaction chamber; “ the natural cooling step ” is from 300 °C to room temperature, which is a natural cooling process, because the substrate had been taken out the silicon epitaxial reaction chamber.
Third, “ Such cooling arrangements can reduce thermal mismatch between the layers ” is mapped as shown in claim 1, cited “ Doing so would provide specific slow rate of cooling from the second / fourth temperature to the first / third temperature, and therefore the warpage quality ( Gao, Abstract, The method of the invention can make the warpage (WARP) silicon epitaxial wafer is not qualified after the annealing treatment to be qualified, and can be compatible with the epitaxial process, effectively improving the warpage of the silicon epitaxial wafer ) of polycrystalline silicon layer can be improved. ”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
Prosecution Insights