DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/13/2026 has been entered.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on 5/13/2026. Claim 1 has been amended. No new claims have been added. Claims 2-3 have been cancelled. Claims 8-16 were withdrawn. Currently, claims 1, 4-7, and 17-18 are pending.
Response to Arguments
Applicant’s arguments with respect to amended claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4, 6, and 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 20140138765).
Regarding claim 1, Lee teaches, in Figs. 7A-8C, a semiconductor device ([0015]), comprising:
PNG
media_image1.png
708
660
media_image1.png
Greyscale
Lee Fig. 7B
a dielectric pad (lowest 34, [0075]) over a lower structure (30/31/32, [0047]-[0048]) (see Figs. 7C and 8C);
a contact portion (CT1, see Fig. 7B, [0021]) positioned at a higher level than the dielectric pad (lowest 34) (see Fig. 8C), the contact portion (CT1) including a first word line stack pad ([0022], [0072], see Fig. 8C, alternating 36/43; see Figs. 7B-7C, to the left of 44) and a second word line stack pad (see Fig. 8C, alternating 36/43; see Figs. 7B-7C, to the right of 44); and
a slit structure including a plurality of slits (42 and 44, [0063], [0070]) extending vertically from the dielectric pad (34) to support the first word line stack pad and the second word line stack pad (see Fig. 7C),
wherein the dielectric pad (34) includes:
a plurality of line pads that are parallel to each other; and a plurality of auxiliary pads coupling the line pads to each other, wherein the line pads and the auxiliary pads are positioned at the same level to have a mesh-shape (see annotated Fig. 7B above; while Fig. 7B shows the 43 [CG,USG] layer, Fig. 7C shows that slits 42 and 44 go through bottom layer 34 similar to the way they go through 43 [LSG], thus forming the mesh-shape).
Regarding claim 4, Lee further teaches that each of the first word line stack pad and the second word line stack pad includes a plurality of word line pads (pairs of 36/43) that are stacked in a (vertical) direction perpendicular to a (top) surface of the dielectric pad (see Fig. 8C), and
that the stack of the word line pads has a step-type structure (see Fig. 8C).
Regarding claim 6, Lee further teaches that a cell array portion (CL, [0021]) extending laterally from the contact portion (CT1) and including a first word line stack ([0022], [0072], see Fig. 7C, alternating 36/43 to the left of 44) and a second word line stack (see Fig. 7C, alternating 36/43 to the right of 44), wherein
a first word line pad is defined at (left) end portions of the first word line stack ([0056], between leftmost 44 and leftmost holes H), and
a second word line pad is defined at (right) end portions of the second word line stack ([0056], between rightmost 44 and rightmost holes H).
Regarding claim 17, Lee further teaches that the step-type structure is in contact with the dielectric pad (lowest 34) (see Fig. 8C).
Regarding claim 18, Lee further teaches a plurality of contact plugs (CP1, CP2, and CP3, [0071]) directly coupled to the step-type structure (see Fig. 8C).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20140138765) in view of Kim et al. (US 10978384).
Regarding claim 5, Lee teaches the limitations of claim 4. Lee does not teach that each of the word line pads include: a first pad and a second pad that are stacked in a direction perpendicular to the surface of the dielectric pad; and a word line pad interposed between the first pad and the second pad.
In a similar field of endeavor, Kim teaches, in Figs. 2 and 7A, that each of the word line pads (ML, labelled as 60a in Fig. 7A; col. 13, lines 45-55; col. 11, lines 60-67) include: a first pad (P1) and a second pad (P3) that are stacked in a direction (vertical direction) perpendicular to the surface of the dielectric pad (Fig. 7A, interlayer insulation film); and a word line pad (P2) interposed between the first pad (P1) and the second pad (P3) (see Figs. 2 and 7A), in order to “provide multi-layer conducting lines configured to reduce a signal delay and integrated circuits of a high integration degree and including the multi-layer conducting lines” (col. 1, lines 35-45).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the word line pads of Lee with the word line pads of Kim, in order to provide multi-layer conducting lines configured to reduce a signal delay and integrated circuits of a high integration degree (col. 1, lines 35-45).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20140138765) in view of Karda et al. (US 10381357).
Regarding claim 7, Lee teaches the limitations of claim 6. Lee does not teach that the cell array portion includes: vertical bit lines disposed between the first word line stack and the second word line stack; active layers respectively coupled to the vertical bit lines; and capacitors including storage nodes that are respectively coupled to the active layers, wherein the active layers are oriented laterally between the vertical bit lines and the capacitors, and wherein each of the first and second word line stacks includes word lines extending laterally in a direction crossing the active layers.
In a similar field of endeavor, Karda teaches, in Figs. 8 and 11, that the cell array portion includes:
vertical bit lines (76a/78a and 76b/78b; col. 6, lines 20-30) disposed between the first word line stack (38) and the second word line stack (38a) (see Fig. 11; col. 10, lines 20-25);
active layers (51/50/52 and 55/54/56, 59/58/60, and 63/62/64; col. 4, lines 20-40) respectively coupled to the vertical bit lines (76a/73a and 76b/73b) (see Fig. 8); and
capacitors (30a and 30b; Fig. 8; col. 11, lines 55-65) including storage nodes (32; col. 13, lines 10-20) that are respectively coupled to the active layers (see Fig. 8),
wherein the active layers are oriented laterally between the vertical bit lines (76a/78a and 76b/78b) and the capacitors (30a, 30b) (see Fig. 8), and
wherein each of the first (38) and second word line stacks (38a) includes word lines extending laterally in a direction (horizontally) crossing the active layers (see Fig. 11),
in order to “develop memory cell configurations which alleviate … floating body effects associated with the transistors T1 and T2, and to develop memory arrays incorporating such memory cell configurations” (col. 2, lines 35-45).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the cell array portion configuration Lee with the cell array portion configuration of Karda, in order to develop memory cell configurations which alleviate floating body effects and to develop memory arrays incorporating such memory cell configurations (col. 2, lines 35-45).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIKA HEERA SON whose telephone number is 703-756-4644. The examiner can normally be reached Monday - Friday 12:30-9 PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached on 571-270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIKA H SON/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
Prosecution Insights