DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on 1/14/2026. Claims 1 and 6 have been amended. Claims 17-18 have been added. Claims 8-16 were withdrawn. Currently, claims 1-7 and 17-18 are pending.
Applicant’s amendment to claim 6 successfully overcomes the 112(b) rejection of claim 6 and dependent claim 7 set forth in the previous Office Action.
Response to Arguments
Applicant’s arguments filed 1/14/2026 have been fully considered but they are not persuasive.
The Applicants argue:
However, the optional semiconductor material layer 10 of Shimabukuro is formed of a semiconductor material, not a dielectric material. Accordingly, Shimabukuro fails to disclose, teach, or even suggest the feature of the claimed invention in which "the bottom surface of the slit structure (WSIL, SSL, LSL) is in contact with the dielectric pad (PDIL)".
The Examiner responds:
The Examiner respectfully disagrees. As set forth in the previous Office Action and in the rejection below, the dielectric pad of Lim (9/13) is used to modify the semiconductor pad of Shimabukuro.
The Applicants argue:
Referring to FIG.5 and [0025] of Lim below, the upper substrate 12 is in contact with lower insulating layer 9 and the gap-fill insulating layer 13. Therefore, even if Shimabukuro and Lim are combined, the features of the present invention are not derived.
The Examiner responds:
The Examiner respectfully disagrees. As set forth in the previous Office Action and in the rejection below, the dielectric pad of Lim is (9/13) and does not include (12), even though 12 contacts 9/13.
Thus, Shimabukuro in view of Lim renders obvious the limitations of amended claim 1. As a result, the rejection of claims 1-7 is maintained.
All other arguments have been fully addressed in prior Office Actions or in the rejections set forth below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Shimabukuro et al. (US 12213320) in view of Lim et al. (US 11271003).
Regarding claim 1, Shimabukuro teaches, in Figs. 16A-16B, a semiconductor device comprising:
a semiconductor pad (10; col. 5, lines 60-65) over a lower structure (9) (see Fig. 16A);
a contact portion (300; Fig. 16B; col. 6, line 65 – col. 7, line 5) positioned at a higher level than the semiconductor pad (10) (see Fig. 16A), the contact portion including a first word line stack pad (Fig. 16B, above 74/76) and a second word line stack pad (Fig. 16B, below 74/76); and
a slit structure including a plurality of slits (20; col. 15, lines 30-40) extending vertically from the semiconductor pad (10) to support the first word line stack pad (Fig. 16B, above 74/76) and the second word line stack pad (Fig. 16B, below 74/76) (see Fig. 16A),
wherein a bottom surface of the slit structure (20) is in contact with the pad (10) (see Fig. 16A).
Shimabukuro does not teach that the pad over a lower structure is dielectric.
In a similar field of endeavor, Lim teaches, in Fig. 3, that the pad (9/13) over a lower structure (5) is dielectric (col. 4, lines 30-40), in order to “have improved integration density” of the semiconductor device (col. 1, lines 30-35; col. 20, lines 55-65).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the pad of Shimabukuro with the dielectric pad of Lim, in order to improve integration density of the semiconductor (col. 1, lines 30-35; col. 20, lines 55-65).
Regarding claim 2, Shimabukuro in view of Lim teaches the limitations of claim 1. Lim further teaches that the dielectric pad (9/13) includes:
a plurality of line pads that are parallel to each other (see Fig. 2; see also Figs. 3, 7, and 9 for cross-sectional diagrams of Fig. 2; 13 and portions of 9 covered by 13; 13 are rectangular line pads with borders that surround the borders of IA1 and IA2); and
a plurality of auxiliary pads (portions of 9 not covered by 13) coupling the line pads to each other (see Fig. 2; see also Figs. 3, 7, and 9).
Regarding claim 3, Shimabukuro in view of Lim teaches the limitations of claim 2. Lim further teaches that the line pads (13 and 9 covered by 13) and the auxiliary pads (portions of 9 not covered by 13) are positioned at the same level (see Fig. 3).
Regarding claim 4, Shimabukuro in view of Lim teaches the limitations of claim 1. Shimabukuro further teaches, in Fig. 16A, that each of the first word line stack pad (Fig. 16B, above 74/76) and the second word line stack pad (Fig. 16B, below 74/76) includes a plurality of word line pads (46; col. 27, lines 50-60) that are stacked in a direction (vertical direction) perpendicular to a surface of the dielectric pad (10), and that the stack of the word line pads (46) has a step-type structure (see Fig. 16A).
Regarding claim 6, Shimabukuro in view of Lim teaches the limitations of claim 1. Shimabukuro further teaches, in Figs. 16A-16B, a cell array portion (100; Fig. 16B; col. 10, lines 15-25) extending laterally from the contact portion (300) and including a first word line stack (Fig. 16B, above 74/76) and a second word line stack (Fig. 16B, below 74/76), wherein
a first word line pad (46, Fig. 16A) is defined at end portions of the first word line stack (see Fig. 16A, left end), and a second word line pad (46) is defined at end portions of the second word line stack (see Fig. 16A, left end).
Regarding claim 17, Shimabukuro in view of Lim teaches the limitations of claim 4. Shimabukuro further teaches, in Fig. 16A, that the step-type structure (stack of word line pads 46) is in contact with the dielectric pad (10) (see Fig. 16A).
Regarding claim 18, Shimabukuro in view of Lim teaches the limitations of claim 17. Shimabukuro further teaches a plurality of contact plugs (86; col. 27, lines 45-60) directly coupled to the step-type structure (stack of word line pads 46) (see Fig. 16A).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Shimabukuro et al. (US 12213320) in view of Lim et al. (US 11271003), and further in view of Kim et al. (US 10978384).
Regarding claim 5, Shimabukuro in view of Lim teaches the limitations of claim 4. Shimabukuro in view of Lim does not explicitly teach that each of the word line pads include: a first pad and a second pad that are stacked in a direction perpendicular to the surface of the dielectric pad; and a word line pad interposed between the first pad and the second pad.
In a similar field of endeavor, Kim teaches, in Figs. 2 and 7A, that each of the word line pads (ML, labelled as 60a in Fig. 7A; col. 13, lines 45-55; col. 11, lines 60-67) include: a first pad (P1) and a second pad (P3) that are stacked in a direction (vertical direction) perpendicular to the surface of the dielectric pad (Fig. 7A, interlayer insulation film); and a word line pad (P2) interposed between the first pad (P1) and the second pad (P3) (see Figs. 2 and 7A), in order to “provide multi-layer conducting lines configured to reduce a signal delay and integrated circuits of a high integration degree and including the multi-layer conducting lines” (col. 1, lines 35-45).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the word line pads of Shimabukuro in view of Lim with the word line pads of Kim, in order to provide multi-layer conducting lines configured to reduce a signal delay and integrated circuits of a high integration degree (col. 1, lines 35-45).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Shimabukuro et al. (US 12213320) in view of Lim et al. (US 11271003), and further in view of Karda et al. (US 10381357).
Regarding claim 7, Shimabukuro in view of Lim teaches the limitations of claim 6. Shimabukuro in view of Lim does not explicitly teach that the cell array portion includes: vertical bit lines disposed between the first word line stack and the second word line stack; active layers respectively coupled to the vertical bit lines; and capacitors including storage nodes that are respectively coupled to the active layers, wherein the active layers are oriented laterally between the vertical bit lines and the capacitors, and wherein each of the first and second word line stacks includes word lines extending laterally in a direction crossing the active layers.
In a similar field of endeavor, Karda teaches, in Figs. 8 and 11, that the cell array portion includes:
vertical bit lines (76a/78a and 76b/78b; col. 6, lines 20-30) disposed between the first word line stack (38) and the second word line stack (38a) (see Fig. 11; col. 10, lines 20-25);
active layers (51/50/52 and 55/54/56, 59/58/60, and 63/62/64; col. 4, lines 20-40) respectively coupled to the vertical bit lines (76a/73a and 76b/73b) (see Fig. 8); and
capacitors (30a and 30b; Fig. 8; col. 11, lines 55-65) including storage nodes (32; col. 13, lines 10-20) that are respectively coupled to the active layers (see Fig. 8),
wherein the active layers are oriented laterally between the vertical bit lines (76a/78a and 76b/78b) and the capacitors (30a, 30b) (see Fig. 8), and
wherein each of the first (38) and second word line stacks (38a) includes word lines extending laterally in a direction (horizontally) crossing the active layers (see Fig. 11),
in order to “develop memory cell configurations which alleviate … floating body effects associated with the transistors T1 and T2, and to develop memory arrays incorporating such memory cell configurations” (col. 2, lines 35-45).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the cell array portion configuration of Shimabukuro in view of Lim with the cell array portion configuration of Karda, in order to develop memory cell configurations which alleviate floating body effects and to develop memory arrays incorporating such memory cell configurations (col. 2, lines 35-45).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIKA HEERA SON whose telephone number is (703)756-4644. The examiner can normally be reached Monday - Friday 11:30-8:30 PM ET.
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/ERIKA H SON/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893