Prosecution Insights
Last updated: July 17, 2026
Application No. 18/073,931

METHOD OF MANUFACTURING SEMICONDUCTOR CHIP INCLUDING DICING SUBSTRATE

Non-Final OA §103
Filed
Dec 02, 2022
Priority
Jul 13, 2022 — RE 10-2022-0086556
Examiner
PETERSON, ERIK T
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SK hynix Inc.
OA Round
3 (Non-Final)
77%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
89%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
279 granted / 361 resolved
+9.3% vs TC avg
Moderate +12% lift
Without
With
+11.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
40 currently pending
Career history
403
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
69.0%
+29.0% vs TC avg
§102
10.4%
-29.6% vs TC avg
§112
12.3%
-27.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 361 resolved cases

Office Action

§103
DETAILED ACTION A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 13, 2026, has been entered. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered. Claim Rejections - 35 USC § 103 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claims 1, 2, 4-6, 13, 15-18, 21, and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (US 2020/0091100). (Re Claim 1) Han teaches a method of manufacturing a semiconductor chip, comprising (see Figs. 1, 2, 5G-5I) and corresponding text: forming, on a first surface of a substrate, a first notch portion and a second notch portion that are spaced apart from each other along a first dicing line (see Figs. 1, 2, 5H, and 5I, first and second notch portions correspond to any two openings OP/OP2 formed at each intersection of the dicing grid in the first surface of the substrate, “substrate” corresponds to all layers present); forming modified patterns within the substrate (Fig. 5H, modified region SP, ¶74); and dicing the substrate by propagating cracks into the substrate from the modified patterns (Fig. 5I, ¶75). wherein each of the first notch portion and the second notch portion has wedge-shaped portion, and the first notch portion and the second notch are arranged such that noses of the wedge-shaped portions face each other in a plane perpendicular to the substrate (see Figs. 5I-5J, the side surface of the opening in 153 and 130 is angled/sloped and thus meets the claimed wedge-shaped portion noses facing each other, they are facing each other in the Fig. 5I cross section which is along the I-I’ section which is in the D1-D3 plane, the substrate is in the D1-D2 plane, see Figs. 1-2 showing the axes, the two planes are perpendicular). While Han does not recite “propagating cracks”, this is obvious in light of the stealth laser dicing process disclosed (¶¶74-75). When a force is applied to the wafer having the modified regions, cracks will propagate through the wafer from each modified region to singulate the wafer. This is how stealth dicing works. Thus, the claimed propagating cracks will obviously occur whether expressly stated or not. (Re Claim 2) wherein the substrate comprises: a semiconductor base(100); an organic matter layer (153 is polyimide, ¶71) that is formed over the semiconductor base; and an active layer (the layers between 153 and 100) that is formed between the organic matter layer and the semiconductor base, wherein forming the first notch portion and the second notch portion comprises forming penetration holes that penetrate the organic matter layer by removing some portions of the organic matter layer (Figs. 5F-5I, notches are formed through the organic layer 153, i.e. penetration holes). (Re Claim 4) wherein forming the penetration holes comprises partially removing some portion of the active layer (see Figs. 5A-5I, portions of the active layer are removed). (Re Claim 5) wherein the active layer comprises a plurality of conductive layers and a plurality of interlayer insulating layers (conductive layers and insulating layers: 110, 121a, 120, 123a, 103, 130). (Re Claim 6) further comprising forming, on the first surface of the substrate, a third notch portion that is spaced apart from the first notch portion along a second dicing line that intersects the first dicing line (see Figs. 1 and 2, notches OP/OP2 are formed at every intersection of the dicing grid, third notch selected from another intersection). (Re Claim 13) wherein forming the modified patterns comprises irradiating, with a laser, portions of the substrate at which the modified patterns are to be disposed (Fig. 5H and ¶¶74-75). (Re Claim 15) Han teaches a method of manufacturing a semiconductor chip, comprising (see Figs. 1, 2, 5G-5I and corresponding text): forming a substrate which comprises a semiconductor base (100) in which first and second scribe lane regions intersect (see Figs. 1-2), an active layer (layers between 100 and 153) that is formed on the semiconductor base, and an organic matter layer (153 is polyimide, ¶71); forming a first notch portion and a second notch portion that are spaced apart from each other in the first scribe lane region and that penetrate the organic matter layer (see Figs. 1, 2, and 5H, first and second notch portions correspond to any two openings OP/OP2 formed at each intersection of the dicing grid, notches/openings penetrate layer 153); forming modified patterns within the semiconductor base along the first scribe lane region (Fig. 5H, modified region SP, ¶74); and dicing the substrate by propagating cracks into the substrate from the modified patterns (Fig. 5I, ¶75), wherein each of the first notch portion and the second notch portion has wedge-shaped portion, and the first notch portion and the second notch are arranged such that noses of the wedge-shaped portions face each other in a plane perpendicular to the substrate (see Figs. 5I-5J, the side surface of the opening in 153 and 130 is angled/sloped and thus meets the claimed wedge-shaped portion noses facing each other, they are facing each other in the Fig. 5I cross section which is along the I-I’ section which is in the D1-D3 plane, the substrate is in the D1-D2 plane, see Figs. 1-2 showing the axes, the two planes are perpendicular). While Han does not recite “propagating cracks”, this is obvious in light of the stealth laser dicing process disclosed (¶¶74-75). When a force is applied to the wafer having the modified regions, cracks will propagate through the wafer from each modified region to singulate the wafer. This is how stealth dicing works. Thus, the claimed propagating cracks will obviously occur whether expressly stated or not. (Re Claim 16) wherein the first notch portion and the second notch portion are formed to extend into the active layer (see Fig. 5G). (Re Claim 17) wherein the first notch portion and the second notch portion are disposed at portions in which the first and second scribe lane regions intersect (see Figs. 1-2). (Re Claim 18) further comprising forming, in a second scribe lane region, a third notch portion that is spaced apart from the first notch portion (see Figs. 1 and 2, notches OP/OP2 are formed at every intersection of the dicing grid, third notch selected from another intersection). (Re Claim 21) wherein the active layer comprises a plurality of conductive layers and a plurality of interlayer insulating layers (conductive layers and insulating layers: 110, 121a, 120, 123a, 103, 130). (Re Claim 27) wherein forming the modified patterns comprises irradiating, with a laser, portions of the semiconductor base at which the modified patterns are to be disposed (Fig. 5H, modified pattern SP, ¶¶74-75). Claims 3 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (US 2020/0091100) in view of Lee (US 2021/0210458). (Re Claim 3) wherein the organic matter layer comprises poly(imide-isoindoloquinazolinedione). (Re Claim 19) wherein the organic matter layer comprises poly(imide-isoindoloquinazolinedione). Han discloses a photosensitive polyimide however is silent regarding a specific polyimide such as PIQ. A PHOSITA would be motivated to look to related art to teach a specific photosensitive polyimide to use. Related art from Lee discloses PIQ (¶30) is a photosensitive polyimide suitable for semiconductor devices. A PHOSITA would find it obvious to use the photosensitive polyimide PIQ disclosed by Lee for the photosensitive polyimide disclosed by Han. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960). Claims 12, 14, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (US 2020/0091100) in view of Abe et al. (US 2007/0066044). (Re Claim 12) wherein the modified patterns are formed to be arranged in a line along the first dicing line. While Han only shows one modified region SP, a PHOSITA would understand that in a conventional stealth dicing process, a plurality of modified regions are formed along every dicing line. Related art from Abe shows a conventional stealth dicing process wherein a plurality of modified regions are formed along every dicing line (see Figs. 10-11). In view of Abe, it is obvious for Han to similarly form a plurality of modified regions along every dicing line in order to reliably singulate the wafer of devices. (Re Claim 14) wherein dicing the substrate comprises grinding a second surface that is opposite to the first surface of the substrate. (Re Claim 20) wherein dicing the substrate further comprises grinding a surface of the semiconductor base, which is opposite to the organic matter layer. Han is silent regarding grinding the substrate. A PHOSITA would recognize backside grinding/thinning a substrate is common practice in the industry and provides many well-known advantages. Thinning or grinding semiconductor wafers enhances device performance through improved thermal management, higher electrical efficiency, and greater mechanical flexibility, while also enabling advanced compact packaging and reducing manufacturing costs. Related art from Abe discloses grinding the substrate from the backside (Fig. 7 and ¶81). A PHOSITA would find it obvious to grind the Han’s substrate, as taught by Abe, for the advantages discussed above. Response to Arguments Applicant's arguments filed April 13, 2026, have been fully considered but they are not persuasive. Applicant asserts Han fails to teach the wedge-shaped noses facing each other in a plane perpendicular to the substrate. The Examiner respectfully disagrees. See Figs. 5I-5J showing the side surfaces of the opening in 153 and 130 is angled/sloped and thus meets the claimed noses of wedge-shaped portions facing each other. They are facing each other in the Fig. 5I cross section which is along the I-I’ section which is in the D1-D3 plane, while the substrate extends in the D1-D2 plane, see Figs. 1-2 showing the axes, the two planes are perpendicular. Applicant’s remarks regarding the planes and the substrate are confusing (remarks p. 8) and appear to be wrong in view of the specification. Applicant’s substrate 100 is understood to extend in the X-Y plane as shown in Fig. 12, however one could construe the substrate 100 as existing and extending in all planes, e.g. X-Y, X-Z, and Y-Z. The claimed plane(s) are not well defined, nor is it particularly clear what Applicant intends to be perpendicular to the substrate. In view of Fig. 12, it appears the Z-direction is perpendicular to the plane of the substrate 100. Applicant should define the relevant planes/directions with respect to the wedge-shape portions/noses and substrate more clearly. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERIK T. K. PETERSON/ Primary Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Show 3 earlier events
Jun 23, 2025
Examiner Interview Summary
Oct 31, 2025
Non-Final Rejection mailed — §103
Jan 30, 2026
Response Filed
Feb 20, 2026
Final Rejection mailed — §103
Apr 13, 2026
Response after Non-Final Action
May 20, 2026
Request for Continued Examination
May 22, 2026
Response after Non-Final Action
Jun 05, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12672497
WAFER WITH TEST STRUCTURE AND METHOD OF DICING WAFER
4y 11m to grant Granted Jun 30, 2026
Patent 12660541
SURFACE PROCESSING METHOD AND PROCESSING SYSTEM
4y 0m to grant Granted Jun 16, 2026
Patent 12660543
METHOD FOR MAKING SEMICONDUCTOR PACKAGES
3y 4m to grant Granted Jun 16, 2026
Patent 12641849
LOW TEMPERATURE N-TYPE CONTACT EPI FORMATION
3y 2m to grant Granted May 26, 2026
Patent 12635245
DISPLAY PANEL AND DISPLAY DEVICE
3y 4m to grant Granted May 19, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

3-4
Expected OA Rounds
77%
Grant Probability
89%
With Interview (+11.6%)
2y 7m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 361 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month