DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 6, and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al (U.S. Pub #2021/0210534).
With respect to claim 1, Chen teaches an image sensor comprising:
a pixel division structure (Fig. 2, 204; Paragraph 28) extending through a substrate (Fig. 2-4, 102) in a vertical direction perpendicular to an upper surface of the substrate, the pixel division structure defining unit pixel regions in which unit pixels are respectively formed;
a light sensing element (Figs. 2-4, 302 and Paragraph 39) in each of the unit pixel regions;
a transistor (Fig. 2-4, 101) on the substrate;
a color filter array layer (Fig. 2-4, 308 and Paragraph 40) under the substrate, the color filter array layer including color filters; and
a microlens (Figs. 2-4, 306 and Paragraph 40) under the color filter array layer,
wherein the transistor comprises a gate structure (Figs. 2-4, 108a+108c) on an active fin (Figs. 2-4, 114) protruding from the upper surface of the substrate, and source/drain regions (Fig. 2, 116/118 and Paragraph 24; Fig. 3-4, 302/304) at portions of the active fin adjacent to the gate structure.
With respect to claim 6, Chen teaches that the gate structure is a first gate structure (Fig 4, 108a), and the image sensor further comprises:
(Paragraph 38 and 44, Note that the structure of Figs. 1-2 can be provided as the source follower transistor of the pixel circuit, and the structure of Fig. 4 can be formed as the transfer transistor)
a second gate structure (Fig. 4, 108e) contacting an upper surface of the light sensing element; and a floating diffusion (FD) region (Fig. 4, 304 and Paragraph 38-39) at an upper portion of the substrate and contacting the second gate structure,
wherein the second gate structure, the light sensing element (Fig. 4, 302) and the FD region configure a transfer transistor (Fig. 4, 101 and Paragraph 38).
With respect to claim 7, Chen teaches that the transistor is one of a reset transistor, a source follower transistor (Paragraph 44) and a select transistor.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 rejected under 35 U.S.C. 103 as being unpatentable over Chen et al (U.S. Pub #2021/0210534), in view of Zang et al (U.S. Pub #2022/0375977).
With respect to claim 8, Chen does not teach that the active fin is one of a plurality of active fins spaced apart from each other in a second direction parallel to the upper surface of the substrate, each of the plurality of active fins extending in a first direction parallel to the upper surface of the substrate and crossing the second direction, and wherein the gate structure extends in the second direction on ones of the plurality of active fins.
Zang teaches an active fin being one of a plurality of active fins (Fig. 3A, 314) spaced apart from each other in a second direction parallel to the upper surface of the substrate, each of the plurality of active fins extending in a first direction parallel to the upper surface of the substrate and crossing the second direction, and wherein the gate structure (Fig. 3A, 320) extends in the second direction on ones of the plurality of active fins.
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to provide a plurality of active fins as taught by Zang in order to have greater control over the threshold voltage (Paragraph 70)
Claim 15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al (U.S. Pub #2021/0210532), in view of Chen et al (U.S. Pub #2021/0210534).
With respect to claim 15, Hung teaches an image sensor comprising:
a first substrate (Fig. 17, 1406);
a first insulating interlayer (see example of interlayers 132 and wiring 126 in Fig. 3A) on the first substrate, the first insulating interlayer containing first wirings (Fig. 17, upper wirings 1404);
a second insulating interlayer on the first insulating interlayer, the second insulating interlayer containing second wirings (Fig. 17, lower wiring 1404);
a second substrate (Fig. 17, 104) on the second insulating interlayer;
a pixel division structure (Fig. 17, 122 and Paragraph 26) in the second substrate, the pixel division structure defining unit pixel regions in which unit pixels are respectively formed;
a light sensing element (Fig. 17, 110a and Paragraph 24) in each of the unit pixel regions of the second substrate;
a first gate structure (Fig. 17, 1102) extending through a lower portion of the second substrate and contacting the light sensing element (Fig. 17, 110);
a floating diffusion (FD) region (Fig. 17, 120 and Paragraph 47) at the lower portion of the second substrate adjacent to the first gate structure;
a lower planarization layer (e.g. Fig. 3A, 132 or 304) on the second substrate; a color filter array (Fig. 17, 134a/134b and Paragraph 29) layer on the second substrate, the color filter array layer including color filters; and
a microlens (Fig. 17, 136 and Paragraph 29) on the color filter array layer.
Hung does not teach
a second gate structure under an active fin, the active fin protruding from a lower surface of the second substrate downwardly.
Chen teaches a gate structure under an active fin, the active fin protruding from a surface of the substrate downwardly.
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to provide a second gate structure on the substrate of Hung having an active fin protruding from a lower surface as taught by Chen in order to provide a source follower transistor having lower power and noise (Paragraph 21 and 130).
With respect to claim 20, Chen teaches source/drain regions (Fig. 2, 116 and 118) at portions of the active fin adjacent to the second gate structure, wherein the second gate structure and the source/drain regions configure one of a reset transistor, a source follower transistor (Paragraph 44) and a select transistor.
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to provide a transistor comprising the portions as taught by Chen on the substrate of Hung in order to provide a source follower transistor as part of the pixel circuit (Fig. 5. SF).
Claim 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Hung and Chen, in view of Wu et al (U.S. Pub #2021/0366956).
With respect to claim 16, Hung does not teach that the first substrate defines a first region, a second region surrounding the first region, a third region surrounding the second region, and a fourth region surrounding the third region in an inner portion of the first substrate, an upper space over the first substrate, and a lower space under the first substrate, the pixel division structure is formed in the first and second regions, and the color filter array layer is formed in the first region.
Wu teaches that a substrate defines a first region (Fig. 46, inner pixel area), a second region (Fig. 46, region underneath and defined by 312) surrounding the first region, a third region (Fig. 46, region defined by via 1550) surrounding the second region, and a fourth region surrounding the third region (Fig. 46, defined by 1524) in an inner portion of the first substrate, an upper space over the first substrate, and a lower space under the first substrate, the pixel division structure (Fig. 47, 116) is formed in the first and second regions, and the color filter array layer (Fig. 47, 120) is formed in the first region.
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to form the substrate of Hong to include first through fourth regions as taught by Wu in order to integrate the image sensor substrate with a processing substrate (Fig. 47, 1530 and Paragraph 64), wherein the additional third and fourth regions accommodate the via and bond pads connections for the processing substrate.
With respect to claim 17, Wu teaches that first and second wirings (Fig. 47, 1512 and 1536) are formed in the third region, and wherein the image sensor further comprises: a through via structure (Fig. 47, 1550 and Paragraph 68) extending through a lower planarization layer, a second substrate, a second insulating interlayer and an upper portion of the first insulating interlayer and commonly contacting the first and second wirings in the third region; and
a conductive pad (Fig. 47, 1524 and Paragraph 130) extending through the lower planarization layer and an upper portion of the second substrate in the fourth region.
It would have been obvious to one of ordinary skill in the art at the time the inveiotn was effectively filed to provide a through via structure and conductive pad extending through the claimed layers in the structure of Hung as taught by Wu in order to achieve the predictable result of making connections between the image sensor and the processing substrate.
Allowable Subject Matter
Claims 9-14 are allowed.
The following is an examiner’s statement of reasons for allowance: the best prior art of record does not teach or fairly suggest:
in claim 9: wherein a silicon-fluorine layer is formed at an upper portion of the substrate under the gate structure.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claims 2-5, 18, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN P SANDVIK whose telephone number is (571)272-8446. The examiner can normally be reached M-F: 10-6.
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/BENJAMIN P SANDVIK/ Primary Examiner, Art Unit 2812