DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Remarks, filed on May 19, 2026, with respect to drawings, specifications, and 35 USC § 112 (b) and (d) rejections of claims 1-20 have been fully considered and are persuasive. The objections to drawings and specifications and the 35 USC § 112 (b) and (d) rejection of claims 1-20 has been withdrawn.
However, upon considering the amended claims, the examiner has raised a 35 USC § 112 (a) and (b) rejections based on new matter being introduced. The examiner has also found prior art, Infineon, to teach the amended limitations. Please see rejections below.
In summary, this application is not in a condition for an allowance.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the first and second terminals being directly bonded to an upper surface of the metal pattern layer, as required by claims 1 and 20, must be shown or the feature canceled from the claims. No new matter should be entered.
The figures show two terminals, a left 160 and a right 160, being bonded to metal pattern layer 130 through the use of bonding layers 161. Hence, these two terminals are not directly bonded to metal pattern layer 130.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 8 is objected to because of the following informalities: the metal pattern layer have [sic: has] a thickness of 0.1mm through 5 mm. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor, at the time the application was filed, had possession of the claimed invention.
The specification of the instant application defines “direct bonding” as bonding two structures without any intervening bonding layer. Paragraph ¶ [0061] states: “the negative patterned substrate 110 and the radiation fins 112 may be directly joined to each other without additional bonding layers and thereby, may have a combined structure.” As noted in the objections to drawings above, claims 1 and 20, and by extension, dependent claims 2-19, require first and second vertical terminals directly bonded to an upper surface of the metal pattern layer. However, this subject matter is not disclosed in the specifications nor in the drawings. As such, the examiner has determined that this particular amended limitation contains a new matter.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “directly bonded” in claim 1, and by extension, in dependent claims 2-19 and the term “directly bonding” in claim 20 are used by the claims to mean “bonding first and second terminals 160 to the metal pattern layer 130 using a bonding layer 161 without any intervening wire,” as described in ¶ [0053] of the instant application, while the accepted meaning is “bonding first and second terminals 160 to metal pattern layer without any use of a bonding layer.” The term is indefinite because the specification does not clearly redefine the term and/or has another definition in ¶ [0061] (see 35 USC § 112 (a) rejection above) that contradicts the meaning used in the claim.
For the purpose of compact prosecution, the examiner will cite art that teaches bonding terminals to a metal pattern layer without any intervening wires.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4, 9-11, 14-15, 17-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Fujino (US 2015/0021750 A1) in view of Katsuki (US 2023/0197470 A1) and Infineon (DE 20 2018 100486 U1).
Regarding claim 1, Fujino teaches a semiconductor package (101; see Figs. 1-4) comprising:
a negative patterned substrate (10) which is penetrated in a negative form (¶ [0044]: concave), comprises a flat negative patterned bottom (11) formed thereon, and is formed of a metal material (¶ [0044]: aluminum), wherein an entire portion (entire upper surface of 11) of an upper surface (upper surface of 11) of the flat negative patterned bottom is flat (see Figs. 2-4);
at least one insulating layer (55) which is formed on the negative patterned bottom, wherein the at least one insulating layer is in direct contact with the flat negative patterned bottom of the negative patterned substrate (Figs. 3-4 and ¶ [0048] shows 55 directly contacting 11);
a metal layer (20&51&52&53) which is formed on the insulating layer;
a pair of semiconductor chips (the pair of 30 & 31 taken along the B-B’ axis; see Figs. 2 and 4) formed on the metal layer, wherein the pair of semiconductor chips are connected to each other with a conductive clip (40; ¶ [0048]: “bus bars 40 made of Cu are placed on the active surfaces of the diodes 30 and the IGBTs 31 and, further, are bonded thereto through a solder 52” );
a wire (54; see Fig. 4);
first (45; see Fig. 2) and second (42) vertical terminals, with the second vertical terminal directly bonded to an upper surface (top surface) of the metal pattern layer (¶ [0048]: “external electrode 42 is bonded to the heat sink 20”); and
a molding sealing member (71) which is filled in a negative space (15) of the negative patterned substrate and is molded to cover the semiconductor chips, the wire, and a part of the vertical terminals (see Figs. 3-4),
wherein the first and second vertical terminals are aligned with the semiconductor chips in a horizontal direction (92; Fig. 2 shows 45, 42, 30 and 31 lie in the same plane of direction 92),
wherein upper ends (upper ends of 45 & 42) of the vertical terminals are exposed to an upper part (upper surface of 71) of the molding sealing member (Figs. 2-4 show upper ends of 45 & 42 are protruding out of the upper surface of 71) and thus, are electrically connected to external electrical connecting members (Fig. 4 shows 45 is connected to 54; ¶ [0048]: 42 and 31 bonded to 20&52; since 42 and 31 are both connected to 20&52, then 42 is also electrically connected to connecting member 54),
wherein the pair of semiconductor chips are provided between the first and second vertical terminals (Fig. 2 shows 30 & 31 between 45 and 42 when viewing the figure along the horizontal axis, B-B) and no vertical terminal is provided between the pair of semiconductor chips (Fig. 2 shows no vertical terminal is provided in between 30 & 31),
wherein horizontal widths of the first and second vertical terminals are different from each other (Fig. 2 shows 42 to be thicker than 45, with the widths measured along direction 92).
Fujino further teach the metal layer to be part of a circuit (60; see ¶ [0047]-[0048]) with at least one of the terminals electrically connected to the circuit (¶ [0048]: 42 bonded to 20). However, Fujino does not explicitly teach the metal layer to be a patterned metal layer and the electrical connecting members connect the pattern metal layer to semiconductor chips.
Katsuki, in the same field of invention, teaches a semiconductor package (1), wherein the metal layer (22a-h; see Fig. 3; note: 22 is formed on insulating layer 21) is a patterned metal layer (see ¶ [0036]-[0041]) and wherein electrical connecting members (24c) connect the patterned metal layer (22d) to semiconductor chips (30).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Katsuki into the device of Fujino to modify the metal layer to be a patterned metal layer. The ordinary artisan would have been motivated to modify Fujino in the manner set forth above for at least the purpose of substituting the metal layer of Fujino with a pattern metal layer, i.e., using electroplating to form the patterned metal layer on insulating layer (21, see Katsuki Fig. 1), to improve the corrosion resistance of the metal layer (¶ [0038] ).
Furthermore, the ordinary artisan, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Katsuki into the device of Fujino to connect the metal layer to the semiconductor chip using the electrical connecting members. The ordinary artisan would have been motivated to modify Fujino in the manner set forth above for at least the purpose of using semiconductor chips that may have electrodes on the top side of the chip (see Katsuki Fig. 3 and ¶ [0049]: “wire 24c directly connects the circuit pattern 22d and the control electrode on the front surface of the semiconductor chip 30”) and hence need the connecting member to connect the semiconductor chip to an output terminal (25d; ¶ [0050] ).
Fujino further teaches a bus bar (40; see Fig. 2) connecting the two semiconductor chips. However, Fujino in view of Katsuki does not teach another wire electrically connecting the metal layer to one of the semiconductor chips and the first vertical terminal directly bonded to an upper surface of the metal pattern layer.
Infineon, in the same field of invention, teaches a device (Fig. 1) comprising of a wire (24) electrically connecting the metal pattern layer (111) to one of the semiconductor chips (20) and the first vertical terminal (left 30) directly bonded (Fig. 1 shows no intervening wires) to an upper surface (top surface) of the metal pattern layer.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Infineon into the device of Fujino in view of Katsuki to replace the bus bar (40; see Fujino Fig. 2) that connects one or more of the semiconductor chips with a wire that connects one of the semiconductor chips to the metal pattern layer and to directly bond the first vertical terminal to an upper surface of the metal pattern layer. The ordinary artisan would have been motivated to modify Fujino in view of Katsuki in the manner set forth above for at least the purpose of using methods known in the art for electrically connecting semiconductor chips and terminals to metal pattern layers (see ¶ [0020], [0027] of the English translation of Infineon), for the further purpose of creating space for a pressure stamp (46) of the lid (44) to improve the fastening of the packaging and heat dissipation (¶ [0024]-[0025] ).
Regarding claim 2, the semiconductor package of claim 1, wherein the negative patterned substrate is formed of a single material such as Al or Cu or an alloy containing 50% or more of any one of Al and Cu (Fujino ¶ [0044]: aluminum; ¶ [0059]: copper ).
Regarding claim 3, the semiconductor package of claim 1, wherein 30% or more of the total surface area of the negative patterned substrate is plated (Fujino ¶ [0059]: Sn-plated steels ).
Regarding claim 4, Fujino et al. teach the semiconductor package of claim 1, but does not explicitly teach: wherein the negative patterned substrate comprises a negative pattern depth in the range of 0.5mm to 10mm.
However, Fujino does teach the height of the negative patterned substrate to be adjusted according to various design considerations (¶ [0018] ).
Hence, a person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to have a negative patterned substrate comprises a negative pattern depth in the range of 0.5mm to 10mm. The ordinary artisan would have been motivated to modify Fujino et al. in the manner set forth above for at least the purpose of optimizing the ranges of the depth of the negative pattern substrate, through routine experimentation, to suit to specific design dimensions and requirements of a specific embodiment of the invention of Fujino et al. (see MPEP § 2144.05 (I) and (II)(A)) and/or to reduce the size of the package (Fujino ¶ [0018] ) and optimizing the insulation creepage distance (¶ [0049] ).
Regarding claim 9, the semiconductor package of claim 1, wherein the semiconductor chip comprises a power conversion function (Fujino ¶ [0001]-[0004], ¶ [0042]; ¶ [0047]: uses IGBT, which is known in the art to be used in power converters )
Regarding claim 10, the semiconductor package of claim 1, wherein the wire is formed of a material containing Au, AI, or Cu (Katsuki ¶ [0049]: 24 made of Al, Cu or alloys thereof ).
Regarding claim 11, the semiconductor package of claim 1, wherein the molding sealing member is formed of a composite material (¶ [0050]: silicone, which is known in the art to be a composite material having silicon content as well as hydrogen, carbon, and oxygen ) containing epoxy content or an insulating material containing Si content.
Regarding claim 14, the semiconductor package of claim 1, wherein longitudinal sections of the vertical terminals are formed as press fit pins (Fujino ¶ [0057]: 42 and 45 can be press-fit terminals ) and are electrically connected to the external electrical connecting members (Fig. 4 shows 45 is connected to 54; ¶ [0048]: 42 and 31 bonded to 20&52; since 42 and 31 are both connected to 20&52, then 42 is also electrically connected to connecting member 54).
Regarding claim 15, Fujino et al. teach the semiconductor package of claim 1, but does not teach: wherein the negative patterned substrate comprises at least one radiation fin structurally joined to the lower surface thereof.
Fujino, through another embodiment, teaches a semiconductor package (107; see Fig. 14) wherein the negative patterned substrate (225) comprises at least one radiation fin (226) structurally joined to the lower surface thereof.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of another embodiment of Fujino into the device of Fujino et al. toad at least one radiation fin to the negative patterned substrate. The ordinary artisan would have been motivated to modify Fujino et al. in the manner set forth above for at least the purpose of providing a cooling mechanism that properly attaches to the negative patterned substrate (Fujino ¶ [0105] ), thereby preventing structural degradations and enhancing the quality of the device (Fujino ¶ [0104] ).
Regarding claim 17, the semiconductor package of claim 1, wherein the negative patterned substrate comprises a cover (72, see Fujino Figs. 3-4) for covering 50% or more of the total area (area of the upper surface of 71) of the molding sealing member formed on the upper part thereof (Figs 3-4 show 72 covering 50% or more of the area of 71) and the vertical terminals penetrate the cover to be exposed to the upper part of the cover (Fig. 1 shows 42 and 45 penetrating through 70, which is the upper surface of 72; see also ¶ [0050] ).
Regarding claim 18, Fujino et al. teach the semiconductor package of claim 1, but do not teach: wherein the negative patterned substrate comprises a cooling system structurally joined thereto and a joining surface interposed between the negative patterned substrate and the cooling system comprises substrate bonding members formed thereon to make a coolant of the cooling system watertight.
Fujino, through another embodiment, teaches a semiconductor package (107, see Fig. 14), wherein the negative patterned substrate (225) comprises a cooling system (226&228) structurally joined thereto (see Fujino Fig. 14B) and a joining surface (inner surfaces of 228 that directly contacts 225) interposed between the negative patterned substrate and the cooling system comprises substrate bonding members formed thereon to make a coolant (¶ [0105]: refrigerant such as water ) of the cooling system watertight (¶ [0105]: 228 used to prevent leakage ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of another embodiment of Fujino into the device of Fujino et al. to add a cooling system that is structurally connected to the negative patterned substrate and a joining surface interposed between the negative patterned substrate and the cooling system in order to seal a coolant in the cooling system. The ordinary artisan would have been motivated to modify Fujino et al. in the manner set forth above for at least the purpose of providing a cooling system that properly attaches to the negative patterned substrate (Fujino ¶ [0105] ), thereby preventing structural degradations and enhancing the quality of the device (¶ [0104] ) and for providing fins (226) that further enhance the cooling effect of the cooling system (¶ [0105] ).
Regarding claim 20, Fujino teaches a method of manufacturing a semiconductor package (101; see Figs. 1-4), the method comprising:
preparing a negative patterned substrate (10) which is penetrated in a negative form (¶ [0044]: concave), comprises a flat negative patterned bottom (11) formed thereon, and is formed of a metal material (¶ [0044]: aluminum), wherein an entire portion (entire upper surface of 11) of an upper surface (upper surface of 11) of the flat negative patterned substrate is flat (see Figs. 2-4);
forming at least one insulating layer (55) which is formed on the negative patterned bottom, wherein the at least one insulating layer is in direct contact with the flat negative patterned bottom of the negative patterned substrate (Figs. 3-4 and ¶ [0048] shows 55 directly contacting 11);
forming a metal layer (20&51&52&53) which is formed on the insulating layer;
installing a pair of semiconductor chips (30 & 31; see Figs. 2 and 4) on the metal pattern layer, wherein the pair of semiconductor chips are connected to each other with a conductive clip (40; ¶ [0048]: “bus bars 40 made of Cu are placed on the active surfaces of the diodes 30 and the IGBTs 31 and, further, are bonded thereto through a solder 52” );
electrically connecting at least one of the semiconductor chips (31) to a wire (54, see Fig. 4);
forming first (45) and second vertical (42) terminals, with the second vertical terminal directly bonded to an upper surface (top surface) of the metal pattern layer (¶ [0048]: “external electrode 42 is bonded to the heat sink 20”); and
filling a negative space of the negative patterned substrate with a molding sealing member (71) and molding to cover the semiconductor chips, the wire, and a part of the vertical terminals (see Figs. 3-4),
wherein the first and second terminals are aligned with the semiconductor chips in a horizontal direction (92; Fig. 2 shows 45A, 42, 30 and 31 lie in the same plane of direction 92),
wherein upper ends (upper ends of 45 & 42) of the vertical terminals are exposed to an upper part (upper surface of 71) of the molding sealing member and thus, are electrically connected to external electrical connecting members (Fig. 4 shows 45 is connected to 54; ¶ [0048]: 42 and 31 bonded to 20&52; since 42 and 31 are both connected to 20&52, then 42 is also electrically connected to connecting member 54),
wherein the pair of semiconductor chips are provided between the first and second vertical terminals (Fig. 2 shows 30 & 31 between 45 and 42 when viewing the figure along the horizontal axis, B-B) and no vertical terminal is formed between the pair of semiconductor chips (Fig. 2 shows no vertical terminal is provided in between 30 & 31),
wherein horizontal widths of the first and second vertical terminals are different from each other (Fig. 2 shows 42 to be thicker than 45, with the widths measured along direction 92).
Fujino further teach making a circuit (60; see ¶ [0047]-[0048]) comprising at least the metal layer with at least one of the terminals electrically connected to the circuit (¶ [0048]: 42 bonded to 20). However, Fujino does not explicitly teach the method wherein the metal layer is made to be a patterned metal layer and electrically connecting the metal pattern layers to the semiconductor chips by using the electrical connecting members.
Katsuki, in the same field of invention, teaches a method of manufacturing a semiconductor package (1), wherein the metal layer (22a-h; see Fig. 3; note: 22 is formed on insulating layer 21) is made to be a patterned metal layer (see ¶ [0036]-[0041]) and electrically connecting the metal pattern layers (22d) to the semiconductor chips (30) by using the electrical connecting members (24c).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Katsuki into the method of Fujino to modify the metal layer to be a patterned metal layer. The ordinary artisan would have been motivated to modify Fujino in the manner set forth above for at least the purpose of substituting the metal layer of Fujino with a pattern metal layer, i.e., using electroplating to form the patterned metal layer on insulating layer (21, see Katsuki Fig. 1), to improve the corrosion resistance of the metal layer (¶ [0038] ).
Furthermore, the ordinary artisan, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Katsuki into the method of Fujino to connect the metal layer to the semiconductor chip using the electrical connecting member. The ordinary artisan would have been motivated to modify Fujino in the manner set forth above for at least the purpose of using semiconductor chips that may have electrodes on the top side of the chip (see Katsuki Fig. 3 and ¶ [0049]: “wire 24c directly connects the circuit pattern 22d and the control electrode on the front surface of the semiconductor chip 30”) and hence need the connecting member to connect the semiconductor chip to an output terminal (25d; ¶ [0050] ).
Fujino further teaches forming a bus bar (40; see Fig. 2) that connects the two semiconductor chips. However, Fujino in view of Katsuki does not teach electrically connecting the metal layer to one of the semiconductor chips by using another wire and directly bonding the first vertical terminal to an upper surface of the metal pattern layer.
Infineon, in the same field of invention, teaches a method of manufacturing a semiconductor package (Fig. 1) comprising of electrically connecting the metal pattern layer (111) to one of the semiconductor chips (20) by using a wire (24) and directly bonding (Fig. 1 shows no intervening wire) the first vertical terminal (left 30) to an upper surface (top surface) of the metal pattern layer.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Infineon into the method of Fujino in view of Katsuki to replace the bus bar (40; see Fujino Fig. 2) that connects one or more of the semiconductor chips with a wire that connects one of the semiconductor chips to the metal pattern layer and to directly bond the first vertical terminal to an upper surface of the metal pattern layer. The ordinary artisan would have been motivated to modify Fujino in view of Katsuki in the manner set forth above for at least the purpose of using methods known in the art for electrically connecting semiconductor chips and terminals to metal pattern layers (see ¶ [0020], [0027] of the English translation of Infineon), for the further purpose of creating space for a pressure stamp (46) of the lid (44) to improve the fastening of the packaging and heat dissipation (¶ [0024]-[0025] ).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Fujino (US 2015/0021750 A1) in view of Katsuki (US 2023/0197470 A1) as applied to claim 1 above, as evidenced by Nishimori (US 2018/0041177 A1) .
Regarding claim 7, the semiconductor package of claim 1, wherein the insulating layers are disposed on the negative patterned bottom in the form of paste or film (Fujino ¶ [0048]: 55 is an insulating sheet, which is also known in the art as an insulating “film” as evidenced by Nishimori ¶ [0062] ).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Fujino (US 2015/0021750 A1) in view of Katsuki (US 2023/0197470 A1) as applied to claim 1 above, and further in view of Kanai (US 2017/0025344 A1).
Regarding claim 8, Fujino et al. teach semiconductor package of claim 1, but does not teach wherein the metal pattern layer have a thickness of 0.1mm through 5mm.
Kanai, in the same field of invention, teaches a device (Fig. 1, and/or Fig. 6) wherein the metal pattern layer (2) have a thickness of 0.1 mm through 5mm (¶ [0065] : 0.2 mm or ¶ [0037]: 0.1 mm to 1 mm)
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Kanai into the device of Fujino et al. to set the thickness of the metal pattern layers to 0.1 mm through 5 mm. The ordinary artisan would have been motivated to modify Fujino et al. in the manner set forth above for at least the purpose of optimizing the ranges of the thickness of the metal layer through routine experimentation (Kanai ¶ [0065] teaches a working example) in order to meet the dimensional requirements of a particular embodiment of the device of Fujino et al. in order to further optimize a preferred electrical resistance and/or bonding strength associated with the thickness of the metal layer (Kanai ¶ [0037] ). See also MPEP § 2144.05 (I) and (II)(A).
Furthermore, “[w]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). See MPEP § 2144.05 (II)(A).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Fujino (US 2015/0021750 A1) in view of Katsuki (US 2023/0197470 A1) as applied to claim 1 above, and further in view of Pavlicek (US 2024/0145332 A1).
Regarding claim 12, Fujino et al. teach the semiconductor package of claim 1, but does not teach: wherein the molding sealing member has a thickness of above 1mm.
Pavlicek, in the same field of invention, teaches a semiconductor package (Fig. 2: 1) wherein the molding sealing member (¶ [0075]: 4) has a thickness (T) of above 1mm (¶ [0075]: 6 mm).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Pavlicek into the device of Fujino et al. to set a thickness of a molding sealing member above 1mm. The ordinary artisan would have been motivated to modify Fujino et al. in the manner set forth above for at least the purpose of optimizing the ranges of the thickness of the molding sealing member through routine experimentation in order to properly cover the internal elements of the semiconductor package (Pavlicek ¶ [0074]-[0075]). See MPEP § 2144.05 (I) and (II)(A).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Fujino (US 2015/0021750 A1) in view of Katsuki (US 2023/0197470 A1) as applied to claim 1 above, and further in view of Sudo (JP 2010182879 A).
Regarding claim 13, Fujino et al. teach the semiconductor package of claim 1, but does not teach: wherein the upper ends of the vertical terminals are formed as female screws.
Sudo, in the same field of invention, teaches a semiconductor package (Fig. 3; see English translation mailed on 16 July 2025) wherein the upper ends (upper ends of 16) of the at vertical terminals (16) are formed as female screws (Page 5 of English translation, last paragraph).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Sudo into the semiconductor package of Fujino et al. to form the upper ends of at least one terminal as female screws in a semiconductor package at least comprising of a negative patterned substrate that is penetrated in a negative form and having a flat negative patterned bottom, at least one insulating layer on the negative patterned bottom, a metal pattern layer on the insulating layer, at least one semiconductor chip on the metal pattern layer, and at least one of the abovementioned terminal exposed outside the negative patterned substrate. The ordinary artisan would have been motivated to modify Fujino et al. in the manner set forth above for at least the purpose of using the female screw in tandem with a male screw as an alternative method of bonding a columnar electrode to a pin electrode without using an adhesive (Sudo Page 5, last paragraph), and for the further purpose of using both male and female screws in a transfer mold process (Sudo Figs. 4-5; Page 4, 5th paragraph) that results in the final product (Sudo Figs. 1 or 6).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Fujino (US 2015/0021750 A1) in view of Katsuki (US 2023/0197470 A1) as applied to claim 1 above, and further in view of Yamamoto (US 6,269,866 B1).
Regarding claim 16, Fujino et al. teach the semiconductor package of claim 1 but does not teach: wherein the negative patterned substrate comprises at least one radiation fin structurally joined to the lower surface thereof.
Fujino, through a different embodiment, teaches a semiconductor package (107, Fig. 14), wherein the negative patterned substrate (225) comprises at least one radiation fin (226, see Fujino Fig. 14B) structurally joined to the lower surface thereof.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of another embodiment of Fujino into the device of Fujino et al. to add at least one radiation fin structurally joined to the lower surface. The ordinary artisan would have been motivated to modify Fujino et al. in the manner set forth above for at least the purpose of providing a heat dissipation method without damaging the structural integrity of the device (Fujino ¶ [0104] ).
However, Fujino et al. does not teach the negative patterned substrate comprises at least one wave-form metal plate structurally joined to the lower surface thereof.
Yamamoto, in the same field of invention, teaches semiconductor packages either with a radiation fin (Figs. 1, 4a, 5, 23, 26, 29-30: 40) or with a wave-form metal plate (Fig. 14b: 4a) for cooling the semiconductor device (Figs. 29-30: 102; see also Col. 1, Ln 34-50; Col. 14, Ln 36-44).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to substitute the radiation fin of Fujino et al. with the wave-form metal plate of Yamamoto for the same purpose of providing cooling to the semiconductor device (Yamamoto Col. 1, Ln 34-50; Col. 14, Ln 36-44). Alternatively, the ordinary artisan would have been motivated to modify Fujino et al. in the manner set forth above for at least the purpose of increasing the surface area of the cooling structure by using wave-form metal plate (Yamamoto Col. 14, Ln 35-37) and for the further purpose of increasing the heat transfer from the semiconductor device to surrounding environment.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Fujino (US 2015/0021750 A1) in view of Katsuki (US 2023/0197470 A1) as applied to claim 1 above, and further in view of Danielson ( US 2021/0307196 A1).
Regarding claim 19, Fujino et al. teach the semiconductor package of claim 1, but does not teach: wherein the negative patterned substrate comprises a cooling system structurally joined thereto, and the negative patterned substrate and the cooling system are joined to each other to make the coolant of the cooling system watertight.
Fujino, through a different embodiment, teaches a semiconductor package (107, see Fig. 14) wherein the negative patterned substrate (225) comprises a cooling system (226 &228) structurally joined thereto (226&228 is joined to 225), and the negative patterned substrate and the cooling system are joined to each other to make the coolant of the cooling system watertight (¶ [0105]: “a jacket 228 which can be bonded to the tray 225 in such a way as to prevent leakages of the refrigerant”).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of another embodiment of Fujino into the device of Fujino et al. to join a watertight cooling system to the negative pattern substrate. The ordinary artisan would have been motivated to modify Fujino et al. in the manner set forth above for at least the purpose of using a refrigerant to further improve the heat dissipation of the device without degrading the structural integrity of the device (Fujino ¶ [0104]-[0105] ).
Fujino et al. further teaches using a jacket (228) to make a watertight seal. However, Fujino et al. does not teach using friction stir welding to make the coolant of the cooling system watertight.
Danielson, in the same field of invention, teaches using friction stir welding and/or other sealing techniques (¶ [0020], [0024]) to make a watertight seal.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Danielson into the device of Fujino et al. to join a negative patterned substrate and a cooling system to each other by using friction stir welding to make a coolant of the cooling system watertight. The ordinary artisan would have been motivated to modify Fujino et al. in the manner set forth above for at least the purpose of substituting the jacket sealing member of Fujino with the friction stir welding of Danielson, for the predictable result of providing watertight sealing (Danielson ¶ [0020]) or, alternatively, for the purpose of substituting equivalent materials known in the prior art for the same purpose of providing watertight seals (Danielson ¶ [0020]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DOUGLAS YAP/Assistant Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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