Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5, 8-12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lilak et al. (Pub. No. US 2020/0294998 A1, herein Lilak).
Regarding claim 1, Lilak discloses an integrated circuit comprising: a first semiconductor device having a first semiconductor region 116A extending in a first direction between a first source region 124A and a first drain region 124A (Lilak: paragraph [0013]), and a first gate structure extending in a second direction over the first semiconductor region, the first gate structure having a first gate dielectric structure 122A and a first gate electrode 120A on the first gate dielectric structure (Lilak: paragraphs [0013], [0019]); and a second semiconductor device having a second semiconductor region 116B extending in the first direction between a second source region 124B and a second drain region 124B, and a second gate structure extending in the second direction over the second semiconductor region, the second gate structure having a second gate dielectric structure 122B and a second gate electrode 120B on the second gate dielectric structure (Lilak: paragraphs [0013], [0019]); wherein the first gate dielectric structure includes a first gate oxide layer and the second gate dielectric structure includes a second gate oxide layer, wherein the first gate oxide layer is thicker than the second gate oxide layer (Lilak: Figs. 1A-9D and paragraph [0021]).
Lilak does not specifically state wherein the first gate oxide layer is at least 2 nm thicker than the second gate oxide layer. However, the claimed thickness range is recognized as a result-effective variable, i.e., a variable which achieves a recognized result. As Lilak stated in paragraph [0021], “the upper and lower gate dielectric structures may be employed with intentionally different thicknesses to be tuned for different types of transistor devices. For instance, he relatively thicker gate dielectric is used for a high voltage transistor device, while the relatively thinner gate dielectric is used for a logic transistor device.” Therefore, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose the particular claimed range because applicant has not disclosed that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another temperature range. The claim(s) is(are) obvious without showing that the claimed range(s) achieve unexpected results relative to the prior art range. See In re Aller, 105 USPQ 233 (CCPA 1955) and In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art).
Regarding claims 2 and 10, Lilak teaches the integrated circuit of claim 1, wherein the first semiconductor region comprises a plurality of first semiconductor nanoribbons and the second semiconductor region comprises a plurality of second semiconductor nanoribbons (Lilak: paragraphs [0008], [0015], [0017], [0030], [0036], [0038], [0079]).
Regarding claims 3 and 11, Lilak teaches the integrated circuit of claim 1, wherein the first gate dielectric structure includes a first layer of high-k material and the second gate dielectric structure includes a second layer of high-k material (Lilak: paragraphs [0019], [0074]).
Regarding claim 4, Lilak teaches the integrated circuit of claim 3, wherein the first layer of high-k material and the second layer of high-k material each have substantially the same thickness (Lilak: paragraphs [0019], [0021]).
Regarding claims 5 and 12, Lilak teaches the integrated circuit of claim 3, wherein the first layer of high-k material and the second layer of high-k material each comprise hafnium and oxygen (Lilak: paragraphs [0019], [0021]).
Regarding claims 8 and 14, Lilak teaches a printed circuit board comprising the integrated circuit of claim 1 (Lilak: paragraphs [0062], [0084]).
Regarding claim 9, the applicant is referred to the rejection applied to claim 1 above. Claim 9 differs from claim 1 in stating the limitation “an electronic device, comprising: a chip package comprising one or more dies, at least one of the one or more dies comprising a first semiconductor device,” which Lilak teaches it in paragraphs [0062]-[0066].
Claims 6 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Lilak in view of Hook (Pub. No. US 2024/0096948 A1).
Regarding claims 6 and 13, Lilak does not specifically show that the first gate dielectric structure does not include a layer of high-k material and the second gate dielectric structure does include a layer of high-k material.
However, in the same field of endeavor, Hook in paragraphs [0030]-[0031] states “the second gate dielectric material layer 20 is composed of a second gate dielectric material including silicon oxide or a high-k dielectric material as mentioned above for the first gate dielectric material. The second gate dielectric material can be compositionally the same as, or compositionally different from, the first gate dielectric material.”
Therefore, given the teachings of Hook, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Lilak in view of Hook by employing the first gate dielectric structure not including a layer of high-k material and the second gate dielectric structure including a layer of high-k material to serve different electrical and reliability roles, so high-k dielectrics are used only where enhanced gate control is needed, while conventional dielectrics are retained where stability, reliability or controlled coupling are more important. High-K materials may suffer from charge trapping, Vt instability, or hysteresis. Silicon oxide provides better TDDB (Time-Dependent Dielectric Breakdown), lower trap generation, and more predictable breakdown behavior. Therefore, high-k materials are used where performance matters most, and oxide is used where robustness dominates.
The applicant is similarly referred to claim 9 of Chang et al. (Pub. No. US 2024/0120239 A1).
Claims 7, 15-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lilak in view of Balakrishnan et al. (Pub. No. US 2017/0194357 A1, herein Balakrishnan).
Regarding claim 7, Lilak does not specifically show the first semiconductor nanoribbon has a midpoint thickness that is at least 1 nm thicker than a midpoint thickness of the second semiconductor nanoribbon.
However, in the same field of endeavor, Balakrishnan teaches an integrated circuit, wherein the first semiconductor region comprises a first semiconductor nano-structure 19A and the second semiconductor region comprises a second semiconductor nano-structure 19B/19C, and the first semiconductor nano-structure has a midpoint thickness that is at least 1 nm thicker than a midpoint thickness of the second semiconductor nano-structure (Balakrishnan: Figs. 10A-12C, paragraphs [0086]-[0101], and claim 2) providing a multiple threshold voltage option for gate-all-around stacked semiconductor nano structures which is capable of meeting the wide variety of power-performance criteria required of microarchitectural circuit blocks and which can circumvent the problem of width quantization (Balakrishnan: paragraphs [0001]-[0004]).
Therefore, given the teachings of Balakrishnan, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Lilak in view of Balakrishnan by employing the nano-structures’ thickness difference of Balakrishnan in the semiconductor nanoribbons of Lilak.
Regarding claim 15, the applicant is referred to the rejections applied to claims 1 and 7 above.
Regarding claims 16-18, the applicant is referred to the rejections applied to claims 3, 4, 5 respectively.
Regarding claim 20, Lilak in view of Balakrishnan does not specifically state wherein the midpoint thickness of a given one of the first semiconductor nanoribbons is in the range of 12 angstroms to 20 angstroms thicker than the midpoint thickness of a given one of the second semiconductor nanoribbons. However, the claimed thickness range is recognized as a result-effective variable, i.e., a variable which achieves a recognized result. As Balakrishnan stated in paragraphs [0001]-[0004], “providing a multiple threshold voltage option for gate-all-around stacked semiconductor nano structures which is capable of meeting the wide variety of power-performance criteria required of microarchitectural circuit blocks and which can circumvent the problem of width quantization.” Therefore, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose the particular claimed range because applicant has not disclosed that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another temperature range. The claim(s) is(are) obvious without showing that the claimed range(s) achieve unexpected results relative to the prior art range. See In re Aller, 105 USPQ 233 (CCPA 1955) and In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Lilak in view of Balakrishnan, as applied above and further in view of Hook.
Regarding claim 19, the previous combination does not specifically show the first gate dielectric structure does not include a layer of high-k material and the second gate dielectric structure does include a layer of high-k material.
However, in the same field of endeavor, Hook in paragraphs [0030]-[0031] states “the second gate dielectric material layer 20 is composed of a second gate dielectric material including silicon oxide or a high-k dielectric material as mentioned above for the first gate dielectric material. The second gate dielectric material can be compositionally the same as, or compositionally different from, the first gate dielectric material.”
Therefore, given the teachings of Hook, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Lilak in view of Hook by employing the first gate dielectric structure not including a layer of high-k material and the second gate dielectric structure including a layer of high-k material to serve different electrical and reliability roles, so high-k dielectrics are used only where enhanced gate control is needed, while conventional dielectrics are retained where stability, reliability or controlled coupling are more important. High-K materials may suffer from charge trapping, Vt instability, or hysteresis. Silicon oxide provides better TDDB (Time-Dependent Dielectric Breakdown), lower trap generation, and more predictable breakdown behavior. Therefore, high-k materials are used where performance matters most, and oxide is used where robustness dominates.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALIHEH MALEK whose telephone number is (571)270-1874. The examiner can normally be reached M/T/W/R/F, 8:30-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
December 29, 2025
/MALIHEH MALEK/Primary Examiner, Art Unit 2813