DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park(USPGPUB DOCUMENT: 2022/0011487, hereinafter Park) in view of Tsaur (USPGPUB DOCUMENT: 2016/0056625, hereinafter Tsaur).
Re claim 9 Park discloses an integrated circuit comprising: a target filter[0327] circuit, wherein the target filter[0327] circuit includes a capacitor(Cst) and a first optional component[0184], the first optional component being one of a first resistive circuit and a first transistor(T1/T2/T3) and being disposed in a first circuit region; a plurality of first wires(EL1/EL2/EL3) in a first metal layer(BML1/BML2/BML3), external nodes[0098] ; and a plurality of second wires(EL1/EL2/EL3) in a second metal layer(BML1/BML2/BML3) and disposed around the first circuit region, and the second metal layer(BML1/BML2/BML3) is above the first metal layer(BML1/BML2/BML3), wherein the capacitor(Cst) is disposed in the first circuit region and above the first optional component, the capacitor(Cst) has a first metal plate(Le3/UE3/LE2/UE2 of Cst) and a second metal plate(Le3/UE3/LE2/UE2 of Cst) that are disposed opposite to each other, and the first metal plate(Le3/UE3/LE2/UE2 of Cst) and the second metal plate(Le3/UE3/LE2/UE2 of Cst)s are respectively located in two of the second metal layer(BML1/BML2/BML3) and the at least one third metal layer(BML1/BML2/BML3) above the second metal layer(BML1/BML2/BML3).
Park does not disclose a target filter[0327] circuit disposed at a predetermined position in a circuit layout; a plurality of first wires(EL1/EL2/EL3) in a first metal layer(BML1/BML2/BML3), for respectively and electrically coupling the first optional element to a plurality of first external nodes[0098] outside the first circuit region wherein the plurality of second wires(EL1/EL2/EL3) are for respectively and electrically coupling the first external nodes[0098],
Tsaur disclose electrically coupling the first optional element(R1/R2/RN)[0015] to a plurality of first external nodes(first node/second node)[0015] outside the first circuit region(region of C1/C2/CM) wherein the plurality of second wires(102/104) are for respectively and electrically coupling the first external nodes[0015],
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Tsaur to the teachings of Park in order to achieve the effect of protecting internal circuit [0005, Tsaur]. In doing so, a target filter[0327] circuit disposed at a predetermined position in a circuit layout; a plurality of first wires(EL1/EL2/EL3) in a first metal layer(BML1/BML2/BML3), for respectively and electrically coupling the first optional element to a plurality of first external nodes[0098] outside the first circuit region wherein the plurality of second wires(EL1/EL2/EL3) are for respectively and electrically coupling the first external nodes[0015 of Tsaur],
Re claim 10 Park and Tsaur disclose the integrated circuit according to claim 9, wherein the first optional component is not higher than the first metal layer(BML1/BML2/BML3) in position.
Re claim 11 Park and Tsaur disclose the integrated circuit according to claim 9, wherein the target filter[0327] circuit further includes a second optional element, and in response to the first optional element being the first resistor[0184], the second optional element is a second finFET, in response to the first optional element being the first finFET, the second optional element is a second resistor.
Re claim 12 Park and Tsaur disclose the integrated circuit of claim 11, wherein the second optional component is disposed in the first circuit region without overlapping with the first optional component, and the integrated circuit further comprises: a plurality of third wires(EL1/EL2/EL3) located in the first metal layer(BML1/BML2/BML3), and respectively used for electrically connecting the second optional element to a plurality of second external nodes[0015 of Tsaur] outside the first circuit region; and a plurality of fourth wires(EL1/EL2/EL3) located in the second metal layer(BML1/BML2/BML3) and respectively electrically connected to the plurality of second external nodes[0015 of Tsaur], wherein the fourth wires(EL1/EL2/EL3) are disposed around the first circuit region without overlapping with the plurality of second wires(EL1/EL2/EL3), wherein the capacitor(Cst) is disposed above the second optional component.
Re claim 13 Park and Tsaur disclose the integrated circuit according to claim 12, wherein the second optional component is not higher than the first metal layer(BML1/BML2/BML3) in position.
Re claim 14 Park and Tsaur disclose the integrated circuit according to claim 9, wherein a part of the plurality of second circuits is disposed at a first side of the first circuit region, and another part of the plurality of second wires(EL1/EL2/EL3) is arranged at a second side of the first circuit region.
Re claim 15 Park and Tsaur disclose the integrated circuit according to claim 9, wherein a quantity of the at least one third metal layer(BML1/BML2/BML3) is one, two, three, four, or five.
Re claim 16 Park and Tsaur disclose the integrated circuit according to claim 9, wherein a first circuit region is a capacitor(Cst) reserved region.
Response to Arguments
Applicant’s arguments with respect to claim 9-16 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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