DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendments filed on 12/16/2025 and 12/29/2025 has been entered and accepted.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. A full rejection can be found below.
Election/Restrictions
Newly submitted claim 13 directed to an invention that is independent or distinct from the invention originally claimed for the following reasons:
Claim 13 is an apparatus claim wherein the originally filed claims are all method claims.
Furthermore, claim 13 recites the limitation of “a plurality of conductors are arranged with a predetermined interval” and “an edge of the scale pattern has a recess formed therein that is recessed further than lower ends of the plurality of conductors on a substrate side” which are newly presented limitations. Claim 13 also does not require the use of a short pulse laser which is a limitation present in each of the independent claims of the originally claimed invention.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claim 13 is withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by WATANABE (JP 2019129247 A).
Regarding claim 1, WATANABE (JP 2019129247 A) teaches a manufacturing method of a scale pattern (Figure 1) comprising:
preparing a substrate provided with a conductor on one main surface thereof (Paragraph 21, glass substrate 1 covered with a metal film 2);
forming an outline of the scale pattern on the conductor with a short-pulse laser (Paragraph 27, laser irradiation involves irradiating the UV laser on the surface of the metal coating other than the region where the wiring pattern is to be formed; Paragraph );
removing at least a part of the conductor other than the scale pattern by etching (Paragraph 10, etching the area remaining the area other than the region where the wiring pattern is to be formed to expose the glass surface).
Regarding claim 11, WATANABE teaches the method as claimed in claim 9,
wherein, in the forming the outline of the scale pattern, edges of the plurality of patterns are removed by the short-pulse laser (Figures 1a-1b Paragraph 26, edges of the pattern are removed by the laser).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-4, 7, and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Klocek (US 20210315104 A1) in view of TAKIGUCHI (JP 2008126230 A).
Regarding claim 1, Klocek (US 20210315104 A1) teaches a manufacturing method of a scale pattern comprising:
preparing a substrate provided with a conductor on one main surface thereof (Figure 3 Paragraph 103, electrically conductive layer structure 102 is stacked upon an insulating layer structure 101);
forming an outline of the scale pattern on the conductor (Paragraph 73, forming through holes through the laminate by laser drilling; Paragraph 103, outline of the scale pattern is formed by means of exposing parts of the photoresist 104 through laser radiation; Paragraph 106, exposed copper surface is irradiated with irradiation); and
removing at least a part of the conductor other than the scale pattern by etching (Figure 4 Paragraph 106, recess is developed in the exposed parts of the photoresist 104 by means of etching).
Klocek fails to explicitly teach:
forming an outline of the scale pattern on the conductor with a short-pulse laser
TAKIGUCHI (JP 2008126230 A) teaches a laser beam machining method of processing a workpiece such as a flexible circuit board (Paragraphs 1-4), comprising:
forming an outline of the conductor pattern on the conductor with a short-pulse laser (Paragraph 17, ultrashort pulse laser is used to process the substrate with a pulse width on the order of femtoseconds)
It would have thus been obvious to someone of ordinary skill in the art before the filing date of the claimed invention to have modified Klocek with TAKIGUCHI and used an ultrashort pulse laser to process the printed circuit board. This would be done as the ultrashort pulse laser is known in the art to be functional in processing printed circuit boards and makes it possible to perform high-precision processing without thermal history (TAKIGUCHI Paragraph 17).
Regarding claim 3, Klocek as modified teaches the method as claimed in claim 1, wherein,
after forming the outline of the scale pattern on the conductor with the short pulse laser (Paragraph 103, exposing the photoresist to UV light in the scale pattern outline of the conductor), a resist pattern is formed (Paragraph 103, photoresist is developed) so as to cover the scale pattern (Paragraph 73, forming through holes through the laminate by laser drilling; Paragraph 103, outline of the scale pattern is formed by means of exposing parts of the photoresist 104 through laser radiation), and then the conductor not covered with the resist pattern is removed by etching (Figure 4 Paragraph 106, exposed copper surface is irradiated with irradiation and a recess is developed in the exposed parts of the photoresist 104 by means of etching).
The Office further notes that forming a newly adjusted resist pattern (in which part of the film is removed) after an initial processing of the conductive layer is known in the art as evidenced by Figures 2B and 2C of LEE (US 20230180391 A1).
Regarding claim 4, Klocek as modified teaches the method as claimed in claim 1, further comprising:
forming a plurality of the conductor spaced apart from each other, on the substrate so as to array (Figure 3 Paragraph 106, electrically conductive layer structures having a recess 110 between them; Figure 3 Paragraph 103, said electrically conductive layer structures are placed upon electrically insulating layer structure 101),
wherein, after forming the outline of the scale pattern on the conductor with the short pulse laser (Paragraph 103, exposing the photoresist to UV light in the scale pattern outline of the conductor), a resist pattern is formed (Paragraph 103, photoresist is developed) so as to cover the scale pattern (Paragraph 73, forming through holes through the laminate by laser drilling; Paragraph 103, outline of the scale pattern is formed by means of exposing parts of the photoresist 104 through laser radiation), and then the conductor not covered with the resist pattern is removed by etching (Figure 4 Paragraph 106, exposed copper surface is irradiated with irradiation and a recess is developed in the exposed parts of the photoresist 104 by means of etching).
The Office further notes that forming a newly adjusted resist pattern (in which part of the film is removed) after an initial processing of the conductive layer is known in the art as evidenced by Figures 2B and 2C of LEE (US 20230180391 A1).
Regarding claim 7, Klocek as modified teaches the method as claimed in claim 1, further comprising:
a width of a laser- processed groove formed by the short-pulse laser is 3 um or more and 100 um or less (Paragraph 91, line width lower than 50 um such as 30 um can be achieved).
Regarding claim 12, Klocek as modified teaches the method as claimed in claim 1.
TAKIGUCHI further teaches:
the short-pulse laser is a laser that injects a pulse with a pulse width on an order of femtoseconds to picoseconds (Paragraph 17, ultrashort pulse laser is used to process the substrate with a pulse width on the order of femtoseconds).
It would have been obvious for the same motivation as claim 1.
Claim(s) 1-2, 7-9, and 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20230180391 A1) in view of Klocek (US 20210315104 A1) and TAKIGUCHI (JP 2008126230 A).
Regarding claim 1, Lee (US 20230180391 A1) teaches a manufacturing method of a scale pattern comprising:
preparing a substrate provided with a conductor on one main surface thereof (Paragraph 71, metal layer on an electrically insulating substrate 115);
forming an outline of the scale pattern on the conductor (Figure 2A Paragraph 72, metal layer 110 forming exposed areas in the film wherein pats of the metal layer below the holes will be exposed; Figure 2D Paragraph 74, second etch which enlarges the cavities)
removing at least a part of the conductor other than the scale pattern by etching (Figures 2B-2C Paragraph 72, a first etch is carried out which removes a further part of the exposed metal layer such as to form cavities within the metal layer and a further etch is carried out to thin the film).
Lee fails to explicitly teach:
forming an outline of the scale pattern on the conductor with a short-pulse laser;
Klocek (US 20210315104 A1) teaches an anisotropic etching method using photosensitive compound, comprising:
forming an outline of the scale pattern on the conductor with a laser (Figure 3 Paragraph 103, the photoresist layer after being exposed and developed by exposure to UV light forms a gap in which the outline of the scale pattern is formed through the short pulse laser developing a recess in the exposed parts of the photo recess);
It would have thus been obvious to someone of ordinary skill in the art before the filing date of the claimed invention to have modified Lee with Klocek and use a laser to perform the further etching of the conductive layer. This would have been done as to obtain an etched electrically conductive layer structure having a recess with a partially substantially vertically side walls which increases the overall quality of the component carrier (Klocek Paragraph 6).
Lee modified with Klocek fails to teach:
forming an outline of the scale pattern on the conductor with a short-pulse laser;
TAKIGUCHI (JP 2008126230 A) teaches a laser beam machining method of processing a workpiece such as a flexible circuit board (Paragraphs 1-4), comprising:
forming an outline of the conductor pattern on the conductor with a short-pulse laser (Paragraph 17, ultrashort pulse laser is used to process the substrate with a pulse width on the order of femtoseconds)
It would have thus been obvious to someone of ordinary skill in the art before the filing date of the claimed invention to have modified Lee with TAKIGUCHI and used an ultrashort pulse laser to process the printed circuit board. This would be done as the ultrashort pulse laser is known in the art to be functional in processing printed circuit boards and makes it possible to perform high-precision processing without thermal history (TAKIGUCHI Paragraph 17).
Regarding claim 2, Lee as modified teaches the method as claimed in claim 1 wherein,
after forming a resist pattern on the conductor by photolithography (Figure 2A Paragraph 71, film is patterned by photolithography on the metal layer 110), etching is performed using the resist pattern as a mask (Figures 2B-2C Paragraph 72, a first etch is carried out which removes a further part of the exposed metal layer such as to form cavities within the metal layer and a further etch is carried out to thin the film)
Klocek further teaches:
then the outline of the scale pattern is formed by the short pulse laser (Figure 3 Paragraph 103, the photoresist layer after being exposed and developed by exposure to UV light forms a gap in which the outline of the scale pattern is formed through the short pulse laser developing a recess in the exposed parts of the photo recess).
It would have been obvious for the same motivation as claim 1.
Regarding claim 7, Lee as modified teaches the method as claimed in claim 1.
Klocek further teaches:
a width of a laser- processed groove formed by the short-pulse laser is 3 um or more and 100 um or less (Paragraph 91, line width lower than 50 um such as 30 um can be achieved).
It would have been obvious for the same motivation as claim 1.
Regarding claim 8, Lee as modified teaches the method as claimed in claim 1, wherein
removing the conductor along the outline of the scale pattern to a depth greater than a thickness of the conductor (Figure 2D Paragraph 74, second etch which enlarges cavity 140 and further cavity 141 so that a metal trace is formed between the cavities wherein the depth at which the etching occurs extends into the component carrier 100).
Klocek further teaches:
wherein, in the forming the outline of the scale pattern, the short-pulse laser is irradiated onto the conductor along the outline of the scale pattern, thereby removing the conductor along the outline of the scale pattern (Figure 3 Paragraph 103, the photoresist layer after being exposed and developed by exposure to UV light forms a gap in which the outline of the scale pattern is formed through the short pulse laser developing a recess in the exposed parts of the photo recess).
It would have been obvious for the same motivation as claim 1.
Regarding claim 9, Lee as modified teaches the method as claimed in claim 1.
the scale pattern includes a plurality of patterns spaced from each other (Figures 2A-2D Paragraphs 73-74, plurality of metal layers 110 spaced from one another)
removing the conductor along the outline of the plurality of patterns to a depth greater than a thickness of the conductor (Figure 2D Paragraph 74, second etch which enlarges cavity 140 and further cavity 141 so that a metal trace is formed between the cavities wherein the depth at which the etching occurs extends into the component carrier 100)
wherein, in the removing, the conductor is removed between the plurality of patterns by etching (Paragraphs 71-74, metal layer is removed between the plurality of patterns by means of etching)
Klocek further teaches:
the scale pattern includes a plurality of patterns spaced from each other (Figure 3 Paragraph 106, electrically conductive layer structures having a recess 110 between them; Figure 3 Paragraph 103, said electrically conductive layer structures are placed upon electrically insulating layer structure 101),
wherein, in the forming the outline of the scale pattern, the short-pulse laser is irradiated onto the conductor along the outline of the plurality of patterns, thereby removing the conductor along the outline of the plurality of patterns (Figure 3 Paragraph 103, the photoresist layer after being exposed and developed by exposure to UV light forms a gap in which the outline of the scale pattern is formed through the short pulse laser developing a recess in the exposed parts of the photo recess between the electrically conductive layer structures), and
wherein, in the removing, the conductor is removed between the plurality of patterns by etching (Figure 4 Paragraph 106, exposed copper surface is irradiated with irradiation and a recess is developed in the exposed parts of the photoresist 104 by means of etching).
It would have been obvious for the same motivation as claim 1.
Regarding claim 11, Lee as modified teaches the method as claimed in claim 1.
Klocek further teaches:
wherein in the forming the outline of the scale pattern, edges of the plurality of patterns are removed by the short-pulse laser (Figure 4 Paragraph 106, exposed copper surface is irradiated with irradiation and a recess is developed in the exposed parts of the photoresist 104 by means of etching such as to form the edges of the plurality of patterns).
It would have been obvious for the same motivation as claim 1.
Regarding claim 12, Lee as modified teaches the method as claimed in claim 1.
TAKIGUCHI further teaches:
wherein the short-pulse laser is a laser that injects a pulse with a pulse width on an order of femtoseconds to picoseconds (Paragraph 17, ultrashort pulse laser is used to process the substrate with a pulse width on the order of femtoseconds).
It would have been obvious for the same motivation as claim 1.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20230180391 A1) as applied to claim 9 above, and further in view of Kang (US 20050205524 A1).
Regarding claim 10, Lee as modified teaches the method as claimed in claim 9, wherein
in the removing, the conductor is removed between the plurality of patterns by etching (Figures 2B-2C Paragraph 72, a first etch is carried out which removes a further part of the exposed metal layer such as to form cavities within the metal layer and a further etch is carried out to thin the film).
Lee as modified fails to teach:
in the removing, the plurality of patterns and at least part of a recess formed by irradiation of the short-pulse laser are covered by a resist
Kang (US 20050205524 A1) teaches a method of manufacturing tap wiring substrates, wherein:
in the removing, the plurality of patterns and at least part of a recess formed by irradiation of the short-pulse laser are covered by a resist (Figures 3A-3C Paragraphs 32-34, wiring pattern is formed using a laser are covered by a solder resist 340 which is coated on a portion of the base film such as to protect the wiring from an external impact)
It would have thus been obvious to someone of ordinary skill in the art before the filing date of the claimed invention to have modified Lee with Kang and have part of the removing process include covering at least part of a recess processed by the laser by a solder resist. This would be done to protect the wiring from an external impact (Kang Paragraph 33).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRANKLIN JEFFERSON WANG whose telephone number is (571)272-7782. The examiner can normally be reached M-F 10AM-6PM (E.S.T).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ibrahime Abraham can be reached at (571) 270-5569. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/F.J.W./Examiner, Art Unit 3761
/IBRAHIME A ABRAHAM/Supervisory Patent Examiner, Art Unit 3761
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