DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/24/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. A new rejection has been made over Lee (US 20050205524 A1) in view of Roos (US 20050098546 A1). A full rejection can be found below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 9, 11-12, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20050205524 A1) in view of Roos (US 20050098546 A1).
Regarding claim 1, Lee (US 20050205524 A1) teaches a manufacturing method of a scale pattern (Figures 3A-3C Paragraph 3, method of manufacturing a tape wiring substrate on which a wiring pattern is formed using a laser) comprising:
preparing a substrate (base film 310) provided with a conductor (metal layer 320) on one main surface thereof (Paragraph 30, metal layer 320 is formed on a base film 310);
forming an outline of the scale pattern on the conductor with a pulse laser (Paragraph 44, pulse type laser is used to etch the metal layer 320; Paragraph 49, forming of the wiring pattern 325 using the laser); and
removing at least a part of the conductor other than the scale pattern by etching (paragraph 49, thermal energy from the laser etches the metal layer 320 around the contact portion; the laser both forms an outline of the scale pattern as well as etches the conductor under broadest reasonable interpretation),
wherein, in forming the outline of the scale pattern, the pulse laser is irradiated onto the conductor along the outline of the scale pattern (Paragraph 44, pulse type laser is used to etch the metal layer 320; Paragraph 49, forming of the wiring pattern 325 using the laser), thereby removing the conductor along the outline of the scale pattern to a depth greater than the conductor while not completely penetrating the substrate (Figure 3A Paragraph 47, metal layer 320 is fully etched by the laser wherein the base film 310 positioned below the metal layer is also etched to a thickness of about 7.5um during the etching of the metal layer 320).
Lee fails to teach:
forming an outline of the scale pattern on the conductor with a short -pulse laser
Roos (US 20050098546 A1) teaches a method of defining features on materials with femtosecond laser, wherein:
forming an outline of the conductor pattern on the conductor with a short-pulse laser (Paragraph 18-19, cutting of defining features by removing material such as metal with a very short femtosecond laser pulse delivered at high repetition rates with wavelengths at approximately 250nm)
It would have thus been obvious to someone of ordinary skill in the art before the filing date of the claimed invention to have modified Lee with TAKIGUCHI and used an ultrashort pulse laser to form the outline of the conductor pattern. This would be done as said lasers offer extremely high precision machining when removing metal material with no heat or shock affected zone (Roos Paragraph 18).
The Office further notes that the use femtosecond lasers with a wavelength range of 540nm to 250nm is known in the art to be used for laser etching as evidenced by Lei (US 20110312157 A1).
Regarding claim 9, Lee as modified teaches the method as claimed in claim 1, wherein:
in wherein the scale pattern includes a plurality of patterns spaced from each other (Figure 3B, pattern of wiring pattern includes a plurality of wiring patterns 325 spaced from one another), and
wherein, in the removing, the conductor is removed between the plurality of patterns by etching (Paragraph 44, metal layer 320 except for wiring pattern 325 is etched by the laser such as to be removed).
Regarding claim 11, Lee as modified teaches the method as claimed in claim 1, wherein:
the scale pattern includes a plurality of patterns spaced from each other (Figure 3B, wiring pattern 325 comprises a plurality of patterns spaced from each other) and,
in the forming the outline of the scale pattern, edges of the plurality of patterns are removed by the short-pulse laser (Figures 3A-3B Paragraph 49, edges of the patterns are defined by using the laser to remove portions of the metal layer 320).
Regarding claim 12, Lee as modified teaches the method as claimed in claim 1.
TAKIGUCHI further teaches:
the short-pulse laser is a laser that injects a pulse with a pulse width on an order of femtoseconds to picoseconds (Paragraph 17, ultrashort pulse laser is used to process the substrate with a pulse width on the order of femtoseconds).
It would have been obvious for the same motivation as claim 1.
Regarding claim 14, Lee as modified teaches the method as claimed in claim 1, wherein:
in the forming the outline of the scale pattern, the short-pulse laser is irradiated onto the conductor along the outline of the scale pattern so that a surface shape of the outline is smooth and uniform (Figures 3A-3C, the scale pattern as a result of the laser processing has a smooth and uniform shape similar to that of Figures 3A-3C of the applicant’s drawings filed 12/06/2022 from which the applicant draws support for the limitation from).
The Office further notes that forming substantially rectangularly shaped surface conductors is known in the art to desirable and achievable by means of laser processing as evidenced by Paragraph 5 of Egitto (US 20080014409 A1).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20050205524 A1) in view of Roos (US 20050098546 A1) as applied to claim 1 above, and further in view of Johnson (US 20070212878 A1) and Kolodin (US 20090212317 A1).
Regarding claim 2, Lee as modified teaches the method as claimed in claim 1.
Lee as modified fails explicitly teach:
after forming a resist pattern on the conductor by photolithography, etching is performed using the resist pattern as a mask, and then the outline of the scale pattern is formed by the short pulse laser.
Johnson (US 20070212878 A1) teaches a method for producing conductive patterns, wherein:
after forming a resist pattern on the conductor (Paragraph 21, chemical etch refers to a process of masking areas of exposed metal to allow the unmasked regions to be removed by exposure to a chemical process), etching is performed using the resist pattern as a mask (Paragraph 21, chemical etch refers to a process of masking areas of exposed metal to allow the unmasked regions to be removed by exposure to a chemical process), and then the outline of the scale pattern is formed by the short pulse laser (Paragraph 43, chemical etching of the blanket layer of material is followed by a step of laser etching such as to provide gap width adjustments which would form the outline of the scale pattern).
It would have thus been obvious to someone of ordinary skill in the art before the filing date of the claimed invention to have modified Lee with Johnson and have a step of chemical etching be performed before forming the outline of the scale pattern by the laser. This would have been done to allow for the laser etching to provide a high level of precision (Johnson Paragraph 43), while reducing the process time by utilizing wet chemical etching which is known in the art to be a relatively fast process as evidenced by Paragraphs 26 and 33 of Kolodin (US 20090212317 A1).
While Lee modified with Johnson fails to explicitly teach that the step of forming a resist pattern on the conductor is performed “by photolithography”, the use of photolithographic wet chemical etching is a type of wet etching well-known in the art to be used for etching or removing material of an electrically conductive layer as evidenced by Paragraphs 23-25 of Kolodin (US 20090212317 A1). Kolodin additionally teaches that the wet etching is used in combination with laser cutting to form the circuitry pattern (Kolodin Paragraph 34). It would have thus been obvious to someone of ordinary skill in the art before the filing date of the claimed invention to have modified Lee with Kolodin and have the chemical etching be a photolithographic wet chemical etching wherein a resist pattern is formed first on a conductor by photolithography. This would have been done to cover the regions of the conductive layer while exposing the regions from which the conductive layer is to be removed (Kolodin Paragraphs 23-24).
Claim(s) 3-4 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20050205524 A1) in view of Roos (US 20050098546 A1) as applied to claim 1 above, and further in view of Egitto (US 20080014409 A1).
Regarding claim 3, Lee as modified teaches the method as claimed in claim 1.
Lee as modified fails to explicitly teach:
after forming the outline of the scale pattern on the conductor with the short pulse laser, a resist pattern is formed so as to cover the scale pattern, and then the conductor not covered with the resist pattern is removed by etching.
Egitto (US 20080014409 A1) teaches a fine line circuitization, wherein:
after forming the outline of the scale pattern on the conductor with the short pulse laser (Figure 8 Paragraph 34, interim side wall 66 is formed in a conductive layer 62 by means of laser or laser etching), a resist pattern is formed so as to cover the scale pattern (Figure 9 Paragraph 35, layer of patternable material 68 is positioned such as to cover the conductive layer including the scale pattern wherein the material is the same as patternable material 40; Paragraph 29, layer of patternable material 40 is an acrylic or an epoxy acrylic photosensitive material such as a photo resist or a soldermask; Figure 10 Paragraph 36, a portion of the patternable material 68 is removed such as to expose portions surrounding the scale pattern), and then the conductor not covered with the resist pattern is removed by etching (Figure 11 Paragraph 37, chemical etching is performed to remove portions of interim side wall and portion 70 of substantially planar upper surface).
It would have thus been obvious to someone of ordinary skill in the art before the filing date of the claimed invention to have modified Lee with Egitto and have the step of laser etching be followed by steps of forming a resist pattern and etching portions not covered by the resist pattern. This would have been done to produce a circuitized substrate in a relatively inexpensive yet effective process (Egitto Paragraph 38), while reducing the process time by utilizing wet chemical etching which is known in the art to be a relatively fast process as evidenced by Paragraphs 26 and 33 of Kolodin (US 20090212317 A1).
Regarding claim 4, Lee as modified teaches the method as claimed in claim 1, further comprising:
forming a plurality of the conductor spaced apart from each other, on the substrate so as to array (Figure 3B Paragraph 49, laser is used to form wiring pattern 325 which comprises a plurality of patterns spaced from each other).
Lee as modified fails to explicitly teach:
after forming the outline of the scale pattern on the conductor with the short pulse laser, a resist pattern is formed so as to cover the scale pattern, and then the conductor not covered with the resist pattern is removed by etching.
Egitto (US 20080014409 A1) teaches a fine line circuitization, wherein:
after forming the outline of the scale pattern on the conductor with the short pulse laser (Figure 8 Paragraph 34, interim side wall 66 is formed in a conductive layer 62 by means of laser or laser etching), a resist pattern is formed so as to cover the scale pattern (Figure 9 Paragraph 35, layer of patternable material 68 is positioned such as to cover the conductive layer including the scale pattern wherein the material is the same as patternable material 40; Paragraph 29, layer of patternable material 40 is an acrylic or an epoxy acrylic photosensitive material such as a photo resist or a soldermask; Figure 10 Paragraph 36, a portion of the patternable material 68 is removed such as to expose portions surrounding the scale pattern), and then the conductor not covered with the resist pattern is removed by etching (Figure 11 Paragraph 37, chemical etching is performed to remove portions of interim side wall and portion 70 of substantially planar upper surface).
It would have thus been obvious to someone of ordinary skill in the art before the filing date of the claimed invention to have modified Lee with Egitto and have the step of laser etching be followed by steps of forming a resist pattern and etching portions not covered by the resist pattern. This would have been done to produce a circuitized substrate in a relatively inexpensive yet effective process (Egitto Paragraph 38), while reducing the process time by utilizing wet chemical etching which is known in the art to be a relatively fast process as evidenced by Paragraphs 26 and 33 of Kolodin (US 20090212317 A1).
Regarding claim 10, Lee as modified teaches the method as claimed in claim 9.
Lee as modified fails to teach:
in the removing, the plurality of patterns and at least part of a recess formed by irradiation of the short-pulse laser are covered by a resist, and the conductor is removed between the plurality of patterns by etching.
Egitto (US 20080014409 A1) teaches a fine line circuitization, wherein:
in the removing, the plurality of patterns and at least part of a recess formed by irradiation of the short-pulse laser are covered by a resist (Figure 9 Paragraph 35, layer of patternable material 68 is positioned such as to cover the conductive layer including the scale pattern wherein the material is the same as patternable material 40; Paragraph 29, layer of patternable material 40 is an acrylic or an epoxy acrylic photosensitive material such as a photo resist or a soldermask; Figure 10 Paragraph 36, a portion of the patternable material 68 is removed such as to expose portions surrounding the scale pattern), and the conductor is removed between the plurality of patterns by etching (Figure 11 Paragraph 37, chemical etching is performed to remove portions of interim side wall and portion 70 of substantially planar upper surface).
It would have thus been obvious to someone of ordinary skill in the art before the filing date of the claimed invention to have modified Lee with Egitto and have the step of laser etching be followed by steps of forming a resist pattern and etching portions not covered by the resist pattern. This would have been done to produce a circuitized substrate in a relatively inexpensive yet effective process (Egitto Paragraph 38), while reducing the process time by utilizing wet chemical etching which is known in the art to be a relatively fast process as evidenced by Paragraphs 26 and 33 of Kolodin (US 20090212317 A1).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20050205524 A1) in view of Roos (US 20050098546 A1) as applied to claim 1 above, and further in view of NAIR (US 20140353005 A1).
Regarding claim 7, Lee as modified teaches the method as claimed in claim 1.
Lee as modified fails to explicitly teach:
a width of a laser- processed groove formed by the short-pulse laser is 3 um or more and 100 um or less.
NAIR (US 20140353005 A1) teaches a method of making microwave electronic circuits, wherein:
a width of a laser- processed groove formed by the short-pulse laser is 3 um or more and 100 um or less (Paragraph 15, laser beam with a wavelength in the range of 240nm-350nm is used to obtain a line with between 25.4 microns and 75 microns by ablation of the metallization upon laser pass; Paragraph 20, varied gap widths of 30/40/50/60/100 microns are also achievable).
It would have thus been obvious to someone of ordinary skill in the art before the filing date of the claimed invention to have modified Lee with NAIR and have the width of the laser-process groove formed by the laser be within the range of 3 microns to 100 microns. This would have been done to form high resolution conductor patterns (NAIR Paragraph 14).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRANKLIN JEFFERSON WANG whose telephone number is (571)272-7782. The examiner can normally be reached M-F 10AM-6PM (E.S.T).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ibrahime Abraham can be reached at (571) 270-5569. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/F.J.W./Examiner, Art Unit 3761
/WOODY A LEE JR/Primary Examiner, Art Unit 3761
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