CTFR 18/076,130 CTFR 92321 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1-20 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Wu et al. (US 20220310452 A1, hereinafter Wu ) With regards to claim 1 , Wu discloses an integrated circuit structure, (FIG. 14) comprising: a plurality of gate structures (at least metal gate 250) over corresponding ones of a plurality of vertical stacks of horizontal nanowires; (semiconductor nanowires 210A) a plurality of conductive trench contact structures (contacts 260) alternating with the plurality of gate structures, each of the plurality of conductive contact structures having an upper portion (portion of 260 not contacting spacer 248) over a lower portion, (portion of 260 directly contacting spacer 248) the upper portion of each of the plurality of conductive trench contact structures having a length between ends; and a dielectric liner (liner 248 and portion of ILD 256 over ILD liner 248) in lateral contact with sides along the length of the upper portion of each of the plurality of conductive contact structures, wherein the dielectric liner is not in contact with the ends of the upper portion of each of the plurality of conductive contact structures, (see FIG. 14, showing a lack of contact with the upper sides of 260) and wherein the dielectric liner has an uppermost surface at a same level as an uppermost surface of the upper portion of each of the plurality of conductive contact structures. (see FIG. 14, wherein the top portion of ILD 256 above liner 248 is at a same level as the contacts 260, see response to Arguments) With regards to claim 2 , Wu discloses the integrated circuit structure of claim 1, further comprising: a gate contact via (contact 270) in contact with one of the plurality of gate structures, the gate contact via laterally adjacent to the dielectric liner on of one the sides of one of the upper portions of one of the plurality of conductive trench contact structures. (see FIG. 14, showing the lateral adjacency) With regards to claim 3 , Wu discloses the integrated circuit structure of claim 1, further comprising: a plurality of epitaxial source or drain structures, (S/D features 240) each of the plurality of epitaxial source or drain structures between ends of corresponding ones of the plurality of vertical stacks of horizontal nanowires. (paragraph [0027]: “the S/D features 240 are epitaxially grown in the S/D trenches 224…”) With regards to claim 4 , Wu discloses the integrated circuit structure of claim 1, further comprising: a plurality of dielectric spacers, (ILD layers 222 and portion of ILD 256 not over liner 248) a corresponding one of the plurality of dielectric spacers between adjacent ones of the plurality of gate structures and corresponding ones the plurality of conductive trench contact structures, the plurality of dielectric spacers having an uppermost surface at a same level as an uppermost surface of the upper portion of each of the plurality of conductive contact structures. (see FIG. 14, showing the same heights) With regards to claim 5 , Wu discloses the integrated circuit structure of claim 1, wherein the dielectric liner comprises silicon and carbon, (Paragraph [0029]: “the ILD layer 248 comprises a low-k (K<3.9) dielectric material, such as tetraethylorthosilicate (TEOS), un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), other suitable dielectric materials, or combinations thereof.” Thus, silicon and carbon are included) or wherein the dielectric liner comprises silicon and nitrogen. With regards to claim 6 , Wu discloses an integrated circuit structure, (FIG. 14) comprising: a plurality of gate structures (gate structures 250) over corresponding ones of a plurality of fins; (fins 210) a plurality of conductive trench contact structures (contacts 260) alternating with the plurality of gate structures, each of the plurality of conductive contact structures having an upper portion (portion of 260 not contacting spacer 248) over a lower portion, (portion of 260 directly contacting spacer 248) the upper portion of each of the plurality of conductive trench contact structures having a length between ends; and a dielectric liner (liner 248 and portion of ILD 256 over ILD liner 248) in lateral contact with sides along the length of the upper portion of each of the plurality of conductive contact structures, wherein the dielectric liner is not in contact with the ends of the upper portion of each of the plurality of conductive contact structures. (see FIG. 14, showing a lack of contact with the upper sides of 260) and wherein the dielectric liner has an uppermost surface at a same level as an uppermost surface of the upper portion of each of the plurality of conductive contact structures. (see FIG. 14, wherein the top portion of ILD 256 above liner 248 is at a same level as the contacts 260, see response to Arguments) With regards to claim 7 , Wu discloses the integrated circuit structure of claim 6, further comprising: a gate contact via (contact 270) in contact with one of the plurality of gate structures, the gate contact via laterally adjacent to the dielectric liner on of one the sides of one of the upper portions of one of the plurality of conductive trench contact structures. (see FIG. 14, showing the lateral adjacency) With regards to claim 8 , Wu discloses the integrated circuit structure of claim 6, further comprising: a plurality of epitaxial source or drain structures, (S/D features 240, see paragraph [0027]) each of the plurality of epitaxial source or drain structures between ends of corresponding ones of the plurality of fins. (see FIG. 14) With regards to claim 9 , Wu discloses the integrated circuit structure of claim 6, further comprising: a plurality of dielectric spacers, (ILD layers 222 and portion of ILD 256 not over liner 248) a corresponding one of the plurality of dielectric spacers between adjacent ones of the plurality of gate structures and corresponding ones the plurality of conductive trench contact structures, the plurality of dielectric spacers having an uppermost surface at a same level as an uppermost surface of the upper portion of each of the plurality of conductive contact structures. (see FIG. 14, showing the placement and same heights) With regards to claim 10 , Wu discloses the integrated circuit structure of claim 6, wherein the dielectric liner comprises silicon and carbon, or wherein the dielectric liner comprises silicon and nitrogen. (Paragraph [0029]: “the ILD layer 248 comprises a low-k (K<3.9) dielectric material, such as tetraethylorthosilicate (TEOS), un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), other suitable dielectric materials, or combinations thereof.” Thus, silicon and carbon are included) With regards to claim 11 , Wu discloses an computing device, (FIGS. 2-14) comprising: a board; (Examiner is taking official notice that components, such as those shown in FIG. 2, are coupled to a circuit board) and a component (integrated circuit shown in FIGS. 2 and 14) coupled to the board, the component including an integrated circuit structure, comprising: a plurality of gate structures (gates 250) over corresponding ones of a plurality of vertical stacks of horizontal nanowires; (semiconductor nanowires 210A) a plurality of conductive trench contact structures (contacts 260) alternating with the plurality of gate structures, each of the plurality of conductive contact structures having an upper portion (portion of 260 not contacting spacer 248) over a lower portion, (portion of 260 directly contacting spacer 248) the upper portion of each of the plurality of conductive trench contact structures having a length between ends; and a dielectric liner (liner 248 and portion of ILD 256 over ILD liner 248) in lateral contact with sides along the length of the upper portion of each of the plurality of conductive contact structures, wherein the dielectric liner is not in contact with the ends of the upper portion of each of the plurality of conductive contact structures, (see FIG. 14, showing a lack of contact with the upper sides of 260) and wherein the dielectric liner has an uppermost surface at a same level as an uppermost surface of the upper portion of each of the plurality of conductive contact structures. (see FIG. 14, wherein the top portion of ILD 256 above liner 248 is at a same level as the contacts 260, see response to Arguments) With regards to claim 12 , Wu discloses the computing device of claim 11, further comprising: a memory (memory, see Paragraphs [0012]-[0014]) coupled to the board. With regards to claim 13 , Wu discloses the computing device of claim 11, further comprising: a communication chip (I/O region, see paragraphs [0012]-[0014]) coupled to the board. (Examiner takes official notice that the current application can be used in different electronic applications, such as cell phones, see at least Chen et al. (US 20220102494 A1) Paragraph [0002]) With regards to claim 14 , Wu discloses the computing device of claim 11, further comprising: a camera coupled to the board. (Examiner takes official notice that the current application can be used in different electronic applications, such as camera, see at least Chen et al. (US 20220102494 A1) Paragraph [0002]) With regards to claim 15 , Wu discloses the computing device of claim 11, wherein the component is a packaged integrated circuit die. (see FIGS. 2-14, showing the component on the board, and paragraph [0012]) With regards to claim 16 , Wu discloses a computing device, (FIGS. 2-14) comprising: a board; (substrate 2020) and a component coupled to the board, the component including an integrated circuit structure, (FIGS. 2-14) comprising: a plurality of gate structures (gate 250) over corresponding ones of a plurality of fins; (at least fins of substrate 202) a plurality of conductive trench contact structures (contacts 260) alternating with the plurality of gate structures, each of the plurality of conductive contact structures having an upper portion (portion of 260 not contacting spacer 248) over a lower portion, (portion of 260 directly contacting spacer 248) the upper portion of each of the plurality of conductive trench contact structures having a length between ends; and a dielectric liner (liner 248 and portion of ILD 256 over ILD liner 248) in lateral contact with sides along the length of the upper portion of each of the plurality of conductive contact structures, wherein the dielectric liner is not in contact with the ends of the upper portion of each of the plurality of conductive contact structures, (see FIG. 14, showing a lack of contact with the upper sides of 260) and wherein the dielectric liner has an uppermost surface at a same level as an uppermost surface of the upper portion of each of the plurality of conductive contact structures. (see FIG. 14, wherein the top portion of ILD 256 above liner 248 is at a same level as the contacts 260, see response to Arguments) With regards to claim 17 , Wu discloses the computing device of claim 16, further comprising: a memory (memory, see Paragraph [0012]) coupled to the board. (see FIGS. 2 and 14) With regards to claim 18 , Wu discloses the computing device of claim 16, further comprising: a communication chip coupled to the board. (Examiner takes official notice that the current application can be used in different electronic applications, such as cell phones, see at least Chen et al. (US 20220102494 A1) Paragraph [0002]) With regards to claim 19, Wu discloses the computing device of claim 16, further comprising: a camera coupled to the board. (Examiner takes official notice that the current application can be used in different electronic applications, such as camera, see at least Chen et al. (US 20220102494 A1) Paragraph [0002]) With regards to claim 20 , Wu discloses the computing device of claim 16, wherein the component is a packaged integrated circuit die. (see Paragraph [0012]) Response to Arguments 07-37 AIA Applicant's arguments filed 05/04/2026 have been fully considered but they are not persuasive. Based on the new amendments, Examiner has amended the interpretation to contain a portion of the ILD 256 to be a portion of the dielectric liner, which meets the limitations of at least claims 1, 6, 11, and 16. It should be noted that since the ILD layers can be made using CVD, (See at least paragraph [0014]) a proper interpretation can be made to split the layer 256 into multiple layers, and to have multiple layers considered one “layer.” Therefore, claims 1, 6, 11, and 16 are rejected, and claims 2-5, 7-10, 12-15, and 17-20 are rejected for at least their dependencies . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Bi et al. (US 20200287039 A1) – semiconductor nanowires in a gate structure Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8548. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812 Application/Control Number: 18/076,130 Page 2 Art Unit: 2812 Application/Control Number: 18/076,130 Page 3 Art Unit: 2812 Application/Control Number: 18/076,130 Page 4 Art Unit: 2812 Application/Control Number: 18/076,130 Page 5 Art Unit: 2812 Application/Control Number: 18/076,130 Page 6 Art Unit: 2812 Application/Control Number: 18/076,130 Page 7 Art Unit: 2812 Application/Control Number: 18/076,130 Page 8 Art Unit: 2812 Application/Control Number: 18/076,130 Page 9 Art Unit: 2812 Application/Control Number: 18/076,130 Page 10 Art Unit: 2812
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