DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu et al. (US 20220310452 A1, hereinafter Wu)
With regards to claim 1, Wu discloses an integrated circuit structure, (FIG. 14) comprising:
a plurality of gate structures (at least metal gate 250) over corresponding ones of a plurality of vertical stacks of horizontal nanowires; (semiconductor nanowires 210A)
a plurality of conductive trench contact structures (contacts 260) alternating with the plurality of gate structures, each of the plurality of conductive contact structures having an upper portion (portion of 260 not contacting spacer 248) over a lower portion, (portion of 260 directly contacting spacer 248) the upper portion of each of the plurality of conductive trench contact structures having a length between ends; and
a dielectric liner (liner 248) in lateral contact with sides along the length of the upper portion of each of the plurality of conductive contact structures,
wherein the dielectric liner is not in contact with the ends of the upper portion of each of the plurality of conductive contact structures. (see FIG. 14, showing a lack of contact with the upper sides of 260)
With regards to claim 2, Wu discloses the integrated circuit structure of claim 1, further comprising:
a gate contact via (contact 270) in contact with one of the plurality of gate structures, the gate contact via laterally adjacent to the dielectric liner on of one the sides of one of the upper portions of one of the plurality of conductive trench contact structures. (see FIG. 14, showing the lateral adjacency)
With regards to claim 3, Wu discloses the integrated circuit structure of claim 1, further comprising:
a plurality of epitaxial source or drain structures, (S/D features 240) each of the plurality of epitaxial source or drain structures between ends of corresponding ones of the plurality of vertical stacks of horizontal nanowires. (paragraph [0027]: “the S/D features 240 are epitaxially grown in the S/D trenches 224…”)
With regards to claim 4, Wu discloses the integrated circuit structure of claim 1, further comprising:
a plurality of dielectric spacers, (ILD layers 256/222) a corresponding one of the plurality of dielectric spacers between adjacent ones of the plurality of gate structures and corresponding ones the plurality of conductive trench contact structures, the plurality of dielectric spacers having an uppermost surface at a same level as an uppermost surface of the upper portion of each of the plurality of conductive contact structures. (see FIG. 14, showing the same heights)
With regards to claim 5, Wu discloses the integrated circuit structure of claim 1, wherein the dielectric liner comprises silicon and carbon, (Paragraph [0029]: “the ILD layer 248 comprises a low-k (K<3.9) dielectric material, such as tetraethylorthosilicate (TEOS), un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), other suitable dielectric materials, or combinations thereof.” Thus, silicon and carbon are included) or wherein the dielectric liner comprises silicon and nitrogen.
With regards to claim 6, Wu discloses an integrated circuit structure, (FIG. 14) comprising:
a plurality of gate structures (gate structures 250) over corresponding ones of a plurality of fins; (fins 210)
a plurality of conductive trench contact structures (contacts 260) alternating with the plurality of gate structures, each of the plurality of conductive contact structures having an upper portion (portion of 260 not contacting spacer 248) over a lower portion, (portion of 260 directly contacting spacer 248) the upper portion of each of the plurality of conductive trench contact structures having a length between ends; and
a dielectric liner (liner 248) in lateral contact with sides along the length of the upper portion of each of the plurality of conductive contact structures, wherein the dielectric liner is not in contact with the ends of the upper portion of each of the plurality of conductive contact structures. (see FIG. 14, showing a lack of contact with the upper sides of 260)
With regards to claim 7, Wu discloses the integrated circuit structure of claim 6, further comprising:
a gate contact via (contact 270) in contact with one of the plurality of gate structures, the gate contact via laterally adjacent to the dielectric liner on of one the sides of one of the upper portions of one of the plurality of conductive trench contact structures. (see FIG. 14, showing the lateral adjacency)
With regards to claim 8, Wu discloses the integrated circuit structure of claim 6, further comprising:
a plurality of epitaxial source or drain structures, (S/D features 240, see paragraph [0027]) each of the plurality of epitaxial source or drain structures between ends of corresponding ones of the plurality of fins. (see FIG. 14)
With regards to claim 9, Wu discloses the integrated circuit structure of claim 6, further comprising:
a plurality of dielectric spacers, (ILD layers 256/222) a corresponding one of the plurality of dielectric spacers between adjacent ones of the plurality of gate structures and corresponding ones the plurality of conductive trench contact structures, the plurality of dielectric spacers having an uppermost surface at a same level as an uppermost surface of the upper portion of each of the plurality of conductive contact structures. (see FIG. 14, showing the placement and same heights)
With regards to claim 10, Wu discloses the integrated circuit structure of claim 6, wherein the dielectric liner comprises silicon and carbon, or wherein the dielectric liner comprises silicon and nitrogen. (Paragraph [0029]: “the ILD layer 248 comprises a low-k (K<3.9) dielectric material, such as tetraethylorthosilicate (TEOS), un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), other suitable dielectric materials, or combinations thereof.” Thus, silicon and carbon are included)
With regards to claim 11, Wu discloses an computing device, (FIGS. 2-14) comprising:
a board; (Examiner is taking official notice that components, such as those shown in FIG. 2, are coupled to a circuit board) and
a component (integrated circuit shown in FIGS. 2 and 14) coupled to the board, the component including an integrated circuit structure, comprising:
a plurality of gate structures (gates 250) over corresponding ones of a plurality of vertical stacks of horizontal nanowires; (semiconductor nanowires 210A)
a plurality of conductive trench contact structures alternating with the plurality of gate structures, each of the plurality of conductive contact structures having an upper portion over a lower portion, the upper portion of each of the plurality of conductive trench contact structures having a length between ends; and
a dielectric liner in lateral contact with sides along the length of the upper portion of each of the plurality of conductive contact structures, wherein the dielectric liner is not in contact with the ends of the upper portion of each of the plurality of conductive contact structures.
With regards to claim 12, Wu discloses the computing device of claim 11, further comprising: a memory coupled to the board.
With regards to claim 13, Wu discloses the computing device of claim 11, further comprising: a communication chip coupled to the board.
With regards to claim 14, Wu discloses the computing device of claim 11, further comprising: a camera coupled to the board.
With regards to claim 15, Wu discloses the computing device of claim 11, wherein the component is a packaged integrated circuit die.
With regards to claim 16, Wu discloses a computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a plurality of gate structures over corresponding ones of a plurality of fins;
a plurality of conductive trench contact structures (contacts 260) alternating with the plurality of gate structures, each of the plurality of conductive contact structures having an upper portion (portion of 260 not contacting spacer 248) over a lower portion, (portion of 260 directly contacting spacer 248) the upper portion of each of the plurality of conductive trench contact structures having a length between ends; and
a dielectric liner (liner 248) in lateral contact with sides along the length of the upper portion of each of the plurality of conductive contact structures, wherein the dielectric liner is not in contact with the ends of the upper portion of each of the plurality of conductive contact structures. (see FIG. 14, showing a lack of contact with the upper sides of 260)
With regards to claim 17, Wu discloses the computing device of claim 16, further comprising:
a memory (memory, see Paragraph [0012]) coupled to the board. (see FIGS. 2 and 14)
With regards to claim 18, Wu discloses the computing device of claim 16, further comprising:
a communication chip coupled to the board. (Examiner takes official notice that the current application can be used in different electronic applications, such as cell phones, see at least Chen et al. (US 20220102494 A1) Paragraph [0002])
With regards to claim 19, Wu discloses the computing device of claim 16, further comprising:
a camera coupled to the board. (Examiner takes official notice that the current application can be used in different electronic applications, such as camera, see at least Chen et al. (US 20220102494 A1) Paragraph [0002])
With regards to claim 20, Wu discloses the computing device of claim 16, wherein the component is a packaged integrated circuit die. (see Paragraph [0012])
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Bi et al. (US 20200287039 A1) – semiconductor nanowires in a gate structure
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM.
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/STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812
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