Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Regarding claims 1, 3-11, 13-16 rejected under 35 U.S.C. 112(b), applicant amendment has been fully considered. The amendment overcomes the 35 U.S.C. 112(b) rejections of claims 1-5, 9-10, 15-16, hence 35 U.S.C. 112(b) rejection is withdrawn for claims 1-5, 10, 15-16. However, the amendment does not overcome the 35 U.S.C. 112(b) rejections of claims 6-8, 11-14, hence the 35 U.S.C. 112(b) rejection is maintained.
Applicant’s arguments with respect to claim(s) 1, 3-11, 13-16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Office now relies on new reference Lin (US 20170011988 A1) for the amended claims as necessitated by the amendments explained below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-8, 11-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites the limitation “…the back side of the substrate to create a void.” There is insufficient antecedent basis for this limitation in the claim since it does not recite “a back side of the substrate” prior to this in the claim. For the purpose of this examination, claim 6 will be interpreted as “the back side of the wafer”.
Claims 7-8 are rejected under 35 U.S.C. 112(b) for their dependency of claim 6.
Claim 11 recites the limitation “…back side of the substrate…”. There is insufficient antecedent basis for this limitation in the claim since it does not recite “a back side of the substrate” prior to this in the claim. For the purpose of this examination, claim 11 will be interpreted as “…back side of the wafer with the insulator further comprises applying the insulator wherein a thickness at a back side of the wafer...”.
Claim 13 is rejected under 35 U.S.C. 112(b) for the claim’s dependency of claim 11.
Claim 14 recites the limitation “…the etched back side of the substrate…”. There is insufficient antecedent basis for this limitation in the claim since it does not recite “a back side of the substrate” prior to this in the claim. For the purpose of this examination, claim 11 will be interpreted as “…the etched back side of the wafer…”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4, 6-7, 9-10, 14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Farooq (US 20140073134 A1) in view of Lin (US 20170011988 A1).
Re: Independent Claim 1 (Currently Amended), Farooq discloses a method comprising:
creating a partial through substrate via (TSV) plug (Farooq, Fig 5B, ¶ [0008] and ¶ [0032], top section via 520 is plugged with fill material 524) in a front side of a wafer (Farooq, Fig 5B, ¶ [0032], wafer with top section via 520; substrate has bottom surface 512) having an insulating layer and a substrate (Farooq teaches, in Fig. 1 and ¶ [0020], dielectric layer 150 over substrate 110; and Farooq further states the processing step can similarly be applied to other embodiments, and with respect to Fig. 5B conductive plug embodiment, states that “as previously described” front-end and back-end processing can be completed after a top section via is lined and plugged), the partial TSV plug having a front side (Farooq, Fig 5B, top end of top via 520 sealed by fill 524) and a back side (Farooq, Fig 5B, bottom face of fill 524 at the interface 537), the back side of the partial TSV extending through a front side of the second layer (Farooq, Fig 5B, ¶ [0032] top via 520 was formed from the front side through the front-side dielectric stack into the substrate before backside steps-therefore the plug's back face at 537 lies below/through the front surface of the second layer);
etching a cavity in a back side of the wafer that exposes the back side of the partial TSV plug (Fig 4B, ¶ [0026], etch bottom/back-side via 430 to at least partially expose the bottom end 425 of the front-formed top via);
applying an insulator to the etched back side of the wafer to coat an inner surface of the cavity with the insulator (Farooq, Fig 4B, ¶ [0026], deposit dielectric liner 432 on the sidewalls of bottom via 430, with deposition also occurring over remote end 435 of the bottom via 430; liner 432 is a conformal dielectric);
exposing the back side of the partial TSV plug by removing a portion of the insulator from the inner surface of the cavity near the back side of the partial TSV plug (Farooq, Fig 4C, ¶¶ [0026]- [0027], liner 432 is deposited over the sidewalls and remote end 435 of bottom via 430, thereby coating the inner surface of the cavity, and anisotropic etch removes liner 432 from via end 425 (and 422, if present) to join sections);
depositing a conductive material to connect the exposed back side of the partial TSV plug to a surface on the back side of the wafer and coating the inner surface of the cavity with the conductive layer (Farooq, Fig 5A and 5B, ¶¶ [0032]-[0033], depositing conductive fill 536 to form conductive path starting from the exposed bottom face of fill 524 at interface 537 and extending to the wafer's backside surface 512; Farooq further teaches, in ¶ [0030], that the lower section need not to completely filled and may instead have only a conductive coating 548 on the lower section surfaces); and adding a protective insulation layer over a portion of the conductive material, wherein adding the protective insulation layer comprises: filling the cavity with the protective insulation layer (Farooq teaches, in ¶ [0027], it may be desirable to form protective layer 413 over substrate 412. Farooq teaches filling the cavity with protective insulation layer because, in ¶ [0030], Farooq teaches the remaining portion of the bottom section could be filled with a CVD/flowable oxide or organic dielectric 549. Accordingly, this dielectric 549 reads on the claimed protective insulation layer, because the instant application describes the protective insulation layer as “dielectric layer” and as substantially covering the back side of the conductive layer).
Farooq is silent regarding
maintaining a connection region to the conductive layer deposited on the surface of the back side of the wafer, enabling an electrical connection through the protective insulation layer.
However, Lin teaches
maintaining a connection region to the conductive layer deposited on the surface of the back side of the wafer, enabling an electrical connection through the protective insulation layer (Li teaches, in Fig. 8 and ¶ [0019], passivation layer 60, which is a dielectric material, formed over conductive element 40” and isolation film 30; the passivation layer is then patterned to form contact opening 62 exposing portion 40D of conductive 40”, or in Fig. 16 and ¶ [0026], opening 64 exposing portion 40E of conductive element 40”, and a connection element cab be formed on the exposed portion. Thus, Lin teaches preserving an electrically accessible connection region through an overlying dielectric/passivation layer to an underlying backside conductive feature).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Farooq so that the dielectric fill material in the backside cavity is arranged to preserve a connection region to the backside conductive layer, as taught by Lin in order to insulate and protect the backside conductive material while still preserving electric access for a later connection element.
Re: Claim 3 (Currently amended), Farooq and Lin disclose all the limitations of claim 1 on which this claim depends.
Lin further teaches
further comprising attaching a conductive connection to the connection region (Lin, in ¶ [0019], teaches passivation layer 60 is patterned to form contact opening 62 exposing portion 40D of conductive element 40”, or alternatively, in ¶ [0026], opening 64 exposing portion 40E of conductive element 40”; a connective element can be formed in the exposed portion; the connection element may be any suitable conductive material such as Cu, Ni, etc. and may be formed by electroplating, printing, jetting, or wire bonding, etc.).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to attach a conductive connection to the connection region of the modified Farooq structure as taught by Lin in order to provide an external electrical connection to the backside conductive feature through the connection region.
Re: Claim 4 (Currently amended), Farooq and Lin disclose all the limitations of claim 3 on which this claim depends.
wherein the conductive connection is selected from the group consisting of an aluminum pad, a Ni-Au pad, a solder ball, or a copper pillar (Liu teaches, in ¶ [0019], conductive connection element may be anu suitable conductive material such as Cu, Ni, Sn, Au, Ag, solder or the like, which reads on the claimed solder ball).
Re: Claim 6 (Original), Farooq and Lin disclose all the limitations of claim 1 on which this claim depends. Farooq further discloses,
wherein creating the partial TSV plug in the front side of the wafer further comprises, applying a plasma to the back side of the substrate to create a void (Farooq, Fig 4A, ¶ [0023], form bottom via 430 from back surface 412 by plasma etch).
Re: Claim 7 (Original), Farooq and Lin disclose all the limitations of claim 6 on which this claim depends. Farooq further discloses,
further comprising lining or filling the void with a second conductive material (Farooq, Fig 5A, ¶ [0030], forming a conductive coating 548 of sufficient thickness on the bottom-section surface i.e., lining the void).
Re: Claim 9 (Original), Farooq and Lin disclose all the limitations of claim 1 on which this claim depends. Farooq further discloses,
wherein the partial TSV plug extends into one or more of an insulating layer (Farooq, Fig 1, ¶ [0020], the plugged/filled top via 120 with fill 124 passes through dielectric layers 150), a routing layer (Farooq, Fig 1, ¶ [0020], plugged top via directly contacting a BEOL contact 150 formed in further dielectric 151), and an SOI layer (Farooq, ¶ [0021], 120 filled with 124 extends into substrate which can be SOI layer).
Re: Claim 10 (Original), Farooq and Lin disclose all the limitations of claim 1 on which this claim depends. Farooq further discloses,
wherein the back side of the partial TSV plug (Farooq, Fig 5B, back side of plug 524 inside top via 520) extends through the front side of the substrate and partially into a bulk of the substrate (Farooq, Fig 5B, plug 524 resides within the substrate body beneath its front side i.e., the plug's back face at interface 537 is located inside the substrate rather than at the surface).
Re: Claim 14 (Original), Farooq and Lin disclose all the limitations of claim 1 on which this claim depends. Farooq further discloses,
wherein exposing the back side of the partial TSV plug by removing the portion of the insulator further comprises applying a directional etch to the etched back side of the substrate with the insulator (Farooq, Fig 4C, ¶ [0027], anisotropic (directional) etch is applied at the back side 412 where insulator/liner 432 is present, to remove a portion of the liner 432 at the junction and expose the back end 425 of the top (partial) via 420).
Re: Claim 16 (Original), Farooq discloses all the limitations of claim 1 on which this claim depends. Farooq further discloses,
wherein etching the cavity in the back side of the substrate exposes the back side of the partial TSV plug (Farooq, Fig 4A/4B, bottom via 430 is etched from the back side (bottom surface 412) to expose the back/bottom end 425 of the partial top via 420 that is plugged with fill 424).
Claims 5, 8, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Farooq (US 20140073134 A1) in view of Lin (US 20170011988 A1).
Re: Claim 5 (Original), Farooq and Lin disclose all the limitations of claim 1 on which this claim depends. Farooq further discloses,
wherein the partial TSV plug has a vertical dimension (Fig 5B, Depth d(top) of the top/front via 520 with plug 524) and a horizontal dimension (Fig 5B, top via width 521).
Farooq does not explicitly disclose wherein a ratio between the vertical dimension and the horizontal dimension is in a range between 1:4 and 7:1. However, Farooq teaches in ¶ [0024], aspect ratio (AR) is a design variable picked for manufacturability: length to width (aspect ratio) between 10 and 1, and preferably 1.5-5. The claimed range 1:4 to 1:7 (i.e., 0.25<=AR<=7) overlaps Farooq's taught 1<=AR<=10, preferably 1.5-5.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to select an aspect ratio within the overlapping portion (e.g. 1.5-5) for the partial plug as a routine optimization of a result-effective variable to achieve the known process goals Farooq identifies such as liner/seed coverage, void-free fill (Farooq, ¶ [0029]).
Re: Claim 8 (Original), Farooq and Lin disclose all the limitations of claim 7 on which this claim depends.
Farooq further discloses, in different embodiment,
wherein the second conductive material is selected from the group consisting of Copper, Aluminum, Tungsten, a solder, Tin/Silver, alloys thereof, a conductive ceramic, a conductive polymer, and combinations thereof (Farooq, ¶ [0034], Farooq teaches in another embodiment in Fig 7, second conductive material 730 could be Copper (Cu)).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use copper as second conductive material in the embodiment of figure 5 in order to achieve low resistance TSV fill.
Re: Claim 15 (Currently amended), Farooq and Lin disclose all the limitations of claim 1 on which this claim depends.
Farooq further discloses,
wherein the partial TSV plug has a vertical dimension (Farooq, Fig 5B, Depth d(top) of the top/front via 520 with plug 524; see also Fig.1 top section via 120 extending into substrate 110 to depth D(top)) and a horizontal dimension (Farooq, Fig 5B, top via width 521; see also Fig. 1 top section via 120 having cross section 121).
Farooq does not explicitly disclose wherein the vertical dimension is approximately equal to the horizontal dimension. However, Farooq teaches in ¶ [0024], that top section depth is selected relative to the top section cross section based a manageable aspect ratio, and teaches, in ¶ [0018]-¶ [0019], example dimensions for the top section via, including a top-section depth of 2-10 microns and a top-section cross section in ranges including 0.04 to 5 microns, with the particular design selections and fill characteristics determining the extent of manageable aspect ratio.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to select the known vertical and horizontal dimensions of Farooq’s partial TSV plug so that the vertical dimension is approximately equal to the horizontal dimension, in order to achieve a workable aspect ratio so the top section via can be filled or plugged with a sacrificial fill material so that top side processing can be continued (Farooq, ¶ [0006]).
Claims 11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Farooq (US 20140073134 A1) in view of Lin (US 20170011988 A1) and further in view of Nakamura (US 20160268163 A1).
Re: Claim 11 (Currently amended), Farooq discloses all the limitations of claim 1 on which this claim depends.
Farooq further discloses,
wherein applying the insulator to the etched back side of the wafer includes lining the etched back side of the substrate with the insulator (Farooq, Fig. 4B, liner 432 is deposited over the sidewalls of bottom via 430, may also be deposited over surface 412 and over the remote end 435 of bottom via 430, and liner 432 is conformal dielectric such as silicon oxide).
Farooq and Lin are silent regarding wherein a thickness of the insulator at a back side of the substrate is greater than the thickness of the insulator coating the inner surface of the cavity.
However, Nakamura teaches wherein a thickness at a back side of the substrate where the insulator is applied is greater than the thickness of the insulator at the etched portion of the substrate (Nakamura teaches in ¶¶ [0030]- [0032] that both the first insulating film 106 and 107 are thicker on the lower/back surface 105b of the substrate than on the inner surface of the via hole (VH)).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement Nakamura's thickness relationship to Farooq's liner deposition in order to reduced thermal stress and thus can be prevented from being warped (Nakamura, ¶ [0023]).
Re: Claim 13 (Currently amended), Farooq, Lin and Nakamura disclose all the limitations of claim 11 on which this claim depends. Farooq further teaches,
wherein applying the insulator to the etched back side of the wafer includes lining a portion of the layer but not the partial TSV plug (Farooq, Fig 4B/4C, insulator/liner 432 is deposited over the sidewalls of the bottom via 430, may also deposit over surface 412 and over the remote end 435 of bottom via 430, and anisotropic etch then removes liner 432, and if necessary liner 422, from via end 425, thereby exposing the back side of the partial TSV plug while the liner remains on the etched backside substrate/cavity surfaces).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BIPANA ADHIKARI DAWADI whose telephone number is (571)272-4149. The examiner can normally be reached Monday-Friday 11:30am-7:30pm.
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/BIPANA ADHIKARI DAWADI/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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