Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendments filed 11/5/2025 have been entered and considered. The amendments to claims 1, 8-9, and 15-20 are acknowledged.
The amendment to claim 15 overcomes the rejection under U.S.C. 112(b) and it has been withdrawn.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 3-4, and 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. US 20200411468 A1 (hereinafter referred to as Li), in view of Lin et al. US 20220361326 A1 (hereinafter referred to as Lin), in view of Kim US 20190206783 A1 (hereinafter referred to as Kim).
Regarding claim 1, Li teaches
An electronic device (“chip package structure 300” para. 0078 FIG. 2), comprising:
a redistribution layer (layer comprising “insulating layer 118”, “conductive pads 167”, and “insulating layer 230”, para. 0075 FIG. 2) comprising:
a first seed layer (“seed layer 162” para. 0049);
a first conductive layer (“conductive layer 166” para. 0052) disposed on the first seed layer;
a first insulating layer (“insulating layer 230”) disposed on the first conductive layer (“insulating layer 230” is formed over “conductive layer 166” of the “conductive pads 167”, para. 0075 FIG. 2) and having a first opening exposing at least a portion of the first conductive layer (the opening exposes portion “conductive layer 166” where “conductive bump 180” is formed, para. 0076 FIG. 2); and
another conductive bump (“conductive via structures 112” para. 0015), wherein the first seed layer is disposed between the first conductive layer and the another conductive bump (“seed layer 162” is formed over “conductive via structures 112” and ““conductive layer 166” is formed over “seed layer 162”, para. 0049 and 0052);
an electronic unit (“substrate 210” para. 0029) electrically connected to the redistribution layer (“substrate 210” is connected to the redistribution layer through “solder balls 190a” on the “conductive bumps 180”, para. 0068 FIG. 2); and
a conductive bump (“conductive bump 180”) disposed between the electronic unit and the first conductive layer and correspondingly disposed in the first opening (“conductive bump 180” is formed in the opening of “insulating layer 230”), wherein the electronic unit is electrically connected to the redistribution layer via the conductive bump (“substrate 210” is connected to the redistribution layer through “solder balls 190a” on the “conductive bumps 180”),
wherein the conductive bump is directly in contact with the first conductive layer (“conductive bump 180” is formed on “conductive layer 166” of “conductive pad 167”, para. 0060),
wherein the first conductive layer is electrically connected to the another conductive bump via the first seed layer (“conductive layer 166”, “seed layer 162” and “conductive via structures 112” are in electrical contact),
wherein in a cross-sectional view of the electronic device, the first conductive layer has an upper surface and a side surface (“conductive pad 167” has a surface in contact with part of “conductive bump 180” and a side surface).
However, Li fails to teach the conductive bump overlaps with the another conductive bump in a normal direction of the electronic device, the first conductive layer has a curved edge, and curved edge connects the upper surface and the side surface.
Nevertheless, alternate embodiment on FIG. 4A-4B in Lin teaches a “conductive bump 180” that appears wider than that of the embodiment in FIG. 2, such that it overlaps with “conductive via structures 112” (para. 0093). Alternatively, Lin US 20220361326 A1 teaches an “interconnection layer 14” connecting the “interconnection layer 10r” on one side with the “conductive pad 15” on the other side (para. 0014-0015 FIG. 1). The “conductive pad 15”, analogous to the “conductive bump 180” in Li, and the “interconnection layer 10r”, analogous to the “conductive via structures 112” in Li, vertically overlap even with an increase in the line width and line spacing (para. 0013 and 0015). It can be seen in the embodiment of FIG. 4A-4B in Lin and in Li that the existence and amount overlap between conductive bumps on opposite sides of the conductive layer depends on the widths of the bumps and the spacing or pitch of the bumps on each side. A smaller difference in pitches and larger bumps can result in an increased overlap between bumps on both sides. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the “conductive via structures 112” and “conductive bumps 180” may overlap depending on the pitch and the width of the “conductive bumps 180” suitable for the intended application.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the electronic device in Li with the teachings in an alternate embodiment in Li and with Lin. Overlap between the conductive bump and the another conductive bump may occur depending on the desired characteristics of the conductive bump and the another conductive bump. A smaller difference in spacing between adjacent conductive bumps and adjacent conductive bumps and larger bumps will result in greater overlap.
However, Li, modified by Lin, fails to teach the first conductive layer has a curved edge, and curved edge connects the upper surface and the side surface.
Nevertheless, Kim teaches a plurality “wiring patterns 142a, 142b, and 142c” having “rounded structure C” between a top surface and side surface of each wiring pattern (para. 0117 FIG. 13). Because of the “rounded structure C”, “the insulating material may be effectively introduced into the spaces between the wiring patterns 142a, 142b, and 142c” (para. 0117), such that “the problem of voids generated between the patterns of the fine pitch and the lowering of reliability due to the voids may be reduced” (para. 0064). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the edges of “conductive pad 167” can be curved like “rounded structure C” so that “insulating layer 230” can be more easily surround all the exposed surfaces of “conductive pad 167” and reduce the formation of voids.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the electronic device taught between Li and Lin with curved edge of the conductive layer as taught in Kim. The first insulating layer can be more reliably formed over the first conductive layer if the first conductive layer has a curved edge that connects the upper surface and the side surface.
Regarding claim 3, Li, modified by Lin and Kim, teaches the electronic device of claim 1, wherein the first conductive layer has a first thickness, the conductive bump has a second thickness, and the second thickness is greater than or equal to the first thickness. (“conductive bump 180 is thicker than the conductive pad 167”, and therefore thicker than “conductive layer 166”, para. 0061).
Regarding claim 4, Li, modified by Lin and Kim, teaches the electronic device of claim 1, wherein an upper surface of the conductive bump is higher than the first insulating layer of the redistribution layer (upper surface of “conductive bump 180” extends past upper surface of “insulating layer 230” as seen in FIG. 2)
Regarding claim 11, Li, modified by Lin and Kim, teaches the electronic device of claim 1, wherein the conductive bump has a same material as the first conductive layer (“conductive layer 166 is made of a metal material such as copper, aluminum, nickel, tungsten, titanium” and “conductive bumps 180 are made of a conductive material such as copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), or nickel (Ni)”, para. 0053 and 0063, so the materials can be the same).
Regarding claim 12, Li, modified by Lin and Kim, teaches the electronic device of claim 1, wherein the first conductive layer is a conductive layer closest to the electronic unit in the redistribution layer (“conductive layer 166” is the closest layer of the redistribution layer to the “substrate 210”).
Regarding claim 13, Li, modified by Lin and Kim, teaches the electronic device of claim 1, wherein the conductive bump is not overlapped with a side surface of the electronic unit in a normal direction of the electronic device (side surfaces of “substrate 210” are at widths that do not overlap with the “conductive bump 180” as seen in FIG. 2).
Regarding claim 14, Li, modified by Lin and Kim, teaches the electronic device of claim 1, further comprising: a conductive member disposed on the conductive bump (“solder balls 190a” are disposed on “conductive bumps 180”, para. 0064-0066) and electrically connected to a pad (“conductive pad 218” para. 0073 FIG. 1H) of the electronic unit and the conductive bump (“solder balls 190a” are bonded to “conductive pads 218” as seen in FIG. 1H-2).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Li, modified by Lin and Kim, as applied to claim 1, in view of Chen et al. US 20210057363 A1 (hereinafter referred to as Chen)
Li, modified by Lin and Kim, teaches the electronic device of claim 4, wherein the conductive bump has a thickness (“conductive bump 180” has a thickness), there is a distance between the upper surface of the conductive bump and an upper surface of the first insulating layer (“insulating layer 230” surrounds sides of but does not cover “conductive bump 180”, such that a portion of a side surface of “conductive bump 180” is exposed, para. 0076 FIG. 2).
However, Li, modified by Lin and Kim, fails to teach a ratio of the distance to the thickness is greater than 0 and less than or equal to 0.3.
Nevertheless, Chen teaches a “third redistribution layer 813” having a 5µm thickness (para. 0061 FIG. 28, “fourth redistribution passivation layer 815” with a 8 µm thickness (para. 0062), and a “underbump metallization 819” with .7-10µm thickness (para. 0065). The “underbump metallization 819” is formed on the top surface of “third redistribution layer 813” and its thickness is understood to be measured from the top surface of “third redistribution layer 813”. The “fourth redistribution passivation layer 815” and “third redistribution layer 813” are formed on a top surface of “third redistribution passivation layer 811” (para. 0061-0062). As such, a distance from top of “third redistribution layer 813” to top of “fourth redistribution passivation layer 815” is around -2.3 to 7µm. Negative values are understood to mean the “underbump metallization 819” is below a top surface of “fourth redistribution passivation layer 815”. The condition for a ratio between the distance to the thickness is satisfied when the “underbump metallization 819” has a thickness between 3-6.43µm. For thicknesses greater than 3µm, the “underbump metallization 819” protrudes past the top surface of “fourth redistribution passivation layer 815”. The examiner understands that the amount of protrusion of “underbump metallization 819” and the thickness of “third external connectors 817” will help determine the final standoff distance between the package shown in FIG. 28 and a structure bonded to the “third external connectors 817”. The examiner further understands that the standoff distance affects the overall package size, parasitic effects between circuitry of the bonded devices, and heat dissipation. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the thickness of “underbump metallization 819” determines how much it protrudes from the “fourth redistribution passivation layer 815”. The amount of protrusion, the distance, helps set the standoff distance when bonded to another device.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the electronic device taught between Li, Lin, and Kim with the conductive bump and first insulation layer thicknesses taught in Chen. The distance between the top surface of the conductive bump and the first insulation layer can be set based on a desired standoff distance to a subsequently bonded device.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Li, modified by Lin and Kim, as applied to claim 1 above, in view of Baek et al. US 20190139921 A1 (hereinafter referred to as Baek).
Li, modified by Lin and Kim, teaches the electronic device of claim 1 but fails to teach wherein the first insulating layer has a recess near the conductive bump.
Nevertheless, Baek teaches
wherein the first insulating layer (“photosensitive film 640” para. 0089 FIG. 7) is partially in contact with a side surface of the conductive bump (“bump 630” para. 0089) higher than the first insulating layer near the conductive bump, or the first insulating layer has a recess near the conductive bump (“first region 641” surrounds “bump 630” and has a lower height than “second region 642”, para. 0093 FIG. 7).
Li, modified by Lin and Kim, and Baek teach electronic devices having a bump formed in an opening that exposes a conductor. The different embodiments in Baek, including the one shown in FIG. 7, feature first regions of a photosensitive resin in contact and around the bump that have a reduced height compared to the region further away from the bump. The formation of the stepped profile achieves removal of residues between the bump and the photosensitive film, improving device reliability (para. 0004, 0055). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the formation of the step portion, the reduction of height of “first region 641”, removes harmful residue lingering between the “bump 630” and the “photosensitive film 640”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the electronic device taught between Li, Lin, and Kim with the recess in the insulating layer as taught in Baek. Residue between the conductive bump and the first insulating layer can be removed by forming the recess around the bump.
Claims 1, 4, and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al US 20220361326 A1 (hereinafter referred to as Lin), in view of Kim et al. US 20220310496 A1 (hereinafter referred to as Kim’96), in view of Kim US 20190206783 A1 (hereinafter referred to as Kim).
Regarding claim 1¸ Lin teaches
An electronic device (“semiconductor package device 1” para. 0011 FIG. 1), comprising:
a redistribution layer (“interconnection layer 14” with “seed layer 14s” para. 0015) comprising:
a first seed layer (“seed layer 14s” para. 0015);
a first conductive layer (“interconnection layer 14” comprising “first portion 14t”and “second portion 14v”, para. 0015) disposed on the first seed layer;
a first insulating layer (“dielectric layer 11” para. 0014) disposed on the first conductive layer (“dielectric layer 11” is formed on “interconnection layer 14”, para. 0015) and having a first opening exposing at least a portion of the first conductive layer (opening in “dielectric layer 11” corresponding to where “seed layer 15s” and “conductive vias 15v” are formed, para. 0016 FIG. 1); and
another conductive bump (“interconnection layer 10r” Lin para. 0013 FIG. 1), wherein the first seed layer is disposed between the first conductive layer and the another conductive bump (“seed layer 14s” lies between “interconnection layer 10r” and “interconnection layer 14”, para. 0015 FIG. 1),
an electronic unit (“electronic component 16” para. 0019 FIG. 1) electrically connected to the redistribution layer (“electronic component 16 is disposed on the protective layer 12 and electrically connected to the first surface 10r1 of the interconnection layer 10r” para. 0019);
and a conductive bump (“conductive pads 15” with “conductive vias 215v” and “seed layer 215s” para. 0016) correspondingly disposed in the first opening.
wherein the conductive bump is directly in contact with the first conductive layer (“seed layer 15s” contacts “interconnection layer 14”),
wherein the first conductive layer is electrically connected to the another conductive bump via the first seed layer (“second portion 14v of the interconnection layer 14 electrically connects to the second surface 10r2 of the interconnection layer 10r” Lin para. 0015), and the conductive bump overlaps with the another conductive bump in a normal direction of the electronic device (“interconnection layer 10r” vertically overlaps “conductive pads 15”),
wherein in a cross-sectional view of the electronic device, the first conductive layer has an upper surface and a side surface (“interconnection layer 14” has a substantially horizontal surface in contact with “conductive pad 15” and a substantially vertical side surface).
However, Lin fails to teach the conductive bump disposed between the electronic unit and the first conductive layer, wherein the electronic unit is electrically connected to the redistribution layer via the conductive bump, a curved edge, and curved edge connects the upper surface and the side surface.
Nevertheless, Kim’96 teaches
an electronic unit (“semiconductor chip 200” para. 0024 FIG. 1) electrically connected to the redistribution layer (electrically connected to “redistribution substrate 100” through “redistribution pad 140”, para. 0024);
the conductive bump (“redistribution pad 140”) disposed between the electronic unit and the first conductive layer (“second redistribution pattern 120” para. 0024), wherein the electronic unit is electrically connected to the redistribution layer via the conductive bump (“semiconductor chip 200” is electrically connected to “redistribution substrate 100” through “redistribution pad 140”).
Lin and Kim’96 teach packages of an electronic unit connected to a redistribution layer. Both teach redistribution layers where each layer has a seed and a conductive layer disposed on the seed. While Lin teaches an “electronic component 16” connected to pads below the first seed layer, Kim teaches a “semiconductor chip 200” connected to “redistribution pads 140” formed after the rest of “redistribution substrate 100”. In other words, Lin and Kim teach electronic units formed on opposing sides of the redistribution layer. “Conductive pads 15” in Lin are exposed through openings to allow for electrical connections (Lin para. 0017). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that electronic units can be disposed on either or each side of the redistribution layer for integration with the electronic package.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the electronic device taught in Lin with the electronic unit taught in Kim’96. The conductive bump in Lin is configured for electrical connection and an electronic unit can be connected to the conductive bump to be integrated into the electronic device.
However, Lin, modified by Kim’96, fails to teach a curved edge, and curved edge connects the upper surface and the side surface.
Nevertheless, Kim teaches a plurality “wiring patterns 142a, 142b, and 142c” having “rounded structure C” between a top surface and side surface of each wiring pattern (para. 0117 FIG. 13). Because of the “rounded structure C”, “the insulating material may be effectively introduced into the spaces between the wiring patterns 142a, 142b, and 142c” (para. 0117), such that “the problem of voids generated between the patterns of the fine pitch and the lowering of reliability due to the voids may be reduced” (para. 0064). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the edges of “conductive pad 167” can be curved like “rounded structure C” so that “insulating layer 230” can be more easily surround all the exposed surfaces of “conductive pad 167” and reduce the formation of voids.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the electronic device taught between Lin and Kim’96 with curved edge of the conductive layer as taught in Kim. The first insulating layer can be more reliably formed over the first conductive layer if the first conductive layer has a curved edge that connects the upper surface and the side surface.
Regarding claim 4, Lin, modified by Kim’96 and Kim, teaches the electronic device of claim 1, wherein an upper surface of the conductive bump is higher than the first insulating layer of the redistribution layer (the surface of “conductive pad 15” facing away from “interconnection layer 14” is further spaced from the top surface of “interconnection layer 14” than “dielectric layer 11”. When FIG. 1 is turned around as shown below, the surface of “conductive pad 15” furthest from “interconnection layer 14” can be considered the upper surface.).
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Regarding claim 9, Lin, modified by Kim’96 and Kim, teaches the electronic device of claim 1, wherein the redistribution layer further comprises: a second insulating layer (“dielectric layer 10” Lin para. 0012) disposed on the other conductive bump and having a second opening (opening where “interconnection layer 10r” is disposed), wherein the second opening exposes a portion of the other conductive bump (surface of “interconnection layer 10r” is exposed through the opening), and the first seed layer is disposed on an upper surface of the second insulating layer and in the second opening (as seen in the turned FIG. 1 above, a lower surface of “seed layer 14s” is part of the upper surface of the opening in “dielectric layer 10”).
Regarding claim 10, Lin, modified by Kim’96 and Kim, teaches the electronic device of claim 9, wherein the second opening of the second insulating layer is overlapped with the first opening of the first insulating layer in a normal direction of the electronic device (the opening in “dielectric layer 11” where “seed layer 15s” is disposed at least partially overlaps with the opening in “dielectric layer 10” where “interconnection layer 10r” is disposed, as seen in annotated FIG. 1 below).
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Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lin, in view of Higashiguchi US 6316735 B1 (hereinafter referred to as Higashiguchi).
Lin teaches the electronic device of claim 1 but fails to teach wherein the other conductive bump comprises a first conductive bump and a second conductive bump, the first conductive bump is closer to an edge of the electronic unit than the second conductive bump, and a width of the first conductive bump is greater than a width of the second conductive bump.
Nevertheless, Higashiguchi teaches
wherein the other conductive bump comprises a first conductive bump (“connection reinforcing pad 13a” col 5 lines 64-65 FIG. 1-3) and a second conductive bump (“connecting pad 12” col 5 line 64), the first conductive bump is closer to an edge of the electronic unit than the second conductive bump (“connection reinforcing pad 13a” is disposed on a corner of the matrix of pads, col 6 lines 19-20 FIG. 1), and a width of the first conductive bump is greater than a width of the second conductive bump (“Each of the connection reinforcing pads 13a-13d is constituted of a solder bump having a diameter larger than that of the connecting pads 12, such as, for example, a diameter of 0.6-1.0 mm” col 6 lines 6-9, while “connecting pads 12 is constituted of a solder bump having a diameter of 0.5 mm and a thickness of 30-40 .mu.m”, col 5 lines 65-67).
Lin, modified by Kim’96 and Kim, and Higashiguchi teach electronic units with conductive bumps for external connections. Higashiguchi teaches the “connection reinforcing pads 13a-13d” at corners of the matrix of pads so that alignment of the “connecting pads 12” onto “wiring patterns 25” of “PCB 3” is more reliable. Even with some misalignment, the reflow of the solder bump on “connection reinforcing pads 13a-13d” will position “connecting pads 12” on opposing “wiring pattern 25” and then the reflow of the solder bumps on “connecting pads 12” will further correct the alignment (col 7 lines 27-50). Furthermore, having the “connection reinforcing pads 13a013d” at the corners protects the “connecting pads 12” from damage due to bending (col 7 lines 58-67 and col 8 lines 1-2). “Connection pads 12” are analogous to the “interconnection layer 10r” in Lin and the examiner understands that the addition of bumps like “connection reinforcing pads 13a-13d” can improve the reliability of the connection with “electronic component 16” and therefore improve the resilience of the electronic device against warping or bending. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that having the larger pads at the edges of the substrate can help protect the pads in the center against damage from physical effects.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the electronic device taught in Lin with the other conductive bump sizes taught in Higashiguchi. Wider first conductive bumps at the edge of the electronic unit can better withstand bending and deformation so that the connections between second conductive pads and another device are more reliable.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC MULERO FLORES whose telephone number is (571)270-0070. The examiner can normally be reached Mon-Fri 8am-5pm (typically).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC MANUEL MULERO FLORES/Examiner, Art Unit 2898 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899