Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on November 11, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Species I and Species A, claims 1-11, 13, 15-20 in the reply filed on May 14, 2025 is acknowledged.
Claims 12 and 14-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on May 14, 2025.
The Examiner notes that claims 1-11, 13, and 17-20 are examined and claims 12, 14-16 are withdrawn.
Priority
Acknowledgment is made of applicant’s claim for foreign priority to Korean Application No. KR10-2022-0062708 under 35 U.S.C. 119 (a)-(d).
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed September 25, 2025. Claims 1, 13, and 20 are amended. Claims 12 and 14-16 remain withdrawn. The Examiner notes that claims 1-11, 13, and 17-20 are examined.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 3-8 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2021/0143800 A1) in view of Reboh (US 2019/0157422 A1) as evidenced by Braunstein (Phys. Rev., 1958).
With respect to claim 1, Lee teaches in Fig. 12A-12B:
A semiconductor device, comprising:
a substrate (substrate 110);
an active pattern (active pattern 105) that extends in a first horizontal direction (X) on the substrate (110);
a first nanosheet (bottommost semiconductor pattern 124, which may be nanosheet per para. 114) that is spaced apart from the active pattern in a vertical direction (Z) (124 and 105 are not in direct contact, see Fig. 12B),
a second nanosheet (middle semiconductor pattern 124) disposed on the first nanosheet (bottom semiconductor pattern 124) spaced apart from the first nanosheet in the vertical direction (separated by 330, see Fig. 12B);
and a gate electrode (gate electrode 320) that extends in a second horizontal direction (Y) on the active pattern (105) and surrounds the first nanosheet and the second nanosheet (Fig. 12),
wherein the second horizontal direction (Y) is different from the first horizontal direction (X).
Lee fails to teach:
and (the first nanosheet) comprises a plurality of layers,
wherein the plurality of layers comprises:
a first layer,
a second layer disposed on the first layer and in contact with the first layer,
and a third layer disposed on the second layer and in contact with the second layer,
wherein the first layer and the third layer include a first material,
and wherein the second layer includes a second material that is different from the first material;
and wherein the second material has a higher energy gap than the first material.
Reboh teaches in Fig. 11:
and [the first nanosheet] comprises a plurality of layers (channel layer 17, channel layer 18, and second part 302 of nanolayer 300),
wherein the plurality of layers comprises:
a first layer (17),
a second layer (302) disposed on the first layer and in contact with the first layer,
and a third layer (18) disposed on the second layer and in contact with the second layer,
wherein the first layer and the third layer include a first material (17 and 18 are formed from 200 and 400 which are made from SiGe per para. 28),
and wherein the second layer includes a second material that is different from the first material (302 is formed form 300 which is made from Si per para. 28);
Reboh does not mention the energy gap of the first or second material, but teaches that the first material is silicon and the second material is silicon-germanium.
and wherein the second material has a higher energy gap than the first material.
However, the Examiner notes that it is known that pure silicon is known in the art to have a higher energy gap than SiGe at all nonzero concentrations of Ge. Evidence is recited in Fig. 17 of Braunstein, which shows that the highest energy gap is for 100% Si and the energy gap decreases monotonically as Ge is alloyed into Si.
Lee discloses the claimed invention except for the nanosheets being made up of three layers of materials, which include a first material with a lower energy gap than the second material. Reboh teaches that it is known to make nanosheets from three layers that comprise a first material having a smaller energy gap than the second material. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Lee as taught by Reboh, since Reboh states in para. 4-5 that this would compressively stress the channel which is beneficial for pMOS transistors. See MPEP 2144.
With respect to claim 3, Lee further teaches:
wherein each sidewall in the second horizontal direction of the plurality of layers is aligned in the vertical direction to remaining sidewalls in the second horizontal direction of the plurality of layers (see Fig. 12B of Lee, each of the sidewalls of the semiconductor structure 124 on the right side are aligned in the Z direction)
With respect to claim 4, Lee/Reboh further teaches:
further comprising:
a gate insulation layer (gate insulation pattern 330 of Lee) disposed between the gate electrode (320 of Lee) and each sidewall (sidewalls of 124 of Lee modified to include the plurality of layers of Reboh) in the second horizontal direction (Y) of the plurality of layers.
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Lee in view of Reboh as explained above.
With respect to claim 5, Lee/Reboh further teaches:
further comprising:
an interface layer (interface pattern 290 of Lee) disposed between the gate insulation layer (330 of Lee) and the sidewalls (sidewalls of 124 of Lee modified to include the plurality of layers of Reboh) in the second horizontal direction (Y) of the plurality of layers,
and that is in contact with the sidewalls in the second horizontal direction of the plurality of layers (290 is in contact with sidewalls of 124, see Fig. 12B of Lee).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Lee in view of Reboh as explained above.
With respect to claim 6, Reboh further teaches:
wherein a second thickness of the second layer (para. 39 “the third nanowire has a thickness, measured in a stacking direction of the first to fifth nanowires, comprised between 2 nm and 15 nm”) in the vertical direction is different from a first thickness of the first layer (17) in the vertical direction (see Fig. 11 and 14, 302 is thicker than 17).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Lee in view of Reboh as explained above.
With respect to claim 7, Reboh further teaches:
wherein the second thickness of the second layer in the vertical direction (para. 39 “the third nanowire has a thickness, measured in a stacking direction of the first to fifth nanowires, comprised between 2 nm and 15 nm” the lower end of the range is smaller than the thickness of the channels) is less than the first thickness of the first layer in the vertical direction (para. 109, the thickness of the 17 and 18 is at least 3 nm).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to choose a thickness in the taught range of 2nm to 15 nm that is smaller than the 3 nm of the first layer with routine experiment and optimization. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990).
With respect to claim 8, Reboh further teaches:
wherein the second thickness (thickness of 302, which may be 2-15 nm per. Para. 39) of the second layer in the vertical direction is greater than the first thickness of the first layer in the vertical direction (thickness of 17) (see Fig. 11 and 14, 302 is thicker than 17).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Lee in view of Reboh as explained above.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2021/0143800 A1) and Reboh (US 2019/0157422 A1) as evidenced by Braunstein (Phys. Rev., 1958) as applied to claims 1 and further in view of Wahab (Applied Physics Letters, 1994).
With respect to claim 2, Lee/Reboh teaches all limitations of claim 1 upon which claim 2 depends. Lee/Reboh further teaches:
wherein the first material contains silicon (Si) (SiGe contains silicon)
Lee/Reboh fails to teach:
and the second material contains silicon carbide (SiC).
Wahab teaches that epitaxially growing 3C-SiC films on Si induces a homogenous strain on Si films (pg. 726 “The corresponding strain contributed to the Si substrate peak broadening discussed above. XTEM showed that no voids were present in the Si substrate, contrary to typical CVD-grown films.” This can be due to the relatively limited carbonization stage and the low deposition temperature which limited the diffusion of Si from the substrate. The absence of voids and dislocations in the Si contributed to the homogeneous strain state in the film as observed by XRD.”) The purpose of the multilayer nanosheet as taught by Reboh is to impart a compressive strain on the channel layers. Wahab further teaches that 3C-SiC is a wide band gap semiconductor, therefore substituting Si for the first material and SiC for the second material meets the limitation of the second material having a higher energy gap than the first material. It would be obvious to use the strained Si on SiC heterostructure taught by Wahab in the device of Lee/Reboh to meet the limitation:
and the second material contains silicon carbide (SiC).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to substitute the strained channels made from SiGe/Si heterostructures with strained channels in which SiC imparts strain on a Si channel. The ordinary artisan would have been motivated to look to analogous art teaching(s) of alternative suitable or useful material such as SiC as taught by Wahab, as the selection of a known material based on its suitability for intended purpose deemed obvious and Si is a known channel material, a compressive strain is known to improve a channel material, and SiC is known to cause a compressive strain on Si. See MPEP 2144.07.
Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2021/0143800 A1) and Reboh (US 2019/0157422 A1) as evidenced by Braunstein (Phys. Rev., 1958) as applied to claims 1 and 6 above and further in view of Lin-2019 (IEEE Transactions on Nanotechnology, 2019).
With respect to claim 9, Lee/Reboh teaches all limitations of claim 1 upon which claim 9 depends. Lee/Reboh fails to teach:
wherein a third thickness of the third layer in the vertical direction is different from a first thickness of the first layer in the vertical direction.
With respect to claim 9, Lin-2019 teaches:
wherein a third thickness (thickness of bottom channel NS height NSb, which is 15 nm, or top channel NS height NSt, which is 30 nm, whichever is different from the layer and thickness assigned first layer and first thickness, see table associated with Fig. 8 of Lin) of the third layer in the vertical direction is different from a first thickness (thickness of bottom channel NS height NSb, which is 15 nm, or top channel NS heigh NSt, which is 30 nm, see table associated with Fig. 8 of Lin) of the first layer in the vertical direction.
It would have been obvious to one to one of ordinary skill in the art at the time of the invention to modify the device of Lee/Reboh with the teachings of Lin-2019 such that individual nanolayer channels of a given nanosheet have different thicknesses. All the claimed elements in Lee, Reboh, and Lin-2019 were known in the prior art and one skilled in the art could have combined the device of Lee/Reboh with the relative dimensions of the channels of Lin-2019 with no change in their respective functions, and the combination would have yielded the predictable result of nanosheets with two channel layers that act as a channel of a gate all around transistor to one of ordinary skill in the art at the time of the invention. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
With respect to claim 10, Lin-2019 teaches:
wherein the third thickness (thickness of top channel, 30 nm) of the third layer in the vertical direction is greater than the first thickness (thickness of bottom channel, 15 nm) of the first layer in the vertical direction.
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Lee in view of Reboh and Lin-2019 as explained above.
With respect to claim 11, Lin-2019 teaches:
wherein the third thickness (thickness of bottom channel, 15 nm) of the third layer in the vertical direction is less than the first thickness (thickness of top channel, 30 nm) of the first layer in the vertical direction.
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Lee in view of Reboh and Lin-2019 as explained above.
Claims 13, 17-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2021/0143800 A1) in view of Reboh (US 2019/0157422 A1) and Wahab (Applied Physics Letters, 1994).
With respect to claim 13, Lee teaches:
a substrate (substrate 110);
an active pattern (active pattern 105) which extends in a first horizontal direction (X) on the substrate (110);
a first nanosheet (bottommost semiconductor pattern 124, which may be nanosheet per para. 114) that is spaced apart from the active pattern in a vertical direction (124 and 105 are not in direct contact, see Fig. 12B),
and a gate electrode (gate electrode 320) that extends in a second horizontal direction (Y) on the active pattern (105) and surrounds the first nanosheet (Fig. 12),
wherein the second horizontal direction (Y) is different from the first horizontal direction (X).
and a source/drain region (source/drain layer 250) disposed on at least one side (along both sides in the X direction) of the gate electrode (gate electrode 320) in the first horizontal direction (X), and in contact with each sidewall in the first horizontal direction of the nanosheet (in contact with the sidewalls of 124).
Lee fails to teach:
and comprises a plurality of layers,
wherein the plurality of layers comprises:
a first layer having a first material containing silicon (Si),
a second layer having a second material containing silicon carbide disposed on the first layer and in contact with the first layer
and a third layer disposed on the second layer and in contact with the second layer and containing silicon (Si);
in contact with each sidewall in the first horizontal direction of the plurality of layers.
wherein the second material has a higher energy gap than the first material.
Reboh teaches in Fig. 11:
and [the first nanosheet] comprises a plurality of layers (channel layer 17, channel layer 18, and second part 302 of nanolayer 300),
wherein the plurality of layers comprises:
a first layer having a first material containing silicon (17, which is made of SiGe which contains Si),
a second layer (302) having a second material disposed on the first layer and in contact with the first layer,
and a third layer (18) disposed on the second layer and in contact with the second layer,
wherein the first layer and the third layer include a first material (17 and 18 are formed from 200 and 400 which are made from SiGe per para. 28),
and wherein the second layer includes a second material that is different from the first material (302 is formed form 300 which is made from Si per para. 28);
a source/drain region disposed on at least one side of the gate electrode in the first horizontal direction, and in contact with each sidewall in the first horizontal direction of the plurality of layers (source and drain electrodes 11 and 12 are in contact with the sidewalls of 17, 18, and 302),
Lee discloses the claimed invention except for the nanosheets being made up of three layers of materials, which include a first material with a lower energy gap than the second material. Reboh teaches that it is known to make nanosheets from three layers that comprise a first material having a smaller energy gap than the second material. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Lee as taught by Reboh, since Reboh states in para. 4-5 that this would compressively stress the channel which is beneficial for pMOS transistors. See MPEP 2144.
Wahab teaches that epitaxially growing 3C-SiC films on Si induces a homogenous strain on Si films (pg. 726 “The corresponding strain contributed to the Si substrate peak broadening discussed above. XTEM showed that no voids were present in the Si substrate, contrary to typical CVD-grown films.” This can be due to the relatively limited carbonization stage and the low deposition temperature which limited the diffusion of Si from the substrate. The absence of voids and dislocations in the Si contributed to the homogeneous strain state in the film as observed by XRD.”) The purpose of the multilayer nanosheet as taught by Reboh is to impart a compressive strain on the channel layers. Wahab further teaches that 3C-SiC is a wide band gap semiconductor, therefore substituting Si for the first material and SiC for the second material meets the limitation of the second material having a higher energy gap than the first material. It would be obvious to use the strained Si on SiC heterostructure taught by Wahab in the device of Lee/Reboh to meet the limitation:
a second layer having a second material containing silicon carbide (SiC)
wherein the second material has a higher energy gap than the first material.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to substitute the strained channels made from SiGe/Si heterostructures with strained channels in which SiC imparts strain on a Si channel. The ordinary artisan would have been motivated to look to analogous art teaching(s) of alternative suitable or useful material such as SiC as taught by Wahab, as the selection of a known material based on its suitability for intended purpose deemed obvious and Si is a known channel material, a compressive strain is known to improve a channel material, and SiC is known to cause a compressive strain on Si. See MPEP 2144.07.
With respect to claim 17, Lee further teaches:
a second nanosheet (middle semiconductor pattern 124) disposed on the first nanosheet (bottom semiconductor pattern 124),
spaced apart from the first nanosheet in the vertical direction (separated by 330, see Fig. 12B),
and surrounded by the gate electrode (gate electrode 320).
With respect to claim 18, Reboh further teaches:
wherein a second thickness of the second layer (para. 39 “the third nanowire has a thickness, measured in a stacking direction of the first to fifth nanowires, comprised between 2 nm and 15 nm”) in the vertical direction is different from a first thickness of the first layer (17) in the vertical direction (see Fig. 11 and 14, 302 is thicker than 17).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Lee in view of Reboh as explained above.
With respect to claim 20, Lee teaches:
a substrate (substrate 110);
an active pattern (active pattern 105) that extends in a first horizontal direction (X) on the substrate (110);
a plurality of nanosheets (semiconductor pattern 124, which may be nanosheet per para. 114) that are stacked and spaced apart from the active pattern in a vertical direction (Z) (124 and 105 are not in direct contact, see Fig. 12B),
and a gate electrode (gate electrode 320) that extends in a second horizontal direction (Y) on the active pattern (105) and surrounds the plurality of nanosheets (124) (Fig. 12),
the second horizontal direction (Y) being different from the first horizontal direction (X).
a source/drain region (source/drain layer 250) disposed on at least one side (along both sides in the X direction) of the gate electrode (gate electrode 320) in the first horizontal direction (X)
a gate insulation layer (gate insulation pattern 330) disposed between the plurality of nanosheets (124) the gate electrode (320)
and an interface layer (interface pattern 290) disposed between the plurality of nanosheets (124) and the gate insulation layer (330),
a first sidewall in the first horizontal direction (X) of each of the plurality of nanosheets (124) is in contact with the source/drain region (250) (see Fig. 12A),
a second sidewall in the second horizontal (Y) direction of each of the plurality of nanosheets (124) is in contact with the interface layer (290) (see Fig. 12B),
Lee fails to teach:
wherein each of the plurality of nanosheets comprises a plurality of layers,
wherein the plurality of layers comprises a first layer having a first material containing silicon (Si),
a second layer having a second material containing silicon carbide (SiC) disposed on the first layer and in contact with the first layer,
and a third layer disposed on the second layer and in contact with the second layer and containing silicon (Si),
wherein a first sidewall in the first horizontal direction of each of the plurality of layers is in contact with the source/drain region,
wherein a second sidewall in the second horizontal direction of each of the plurality of layers is in contact with the interface layer,
wherein a second thickness of the second layer in the vertical direction is less than a first thickness of the first layer in the vertical direction, and the second thickness of the second layer in the vertical direction is less than a third thickness of the third layer in the vertical direction.
Reboh teaches in Figs. 11 and 14:
(a nanosheet that) comprises a plurality of layers (channels 17 and 18 and second part 302),
wherein the plurality of layers comprises:
a first layer having a first material containing silicon (Si) (17, which comprises SiGe which contains Si),
a second layer having a second material containing disposed on the first layer and in contact with the first layer (302, which differs from the claim in that it comprises Si, not SiC),
and a third layer (18) disposed on the second layer (302) and in contact with the second layer and containing silicon (SI) (18 is made from SiGe, which contains Si),
a second thickness of the second layer (para. 39 “the third nanowire has a thickness, measured in a stacking direction of the first to fifth nanowires, comprised between 2 nm and 15 nm” the lower end of the range is smaller than the thickness of the channels) in the vertical direction is less than a first thickness of the first layer in the vertical direction (para. 109, the thickness of the 17 and 18 is at least 3 nm), and the second thickness of the second layer (2-15 nm) in the vertical direction is less than a third thickness of the third layer (at least 3 nm) in the vertical direction.
a first sidewall in the first horizontal direction of each of the plurality of layers is in contact with the source/drain region (sidewalls of 17, 18, and 302 are in contact with source and drain 11 and 12, see Fig. 11),
Lee modified by Reboh to include nanosheets made of multiple layers teaches:
a second sidewall in the second horizontal direction of each of the plurality of layers is in contact with the interface layer (see Fig. 14, sidewalls of 17, 18, and 302 are in contact with interface layer gate insulator 20 in the Y direction. Lee includes an interface layer between the gate insulator and the nanosheet.),
Lee discloses the claimed invention except for the nanosheets being made up of three layers of materials, which include a first material with a lower energy gap than the second material. Reboh teaches that it is known to make nanosheets from three layers that comprise a first material having a smaller energy gap than the second material. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Lee as taught by Reboh, since Reboh states in para. 4-5 that this would compressively stress the channel which is beneficial for pMOS transistors. See MPEP 2144.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to choose a thickness in the taught range of 2nm to 15 nm that is smaller than the 3 nm of the first layer with routine experiment and optimization. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990).
Wahab teaches that epitaxially growing 3C-SiC films on Si induces a homogenous strain on Si films (pg. 726 “The corresponding strain contributed to the Si substrate peak broadening discussed above. XTEM showed that no voids were present in the Si substrate, contrary to typical CVD-grown films.” This can be due to the relatively limited carbonization stage and the low deposition temperature which limited the diffusion of Si from the substrate. The absence of voids and dislocations in the Si contributed to the homogeneous strain state in the film as observed by XRD.”) The purpose of the multilayer nanosheet as taught by Reboh is to impart a compressive strain on the channel layers. Wahab further teaches that 3C-SiC is a wide band gap semiconductor, therefore substituting Si for the first material and SiC for the second material meets the limitation of the second material having a higher energy gap than the first material. It would be obvious to use the strained Si on SiC heterostructure taught by Wahab in the device of Lee/Reboh to meet the limitation:
a second layer having a second material containing silicon carbide (SiC)
wherein the second material has a higher energy gap than the first material.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to substitute the strained channels made from SiGe/Si heterostructures with strained channels in which SiC imparts strain on a Si channel. The ordinary artisan would have been motivated to look to analogous art teaching(s) of alternative suitable or useful material such as SiC as taught by Wahab, as the selection of a known material based on its suitability for intended purpose deemed obvious and Si is a known channel material, a compressive strain is known to improve a channel material, and SiC is known to cause a compressive strain on Si. See MPEP 2144.07.
Claims 19 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2021/0143800 A1), Reboh (US 2019/0157422 A1), and Wahab (Applied Physics Letters, 1994) as applied to claims 13 above and further in view of Lin-2019 (IEEE Transactions on Nanotechnology, 2019).
With respect to claim 19, Lee/Reboh/Wahab teaches all limitations of claim 1 upon which claim 9 depends. Lee/Reboh/Wahab fails to teach:
wherein a third thickness of the third layer in the vertical direction is different from a first thickness of the first layer in the vertical direction.
Lin-2019 teaches:
wherein a third thickness (thickness of bottom channel NS height NSb, which is 15 nm, or top channel NS height NSt, which is 30 nm, whichever is different from the layer and thickness assigned first layer and first thickness, see table associated with Fig. 8 of Lin) of the third layer in the vertical direction is different from a first thickness (thickness of bottom channel NS height NSb, which is 15 nm, or top channel NS heigh NSt, which is 30 nm, see table associated with Fig. 8 of Lin) of the first layer in the vertical direction.
It would have been obvious to one to one of ordinary skill in the art at the time of the invention to modify the device of Lee/Reboh/Wahab with the teachings of Lin-2019 such that individual nanolayer channels of a given nanosheet have different thicknesses. All the claimed elements in Lee, Reboh, Wahab and Lin-2019 were known in the prior art and one skilled in the art could have combined the device of Lee/Reboh/Wahab with the relative dimensions of the channels of Lin-2019 with no change in their respective functions, and the combination would have yielded the predictable result of nanosheets with two channel layers that act as a channel of a gate all around transistor to one of ordinary skill in the art at the time of the invention. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Response to Arguments
Applicant’s arguments with respect to claims 1-11, 13, and 17-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON MICHAEL WEGNER whose telephone number is (571)270-7647. The examiner can normally be reached Mon-Fri 8:30 AM - 5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/A.M.W./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897