Prosecution Insights
Last updated: April 19, 2026
Application No. 18/076,808

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE

Final Rejection §102§103
Filed
Dec 07, 2022
Examiner
REIDA, MOLLY KAY
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SK Hynix Inc.
OA Round
4 (Final)
84%
Grant Probability
Favorable
5-6
OA Rounds
2y 3m
To Grant
86%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allow Rate
348 granted / 417 resolved
+15.5% vs TC avg
Minimal +2% lift
Without
With
+2.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
31 currently pending
Career history
448
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
46.3%
+6.3% vs TC avg
§102
34.4%
-5.6% vs TC avg
§112
16.0%
-24.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 417 resolved cases

Office Action

§102 §103
DETAILED ACTION Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-3, 11, 12, 22, and 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US Pub. 2015/0008499). Regarding independent claim 1, Lee teaches a semiconductor device (Figs. 1, 2A, 2B; para. 0045+), comprising: a source structure (102) disposed over a base (100) (Fig. 2A, 2B; para. 0052-0053); an etch prevention layer (162) disposed over the source structure (Fig. 2A, 2B; para.0068); bit lines (BL) disposed over the etch prevention layer (Fig. 1); a stack structure located between the etch prevention layer and the bit lines and including conductive layers (152, 154, 156) and insulating layers (172), that are alternately stacked (Fig. 2A; para. 0053, 0071); and a source contact structure (182) extending into the stack structure in a vertical direction and coupled to the source structure (Fig. 2A, para. 0072), wherein the source contact structure includes polysilicon (para. 0072), wherein a bottom level of the etch prevention layer and a bottom level of the source contact structure are substantially aligned at the same level (Fig. 2B), and wherein a thickness of the etch prevention layer is less than a thickness of at least one of the insulating layers (Fig. 2A – thickness of etch prevention layer (162) is less than the thickness of at least the bottommost 172). Re claims 2 and 3, Lee teaches wherein the polysilicon includes a dopant (para. 0072) of one of an N-type and a P-type. (please note the “one of an n- type and p-type” includes the entire universe of possibilities; thus, Lee is considered to meet the claim). Re claim 11, Lee teaches a slit passing through the stack structure and the etch prevention layer, wherein the source contact structure is disposed in the slit (Figs. 2A, 2B – where the slit is the hole that 182/184 are within). Re claim 12, Lee teaches a spacer (184) filling the slit and surrounding a sidewall of the source contact structure (Figs. 2A, 2B; para. 0072). Re claim 22, Lee teaches wherein the source structure is disposed below the bottom level of the etch prevention layer (Fig. 2B). Re claim 23, Lee teaches wherein the source structure does not protrude toward the stack structure beyond the bottom level of the etch prevention layer (Fig. 2B). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 4-6, 9, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US Pub. 2015/0008499) in view of Kim et al. (US Pub. 2017/0309635). Re claim 4, Lee is silent with respect to a source contact pad disposed over the source contact structure. Kim teaches a similar device (Fig. 5) including a source contact pad (152) over the source contact structure (para. 0038). It would have been obvious to one of ordinary skill at the time of filing to include the source contact pads as taught by Kim within the device of Lee for the purpose of providing a connection site to the source contact structure. Re claim 5, Lee in view of Kim teaches wherein the source contact pad includes a polysilicon layer including a dopant (para. 0038) of one of an N-type and a P-type. (please note the “one of an n- type and p-type” includes the entire universe of possibilities; thus, the combination of Lee and Kim is considered to meet the claim). Re claim 6, The combination of Lee and Kim does not explicitly disclose wherein the source contact structure and the source contact pad include a same dopant; however, it would have been obvious to one of ordinary skill in the art at the time of filing to have the source contact structure and the source contact pad to include the same dopant for the purpose of providing an operational device. That is, having the source contact structure and the source contact pad doped with the same dopant would allow proper operation of the device while the alternative would create a diode which would make the device inoperable. Re claims 9 and 10, Lee is silent with respect to a barrier layer. Lee in view of Kim teaches a barrier layer surrounding a sidewall of the source contact structure wherein the barrier layer is a Ti/TiN layer (para. 0040). It would have been obvious to one of ordinary skill in the art at the time of filing to include a Ti/TiN barrier layer as taught be Kim for the purpose of preventing diffusion between the metal layer and the polysilicon layer. Claim(s) 15 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US Pub. 2015/0008499) in view of Lee et al. (US Pub. 2012/0119283) (Lee2). Re claim 15, Lee teaches wherein the etch prevention layer includes silicon oxide (para. 0069), but is silent with respect other materials. Lee2 teaches the use of silicon carbonitride (SICN) as a material for an etch stop layer (Fig. 5E; para. 0126). It would have been obvious to one of ordinary skill in the art at the time of filing to use silicon carbonitride (SICN) as the etch stop material within the device of Lee for the purpose of providing the desired etch selectivity. Furthermore, it considered obvious to select a known material based on its suitability for an intended purpose (MPEP 2144.07). Allowable Subject Matter Claims 7, 8, 13, and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: there is no teaching, suggestion, or motivation from the prior art of record, nor does the prior art of record otherwise make obvious the limitations of… Re claims 7 and 8, …wherein the source structure includes a polysilicon layer… Re claims 13 and 14, …the channel structure extending into the source structure… …in combination with the other limitations. Response to Arguments Applicant’s arguments with respect to claim(s) 1-15, 22, and 23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOLLY KAY REIDA whose telephone number is (571)272-4237. The examiner can normally be reached M-F 8:30-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571)272-4237. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOLLY K REIDA/Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Dec 07, 2022
Application Filed
Feb 21, 2025
Non-Final Rejection — §102, §103
May 27, 2025
Response Filed
Jul 03, 2025
Final Rejection — §102, §103
Oct 10, 2025
Request for Continued Examination
Oct 16, 2025
Response after Non-Final Action
Oct 28, 2025
Non-Final Rejection — §102, §103
Jan 30, 2026
Response Filed
Feb 25, 2026
Final Rejection — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
84%
Grant Probability
86%
With Interview (+2.4%)
2y 3m
Median Time to Grant
High
PTA Risk
Based on 417 resolved cases by this examiner. Grant probability derived from career allow rate.

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