DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 14 is objected to because of the following informalities: “the least square circuit”. Other instances of this claim element is referred to as the “least square solver circuit”, whereas claim 14 is the only instance of this different recitation. For purposes of clarity and consistency of the claims, Examiner suggest amending “the least square circuit” of claim 14 to be recited as “the least square solver circuit”.
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-15 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding claim 1, under the Alice Framework Step 1 analysis, the claims falls within the four statutory categories of patentable subject matter: an apparatus.
Under the Alice Framework Step 2A Prong 1 analysis, claim 1 recites Mathematical Concepts. The claim recites Mathematical Calculations, which is specifically identified as an exemplar in the Mathematical Concepts grouping of abstract ideas:
“An electronic device for accelerating a canonical polyadic decomposition (CP decomposition), adaptable for updating a plurality of components of a tensor, wherein the plurality of components comprise a first factor matrix corresponding to a first dimension and a second factor matrix corresponding to a second dimension, wherein the electronic device comprises:
a mix engine circuit, which performs at least one of a Walsh-Hadamard transform (WHT) operation and a discrete cosine transform (DCT) operation on the first factor matrix, the second factor matrix, and the tensor, respectively, to update the first factor matrix, the second factor matrix, and the tensor;
a processor, which is coupled to the mix engine circuit, wherein the processor samples the updated first factor matrix and the updated second factor matrix to generate a first sampled matrix, and samples an unfolded matrix of the updated tensor to generate a second sampled matrix, wherein the unfolded matrix corresponds to a third dimension; and
a least square solver circuit, which is coupled to the processor, wherein the least square solver circuit solves a least square problem corresponding to the first sampled matrix and the second sampled matrix to generate or update a third factor matrix of the tensor, thereby updating the plurality of components, wherein
the processor outputs the plurality of components after the updating of the plurality of components is completed.”
See specification ([0030]) describing the canonical polyadic decomposition. See specification ([0045], [0049]) describing performing the Walsh-Hadamard transform and discrete cosine transform. See specification ([0041], [0054], [0056-0058]) describing sampling. See specification ([0041], [0054], [0058]) describing solving the least square problem. For these reasons, the claim recites Mathematical Concepts.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: “a mix engine circuit”, ”a processor, which is coupled to the mix engine circuit”, “a least square solver circuit, which is coupled to the processor”, and “the processor outputs the plurality of components after the updating of the plurality of components is completed”. The mix engine circuit, processor, least square solver circuit are recited at a high level of generality, and are examples of generic computing components, and/or merely generally linked to a particular technological environment (see MPEP 2106.05(h)(vi): Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment). Further, they are recited at a high-level of generality such that it amounts to no more than mere instructions using a generic computer component, or merely as tools to implement the abstract idea by merely reciting the words “apply it” (or an equivalent) with the judicial exception (see MPEP2106.05(f): Mere Instructions to Apply an Exception). The "processor outputs the plurality of components after the updating of the plurality of components is completed" limitation is an example of insignificant extra-solution activity, mere data gathering (see MPEP 2106.05(g): Insignificant Extra-Solution Activity). Taken alone or in combination, the additional elements fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 analysis, the claims recites limitations described above as recited at a high level of generality merely results in “apply it” on a computer (or an equivalent) with the judicial exception. The limitations described above as an insignificant extra-solution activity are also well-understood, routine, or conventional (see MPEP 2106.05(d)(II): ii. Performing repetitive calculations and iv. Storing and retrieving information in memory). Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 1 is ineligible.
Claims 2, 7, 10-13 merely further limit the mathematical concepts and recite additional elements previously discussed above.
Regarding claim 3, under the Alice Framework Step 2A Prong 1 analysis, the claim recites Mathematical Concepts. The claim recites Mathematical Calculations, which is specifically identified as an exemplar in the Mathematical Concepts grouping of abstract ideas:
“wherein the mix engine circuit obtains a column vector from the first factor matrix, and performs the WHT operation on the column vector in response to a length of the column vector being a product of a power of two and a positive integer.”
See specification ([0050], [0065]) describing performing the WHT operation. For these reasons, the claim recites Mathematical Concepts.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: “the mix engine circuit obtains a column vector from the first factor matrix”. The limitation is an example of insignificant extra-solution activity, mere data gathering (see MPEP 2106.05(g): Insignificant Extra-Solution Activity). Taken alone or in combination, the additional elements fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 analysis, the limitations described above as an insignificant extra-solution activity are also well-understood, routine, or conventional (see MPEP 2106.05(d)(II): iv. Storing and retrieving information in memory). Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 3 is ineligible.
Regarding claim 4, under the Alice Framework Step 2A Prong 1 analysis, the claim recites Mathematical Concepts. The claim recites Mathematical Calculations, which is specifically identified as an exemplar in the Mathematical Concepts grouping of abstract ideas:
“wherein in response to the positive integer greater than one, the mix engine circuit performs the DCT operation on the column vector after performing the WHT operation on the column vector.”
See specification ([0050-0051], [0064-0065]) describing performing the DCT operation. For these reasons, the claim recites Mathematical Concepts.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: “in response to, the mix engine circuit” performs. The limitation is an example of insignificant extra-solution activity, mere data gathering (see MPEP 2106.05(g): Insignificant Extra-Solution Activity). Further, it amounts to no more than mere instructions using a generic computer component, or merely as tools to implement the abstract idea by merely reciting the words “apply it” (or an equivalent) with the judicial exception (see MPEP2106.05(f): Mere Instructions to Apply an Exception). Taken alone or in combination, the additional elements fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 analysis, the limitations described above as an insignificant extra-solution activity are also well-understood, routine, or conventional (see MPEP 2106.05(d)(II): ii. Performing repetitive calculations). Further, using generic computer components merely as a tool to perform the existing process does not integrate the judicial exception into a practical application or provide significantly more. Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 4 is ineligible.
Regarding claim 5, under the Alice Framework Step 2A Prong 1 analysis, the claim recites Mathematical Concepts. The claim recites Mathematical Calculations, which is specifically identified as an exemplar in the Mathematical Concepts grouping of abstract ideas:
“wherein the mix engine circuit obtains a column vector from the first factor matrix, and performs the DCT operation on the column vector in response to a length of the column vector not being a product of a power of two and a positive integer.”
See specification ([0052], [0064]) describing performing the DCT operation. For these reasons, the claim recites Mathematical Concepts.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: “the mix engine circuit obtains a column vector from the first factor matrix”. The limitation is an example of insignificant extra-solution activity, mere data gathering (see MPEP 2106.05(g): Insignificant Extra-Solution Activity). Taken alone or in combination, the additional elements fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 analysis, the limitations described above as an insignificant extra-solution activity are also well-understood, routine, or conventional (see MPEP 2106.05(d)(II): iv. Storing and retrieving information in memory). Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 5 is ineligible.
Regarding claim 6, under the Alice Framework Step 2A Prong 1 analysis, the claim recites Mathematical Concepts. The claim recites Mathematical Calculations, which is specifically identified as an exemplar in the Mathematical Concepts grouping of abstract ideas:
“wherein the mix engine circuit obtains a sub-vector whose length is equal to the power of two from the column vector, and performs the WHT operation on the sub-vector.”
See specification ([0050]) describing performing the WHT operation. For these reasons, the claim recites Mathematical Concepts.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: “the mix engine circuit obtains a sub-vector”. The limitation is an example of insignificant extra-solution activity, mere data gathering (see MPEP 2106.05(g): Insignificant Extra-Solution Activity). Taken alone or in combination, the additional elements fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 analysis, the limitations described above as an insignificant extra-solution activity are also well-understood, routine, or conventional (see MPEP 2106.05(d)(II): iv. Storing and retrieving information in memory). Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 6 is ineligible.
Under the Alice Framework Step 2A Prong 1 analysis, claim 8 recites Mathematical Concepts. The claims recites Mathematical Calculations, which is specifically identified as an exemplar in the Mathematical Concepts grouping of abstract ideas:
“an index sampler, which generates a random index collection, wherein the random index collection comprises a first random index corresponding to the first dimension and a second random index corresponding to the second dimension, wherein
the processor obtains a first vector from the updated first factor matrix according
to the first random index, and obtains a second vector from the updated second factor matrix according to the second random index, wherein
the processor calculates a matrixed tensor times Khatri-Rao product of the first vector and the second vector to generate the first sampled matrix.”
See specification ([0055]) describing generating a random index collection. See specification ([0056]) describing calculating a matrixed tensor. For these reasons, the claim recites Mathematical Concepts.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: “an index sampler” and ”the processor obtains a first vector from the updated first factor matrix according to the first random index, and obtains a second vector from the updated second factor matrix according to the second random index”. The index sampler and processor are recited at a high level of generality, and are examples of generic computing components, and/or merely generally linked to a particular technological environment (see MPEP 2106.05(h)(vi): Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment). Further, they are recited at a high-level of generality such that it amounts to no more than mere instructions using a generic computer component, or merely as tools to implement the abstract idea by merely reciting the words “apply it” (or an equivalent) with the judicial exception (see MPEP2106.05(f): Mere Instructions to Apply an Exception). The "processor obtains a first vector from the updated first factor matrix according to the first random index, and obtains a second vector from the updated second factor matrix according to the second random index" limitation is an example of insignificant extra-solution activity, mere data gathering (see MPEP 2106.05(g): Insignificant Extra-Solution Activity). Taken alone or in combination, the additional elements fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 analysis, the claims recites limitations described above as recited at a high level of generality merely results in “apply it” on a computer (or an equivalent) with the judicial exception. The limitations described above as an insignificant extra-solution activity are also well-understood, routine, or conventional (see MPEP 2106.05(d)(II): iv. Storing and retrieving information in memory). Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 8 is ineligible.
Regarding claim 9, under the Alice Framework Step 2A Prong 1 analysis, the claim recites Mathematical Concepts. The claim recites Mathematical Calculations, which is specifically identified as an exemplar in the Mathematical Concepts grouping of abstract ideas:
“wherein the processor obtains a third vector from the unfolded matrix according to the first random index and the second random index to generate the second sampled matrix.”
See specification ([0054], [0057]) describing the unfolded matrix. For these reasons, the claim recites Mathematical Concepts.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: “the processor obtains a third vector”. The limitation is an example of insignificant extra-solution activity, mere data gathering (see MPEP 2106.05(g): Insignificant Extra-Solution Activity). Taken alone or in combination, the additional elements fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 analysis, the limitations described above as an insignificant extra-solution activity are also well-understood, routine, or conventional (see MPEP 2106.05(d)(II): iv. Storing and retrieving information in memory). Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 9 is ineligible.
Regarding claim 14, under the Alice Framework Step 2A Prong 1 analysis, the claim recites Mathematical Concepts. The claim recites Mathematical Calculations, which is specifically identified as an exemplar in the Mathematical Concepts grouping of abstract ideas:
“a normalizer circuit, which is coupled to the least square circuit, and after solving
the least square problem, performs normalization on the third factor matrix, wherein the normalization comprises:
calculating a norm of a vector of the third factor matrix;
calculating a reciprocal of the norm; and
calculating a product of the reciprocal and the vector.”
See specification ([0059]) describing the normalization process. For these reasons, the claim recites Mathematical Concepts.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: “the normalizer circuit which is coupled to the least square circuit”. The normalizer circuit is recited at a high level of generality, and is an example of generic computing components, and/or merely generally linked to a particular technological environment (see MPEP 2106.05(h)(vi): Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment). Further, it is recited at a high-level of generality such that it amounts to no more than mere instructions using a generic computer component, or merely as tools to implement the abstract idea by merely reciting the words “apply it” (or an equivalent) with the judicial exception (see MPEP2106.05(f): Mere Instructions to Apply an Exception). Taken alone or in combination, the additional elements fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 analysis, the claims recites limitations described above as recited at a high level of generality merely results in “apply it” on a computer (or an equivalent) with the judicial exception. Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 14 is ineligible.
Claim 15 is directed to a method that would be practiced by the apparatus of claim 1. The claim 1 analysis similarly applies to claim 15, and is similarly rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9, 13, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Wei-Pei Huang, Ray C. C. Cheung, and Hong Yan. 2021. An Efficient Parallel Processor for Dense Tensor Computation. IEEE Trans. Very Large Scale Integr. Syst. 29, 7 (July 2021), 1335–1347. https://doi.org/10.1109/TVLSI.2021.3080318 (hereinafter “Huang”, as cited in the Information Disclosure Statement filed on 12/07/2022) in view of Casey Battaglino et al., “A Practical Randomized CP Tensor Decomposition”, SIAM Journal on Matrix Analysis and Applications, January 01, 2018, pp. 1-26 (hereinafter “Battaglino”, as cited in the Information Disclosure Statement filed on 12/07/2022).
Regarding claim 1, Huang discloses an electronic device (p. 1337, co. 2 sec. III-A, fig. 1) for accelerating a canonical polyadic decomposition (CP decomposition) (p. 1336, co. 2, “6) Typical Tensor Decomposition Methods”), adaptable for updating a plurality of components (p. 1337, Algorithm 1:
A
,
B
,
C
) of a tensor (p. 1337, Algorithm 1:
X
), wherein the plurality of components comprise a first factor matrix corresponding to a first dimension (p. 1336, co. 2 sec. III-A,
A
; p. 1337 ⁋1
A
; p. 1335, co. 1 sec. I ⁋2 I, J, K dimension sizes; p. 1339, fig. 2
A
) and a second factor matrix corresponding to a second dimension (p. 1336, co. 2 sec. III-A,
B
; p. 1337 ⁋1
B
; p. 1335, co. 1 sec. I ⁋2 I, J, K dimension sizes; p. 1339, fig. 2
B
), wherein the electronic device comprises:
a mix engine circuit (p. 1337, fig. 1 “HADAMARD PRODUCT”), which performs at least one of a Walsh-Hadamard transform (WHT) operation and a discrete cosine transform (DCT) operation on the first factor matrix, the second factor matrix, and the tensor (p. 1342 “H. HP”), respectively, to update the first factor matrix (p. 1337, Algorithm 1:
C
T
C
*
B
T
B
), the second factor matrix (p. 1337, Algorithm 1:
C
T
C
*
A
T
A
), and the tensor (p. 1340 co. 2 “F. TTMc Operations” mode-1
X
'
and
X
'
'
);
a processor (p. 1337, fig. 1 “TTMc”; p. 1337, sec. III FPGA-based parallel processor architecture), which is coupled to the mix engine circuit (p. 1337, fig. 1 “HADAMARD PRODUCT”), wherein the processor samples the updated first factor matrix and the updated second factor matrix to generate a first sampled matrix (p. 1337 Algorithm 1:
B
⨀
A
), and samples an unfolded matrix (p. 1336 sec. II-B “2) Tensor Matricization”
X
(
n
)
) of the updated tensor to generate a second sampled matrix (p. 1337 Algorithm 1:
X
(
3
)
B
⨀
A
), wherein the unfolded matrix corresponds to a third dimension (p. 1336 sec. II-B “1) Tensor Fibers”, “2) Tensor Matricization”, “3) Tensor Times Matrix (TTM)” mode-n, and when n=3 is mode-3 thus
X
(
i
,
j
,
:
)
and mode-3); and
a least square solver circuit (p. 1337, fig. 1 “PE array”), which is coupled to the processor (p. 1337, fig. 1 “TTMc”; p. 1337, sec. III FPGA-based parallel processor architecture), wherein the least square solver circuit solves a least square problem corresponding to the first sampled matrix and the second sampled matrix to generate or update a third factor matrix of the tensor (p. 1337 Algorithm 1:
C
), thereby updating the plurality of components (p. 1337, Algorithm 1:
A
,
B
,
C
), wherein
the processor outputs the plurality of components (p. 1342 “I. Matrix Inversion” output) after the updating of the plurality of components is completed (p. 1337 Algorithm 1: line 8).
Although Huang generally discloses performing Hadamard operations they appear to be silent to explicitly disclosing these operations as Walsh-Hadamard (WHT) and also silent with disclosing a discrete cosine transform (DCT) operation.
Battaglino discloses the Walsh-Hadamard (WHT) operation and the discrete cosine transform (DCT) operation (p. 5 ⁋1).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Huang’s electronic device to further comprise WHT and DCT operations as disclosed by Battaglino’s features because they are in the claimed invention’s same field of endeavor of tensor decomposition architecture (p. 1 Abstract). Modifying with Battaglino’s WHT and DCT operations would have been obvious to one of ordinary skill in the art as doing so would yield significant improvements by avoiding explicit matrix multiplications (p. 5 ⁋1). Using Battaglino’s WHT and DCT operations to provide a predictable result in Huang’s device before the effective filing date would have been obvious since one of ordinary skill in the art would recognize that Huang’s device was ready for improvement to incorporate these efficient algorithms as doing so would be beneficial by avoiding unnecessary operation executions in the device.
Regarding claim 2, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Huang in view of Battaglino discloses the electronic device wherein Huang discloses:
before performing the at least one of the WHT operation and the DCT operation on the first factor matrix (p. 1337 Algorithm 1: line 3), the mix engine circuit (p. 1337, fig. 1 “HADAMARD PRODUCT”) randomly performs a sign inversion on a first row vector of the first factor matrix (p. 1336, co. 2 sec. III-A,
A
; p. 1337 ⁋1
A
; p. 1335, co. 1 sec. I ⁋2 I, J, K dimension sizes; p. 1339, fig. 2
A
).
Although Huang generally discloses Hadamard operations, they appear to be silent with disclosing the Walsh-H transform operation and the DCT operation and randomly performing a sign inversion on a first row vector.
Battaglino discloses the Walsh-H transform operation and the DCT operation (p. 5 ⁋1) and randomly performing a sign inversion on a first row vector (p. 5 ⁋2).
In addition to the motivation to combine stated for claim 1, Battaglino discloses sign-flipping as part of the steps of FJLT. Further modifying with Battaglino’s sign inversion operation would have been obvious to one of ordinary skill in the art as doing so would yield significant improvements by spreading out the frequency domain of the signal which aids in sparse matrix computations (p. 5 ⁋2). Using Battaglino’s sign inversion operation to provide a predictable result in Huang’s device before the effective filing date would have been obvious since one of ordinary skill in the art would recognize that Huang’s device was ready for improvement to incorporate the sign flipping as doing so would be beneficial by distributing data in a more efficient manner for computations.
Regarding claim 3, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Huang in view of Battaglino discloses the electronic device wherein Huang discloses:
the mix engine circuit (p. 1337, fig. 1 “HADAMARD PRODUCT”) obtains a column vector (p. 1340 co. 1-2 columns of
A
, co. 1 ⁋7
A
=
[
A
1
;
A
2
;
…
;
A
N
p
e
y
]
) from the first factor matrix (p. 1336, co. 2 sec. III-A,
A
; p. 1337 ⁋1
A
; p. 1335, co. 1 sec. I ⁋2 I, J, K dimension sizes; p. 1339, fig. 2
A
), and performs the WHT operation on the column vector in response to a length of the column vector being a product of a power of two and a positive integer (p. 1340 co. 1-2 restriction of
I
and
J
, co. 2 ⁋3-7 in the cases when the length does equal a product of a power of two and a positive integer).
Although Huang generally discloses performing Hadamard operations they appear to be silent to explicitly disclosing these operations as Walsh-Hadamard (WHT) operation.
Battaglino discloses the Walsh-Hadamard (WHT) operation (p. 5 ⁋1).
The motivation to combine provided with respect to claim 1 similarly applies.
Regarding claim 4, the teachings addressed in the claim 3 analysis and rejection are incorporated, and Huang in view of Battaglino discloses the electronic device wherein Huang discloses:
in response to the positive integer greater than one (p. 1340 co. 1-2 restriction of
I
and
J
, co. 2 ⁋3-7 in the cases when the length does equal at least a positive integer greater than one), the mix engine circuit (p. 1337, fig. 1 “HADAMARD PRODUCT”) performs the DCT operation on the column vector after performing the WHT operation on the column vector (p. 1340 co. 1-2 columns of
A
, co. 1 ⁋7
A
=
[
A
1
;
A
2
;
…
;
A
N
p
e
y
]
).
Although Huang generally discloses performing Hadamard operations they appear to be silent to explicitly disclosing these operations as Walsh-Hadamard (WHT) operation and also performing the DCT operation.
Battaglino discloses the Walsh-Hadamard (WHT) operation and DCT operation (p. 5 ⁋1).
The motivation to combine provided with respect to claim 1 similarly applies.
Regarding claim 5, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Huang in view of Battaglino discloses the electronic device wherein Huang discloses:
the mix engine circuit (p. 1337, fig. 1 “HADAMARD PRODUCT”) obtains a column vector (p. 1340 co. 1-2 columns of
A
, co. 1 ⁋7
A
=
[
A
1
;
A
2
;
…
;
A
N
p
e
y
]
) from the first factor matrix (p. 1336, co. 2 sec. III-A,
A
; p. 1337 ⁋1
A
; p. 1335, co. 1 sec. I ⁋2 I, J, K dimension sizes; p. 1339, fig. 2
A
), and performs the DCT operation on the column vector in response to a length of the column vector not being a product of a power of two and a positive integer (p. 1340 co. 1-2 restriction of
I
and
J
, co. 2 ⁋3-7 in the cases when the length does not equal a product of a power of two and a positive integer).
Huang appears to be silent with disclosing performing the DCT operation.
Battaglino discloses performing the DCT operation (p. 5 ⁋1).
The motivation to combine provided with respect to claim 1 similarly applies.
Regarding claim 6, the teachings addressed in the claim 3 analysis and rejection are incorporated, and Huang in view of Battaglino discloses the electronic device wherein Huang discloses:
the mix engine circuit (p. 1337, fig. 1 “HADAMARD PRODUCT”) obtains a sub-vector whose length is equal to the power of two (p. 1340 co. 2 ⁋7
X
(
1
)
) from the column vector (p. 1340 co. 1-2 columns of
A
, co. 1 ⁋7
A
=
[
A
1
;
A
2
;
…
;
A
N
p
e
y
]
), and performs the WHT operation on the sub-vector (p. 1340 co. 2 ⁋7
X
(
1
)
).
Although Huang generally discloses performing Hadamard operations they appear to be silent to explicitly disclosing these operations as Walsh-Hadamard (WHT) operation.
Battaglino discloses the Walsh-Hadamard (WHT) operation (p. 5 ⁋1).
The motivation to combine provided with respect to claim 1 similarly applies.
Regarding claim 7, the teachings addressed in the claim 4 analysis and rejection are incorporated, and Huang in view of Battaglino discloses the electronic device wherein Huang discloses:
the mix engine circuit (p. 1337, fig. 1 “HADAMARD PRODUCT”) performs the DCT operation on the column vector (p. 1340 co. 1-2 columns of
A
, co. 1 ⁋7
A
=
[
A
1
;
A
2
;
…
;
A
N
p
e
y
]
) according to an interval of the power of two (p. 1340 co. 1-2 restriction of
I
and
J
, co. 2 ⁋3-7 in the cases when the length does equal a power of two).
Huang appears to be silent with disclosing performing the DCT operation.
Battaglino discloses performing the DCT operation (p. 5 ⁋1).
The motivation to combine provided with respect to claim 1 similarly applies.
Regarding claim 8, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Huang in view of Battaglino discloses the electronic device further comprising as Huang discloses:
an index sampler (p. 1337 “Data fetch”; p. 1338 co. 2 “E. Tensor-Matrix and Matrix-Matrix Multiplication”), which generates a random index collection (p. 1339 co. 1 ⁋2 element
i
of
I
, element
j
of
J
), wherein the random index collection comprises a first random index corresponding to the first dimension (p. 1340 co. 1 ⁋1-2 element
i
of
I
) and
a second random index corresponding to the second dimension (p. 1340 co. 1 ⁋1-2 element
j
of
J
), wherein the processor (p. 1337, fig. 1 “TTMc”; p. 1337, sec. III FPGA-based parallel processor architecture) obtains a first vector from the updated first factor matrix according to the first random index (p. 1337 Algorithm 1: line 3
A
=
, where
X
(
1
)
is in mode-1; p. 1336 co. 1 sec. II-B “1) Tensor Fibers”; p. 1340 co. 1 element
i
of
I
; p. 1342 co. 1 ⁋1-2), and obtains a second vector from the updated second factor matrix according to the second random index (p. 1337 Algorithm 1: line 3
B
=
, where
X
(
2
)
is in mode-2; p. 1336 co. 1 sec. II-B “1) Tensor Fibers”; p. 1340 co. 1 element
j
of
J
; p. 1342 co. 1 ⁋1-2), wherein
the processor (p. 1337, fig. 1 “TTMc”; p. 1337, sec. III FPGA-based parallel processor architecture) calculates a matrixed tensor times Khatri-Rao product (p. 1341 co. 2 “G. MTTKRP”; p. 1342 co. 1 ⁋1-2) of the first vector and the second vector to generate the first sampled matrix (p. 1337 Algorithm 1:
B
⨀
A
).
Regarding claim 9, the teachings addressed in the claim 8 analysis and rejection are incorporated, and Huang in view of Battaglino discloses the electronic device wherein Huang discloses:
the processor (p. 1337, fig. 1 “TTMc”; p. 1337, sec. III FPGA-based parallel processor architecture) obtains a third vector from the unfolded matrix (p. 1336 sec. II-B “2) Tensor Matricization”
X
(
n
)
; p. 1337 Algorithm 1: line 7
X
(
3
)
) according to the first random index (p. 1337 Algorithm 1: line 3
A
=
, where
X
(
1
)
is in mode-1; p. 1340 co. 1 element
i
of
I
; p. 1342 co. 1 ⁋1-2) and the second random index (p. 1337 Algorithm 1: line 3
B
=
, where
X
(
2
)
is in mode-2; p. 1340 co. 1 element
j
of
J
; p. 1342 co. 1 ⁋1-2) to generate the second sampled matrix (p. 1337 Algorithm 1:
X
(
3
)
B
⨀
A
).
Regarding claim 13, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Huang in view of Battaglino discloses the electronic device wherein Huang discloses:
after solving the least square problem to generate or update the third factor matrix (p. 1337 Algorithm 1: lines 3-7), the mix engine circuit (p. 1337, fig. 1 “HADAMARD PRODUCT”), the processor (p. 1337, fig. 1 “TTMc”; p. 1337, sec. III FPGA-based parallel processor architecture), and the least square solver circuit (p. 1337, fig. 1 “PE array”) update the second factor matrix according to the third factor matrix and the first factor matrix (p. 1337 Algorithm 1: line 5 on subsequent iterations while convergence criterion is not met), thereby updating the plurality of components (p. 1337, Algorithm 1:
A
,
B
,
C
).
Claim 15 is directed to a method that would be performed by the apparatus of claim 1. The claim 1 analysis similarly applies, and claim 15 is similarly rejected.
Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Battaglino as applied to claim 1 above, and further in view of J. D. Bolaños-Jojoa, J. M. Espinosa-Duran and J. Velasco-Medina, "Efficient hardware design of Forward and Inverse Walsh-Hadamard transform," 2014 XIX Symposium on Image, Signal Processing and Artificial Vision, Armenia, Colombia, 2014, pp. 1-5, doi: 10.1109/STSIVA.2014.7010174. (hereinafter “Bolaños-Jojoa”) in view of Parhi, K.K. (1999) VLSI Digital Signal Processing Systems: Design and Implementation. Wiley, USA. (hereinafter “Parhi”).
Regarding claim 10, the teachings addressed in the claim 2 analysis and rejection are incorporated, and Huang in view of Battaglino discloses the electronic device wherein Huang discloses:
after solving the least square problem to generate or update the third factor matrix (p. 1337 Algorithm 1: lines 1-9), the mix engine circuit (p. 1337, fig. 1 “HADAMARD PRODUCT”) performs at least one of an inverse WHT operation and an inverse DCT operation on the first factor matrix (p. 1336, co. 2 sec. III-A,
A
; p. 1337 ⁋1
A
; p. 1335, co. 1 sec. I ⁋2 I, J, K dimension sizes; p. 1339, fig. 2
A
), thereby updating the plurality of components (p. 1337, Algorithm 1:
A
,
B
,
C
).
Although Huang generally discloses performing Hadamard operations they appear to be silent to explicitly disclosing these operations as performing at least one of an inverse WHT operation and an inverse DCT operation.
Battaglino appears to be silent with disclosing performing at least one of an inverse WHT operation and an inverse DCT operation. Further, Huang in view of Battaglino appears to be silent with disclosing performing at least one of an inverse WHT operation and an inverse DCT operation.
Bolaños-Jojoa discloses performing at least one of an inverse WHT operation (p. 3 co. 1 “B. Design of NxN-IWHT based on hard-wired transposition.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Huang in view of Battaglino’s electronic device to further comprise inverse WHT operations as disclosed by Bolaños-Jojoa’s features because they are in the claimed invention’s same field of endeavor of transformation architecture (Abstract). Modifying with Bolaños-Jojoa’s inverse WHT operation would have been obvious to one of ordinary skill in the art as doing so would yield significant improvements by implementing architecture with lower latency, and higher operation frequency and throughput (p. 1 sec. I ⁋3). Using Bolaños-Jojoa’s inverse WHT operations to provide a predictable result in Huang in view of Battaglino’s device before the effective filing date would have been obvious since one of ordinary skill in the art would recognize that Huang’s device was ready for improvement to incorporate the capability of performing the inverse of Battaglino’s WHT operation as doing so would be beneficial by lowering latency and increasing operation frequency and throughput in the device.
Bolaños-Jojoa appears to be silent with disclosing performing at least one of an inverse DCT operation. Further, the combination of Huang in view of Battaglino in view of Bolaños-Jojoa appears to be silent with disclosing performing at least one of an inverse DCT operation.
Parhi discloses performing at least one of an inverse DCT operation (p. 3 IDCT).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Huang in view of Battaglino in view of Bolaños-Jojoa’s electronic device to further comprise inverse DCT operations as disclosed by Parhi’s features because they are in the claimed invention’s same field of endeavor of transformation architecture (p. 3 ⁋1). Modifying with Parhi’s inverse DCT operation would have been obvious to one of ordinary skill in the art as doing so would yield significant improvements by implementing architecture that would reduce number of multiplications (p. 4 ⁋2-3). Using Parhi’s inverse DCT operations to provide a predictable result in Huang in view of Battaglino in view of Bolaños-Jojoa’s device before the effective filing date would have been obvious since one of ordinary skill in the art would recognize that Huang’s device was ready for improvement to incorporate the capability of performing the inverse of Battaglino’s DCT operation as doing so would be beneficial by reducing unnecessary multiplications in the device.
Regarding claim 11, the teachings addressed in the claim 10 analysis and rejection are incorporated, and Huang in view of Battaglino discloses the electronic device wherein Huang discloses:
after performing the at least one of the inverse WHT operation and the inverse DCT operation on the first factor matrix (p. 1336, co. 2 sec. III-A,
A
; p. 1337 ⁋1
A
; p. 1335, co. 1 sec. I ⁋2 I, J, K dimension sizes; p. 1339, fig. 2
A
), the mix engine circuit (p. 1337, fig. 1 “HADAMARD PRODUCT”) performs the sign inversion on the first row vector of the first factor matrix again (p. 1336, co. 2 sec. III-A,
A
; p. 1337 ⁋1
A
; p. 1335, co. 1 sec. I ⁋2 I, J, K dimension sizes; p. 1339, fig. 2
A
).
Although Huang generally discloses Hadamard operations, they appear to be silent with disclosing performing the at least one of the inverse WHT operation and the inverse DCT operation and randomly performing a sign inversion on a first row vector.
Battaglino discloses randomly performing a sign inversion on a first row vector (p. 5 ⁋2).
The motivation to combine provided with respect to claim 2 similarly applies.
Battaglino appears to be silent to disclosing performing the at least one of the inverse WHT operation and the inverse DCT operation. Further, Huang in view of Battaglino appears to be silent with disclosing performing the at least one of the inverse WHT operation and the inverse DCT operation.
Bolaños-Jojoa discloses performing at least one of an inverse WHT operation (p. 3 co. 1 “B. Design of NxN-IWHT based on hard-wired transposition.”).
The motivation to combine provided with respect to claim 10 similarly applies.
Bolaños-Jojoa appears to be silent with disclosing performing the inverse DCT operation. Further, the combination of Huang in view of Battaglino in view of Bolaños-Jojoa appears to be silent with disclosing performing the inverse DCT operation.
Parhi discloses performing the inverse DCT operation (p. 3 IDCT).
The motivation to combine provided with respect to claim 10 similarly applies.
Regarding claim 12, the teachings addressed in the claim 10 analysis and rejection are incorporated, and Huang in view of Battaglino discloses the electronic device wherein Huang discloses:
the mix engine circuit (p. 1337, fig. 1 “HADAMARD PRODUCT”) performs the at least one of the inverse WHT operation and the inverse DCT operation on the first factor matrix (p. 1336, co. 2 sec. III-A,
A
; p. 1337 ⁋1
A
; p. 1335, co. 1 sec. I ⁋2 I, J, K dimension sizes; p. 1339, fig. 2
A
) in response to the number of update iterations (p. 1337 Algorithm 1: lines 2, 9 amount of loops performed) of the plurality of components (p. 1337, Algorithm 1:
A
,
B
,
C
) reaching a threshold (p. 1337 Algorithm 1: lines 2, 9 convergence criterion met).
Although Huang generally discloses Hadamard operations, they appear to be silent with disclosing performing the at least one of the inverse WHT operation and the inverse DCT operation.
Battaglino appears to be silent to disclosing performing the at least one of the inverse WHT operation and the inverse DCT operation. Further, Huang in view of Battaglino appears to be silent with disclosing performing the at least one of the inverse WHT operation and the inverse DCT operation.
Bolaños-Jojoa discloses performing at least one of an inverse WHT operation (p. 3 co. 1 “B. Design of NxN-IWHT based on hard-wired transposition.”).
The motivation to combine provided with respect to claim 10 similarly applies.
Bolaños-Jojoa appears to be silent with disclosing performing the inverse DCT operation. Further, the combination of Huang in view of Battaglino in view of Bolaños-Jojoa appears to be silent with disclosing performing the inverse DCT operation.
Parhi discloses performing the inverse DCT operation (p. 3 IDCT).
The motivation to combine provided with respect to claim 10 similarly applies.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Battaglino as applied to claim 1 above, and further in view of N Benjamin Erichson, Krithika Manohar, Steven L Brunton and J Nathan Kutz. “Randomized CP tensor decomposition”. Published 27 May 2020 • © 2020 The Author(s). Published by IOP Publishing Ltd. Machine Learning: Science and Technology, Volume 1, Number 2. 2020 Mach. Learn.: Sci. Technol. 1 025012 (hereinafter “Erichson”).
Regarding claim 14, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Huang in view of Battaglino discloses the electronic device further comprising, as Huang discloses:
a normalizer circuit (p. 1337 fig. 1 “NORM”; p. 1343 “J. Norm Calculation and Normalization”), which is coupled to the least square circuit (p. 1337, fig. 1 “PE array”), and after solving the least square problem (p. 1337 Algorithm 1: lines 3-7), performs normalization on the third factor matrix (p. 1337 Algorithm 1: lines 8), wherein the normalization comprises:
calculating a norm of a vector (p. 1343 co. 1 “J. Norm Calculation and Normalization”; p. 1337 Algorithm 1: line 8 columns of
C
) of the third factor matrix (p. 1337 Algorithm 1:
C
);
calculating a reciprocal of the norm; and
calculating a product of the reciprocal and the vector (p. 1337 Algorithm 1: line 8 columns of
C
).
Although Huang generally discloses performing normalization, they appear to be silent to explicitly disclosing the exact mathematical process as claimed. Further, Battaglino is also silent with disclosing calculating a reciprocal of the norm, and calculating a product of the reciprocal.
Erichson discloses calculating a reciprocal of the norm (p. 8 Algorithm 2: line 9), and calculating a product of the reciprocal (p. 8 Algorithm 2: line 10).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Huang in view of Battaglino’s electronic device to further comprise further norm operations as disclosed by Erichson’s features because they are in the claimed invention’s same field of endeavor of decomposition architecture (Abstract). Modifying with Erichson’s further norm operations would have been obvious to one of ordinary skill in the art as doing so would yield significant improvements to the congruence of the calculations (p. 9 ⁋1). Using Erichson’s further norm operations to provide a predictable result in Huang in view of Battaglino’s device before the effective filing date would have been obvious since one of ordinary skill in the art would recognize that Huang’s device was ready for improvement to incorporate the capability of performing Erichson’s further norm operations as doing so would be beneficial to the correctness of the calculations via the level of congruence achieved.
Conclusion
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/MARKUS ANTHONY VILLANUEVA/Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
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