DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Applicant’s election without traverse of Group I claims 1-17 in the reply filed on 12/05/2025 is acknowledged. Claims 18-20 cancelled, claims 21-23 withdraw from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/05/2025.
Election/Restrictions
Newly submitted claims 21-23 (canceled process claims 18-20) are directed to an invention that is independent or distinct from the invention originally claimed for the following reasons: Case point, the device (claims 1-17) as claimed can be made via a method of manufacturing with differing temporal ordering.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 21-23 withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claims 1 and 17 objected to because of the following informalities:
Re claim 1 lines 9-10 recite “ a first pre-fabricated redistribution stack layer” should read “ a first prefabricated redistribution stack layer”
Re claim 17 lines 6-7 recite “ second prefabricated substrate and third prefabricated substrate” Should read “second prefabricated substrate and/or third prefabricated substrate”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 10, 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Jo et al (KR 20210073956 A) in view of Paek et al (US20170062372A1).
Re claim 1 Jo teaches a packaging structure (10, fig 4) [0065], comprising:
a lower package (100/370/300/400, fig 4) [0013] and an upper package (500/600, fig 4) [0013] disposed above the lower package, the lower package (100/370/300/400) and the upper package (500/600 being electrically connected (through 370);
wherein the lower package (100/370/300/400) comprises a prefabricated interconnected silicon core stack structure (100, fig 4) [0013] and a first plastic packaging layer (400, fig 4) [0039] surrounding the periphery of the prefabricated interconnected silicon core stack structure (100);
the prefabricated interconnected silicon core stack structure (100, fig 4) comprises a silicon interconnection layer (110, fig 4) [0017], and the silicon interconnection layer (110, fig 4) [0017] comprises a first surface (top of 110) and a second surface (bottom of 110) facing away from each other, a back-end redistribution stack layer (220, fig 4) and a first pre-fabricated redistribution stack layer (210, fig 4) [0029] are stacked sequentially on the first surface (top of 110) and in electrical connection (210 may be connected to the first connection pad 150 of 100);a passivation layer (130, fig 4) [0020] is disposed on the second surface (bottom of 110, fig 4);
the silicon interconnection layer (110) comprises a silicon substrate (middle of 110, fig 4) [0021] and a plurality of first prefabricated conductive pillars (140, fig 4) [0021] embedded in a plurality of through-silicon-vias (columnar shape) [0022] of the silicon substrate (middle of 110), each of the first prefabricated conductive pillar (140) comprises a first end (top of 140) and a second end (bottom of 140) opposite to each other, the first end (140) is exposed (through 150) from the first surface (top of 110), and
wherein the upper package (500/600, fig 4) [0026] is disposed above the first prefabricated redistribution stack layer (210, fig 4), and is electrically connected (through 300) to the first prefabricated redistribution stack layer (210).
Jo does not teach the second end is exposed from a side of the passivation layer and away from the second surface.
Paek teaches the second end (bottom end of 113, fig 3) is exposed from a side (left/right sides of 111, fig 3) of the passivation layer (111, fig 3) [0035] and away from the second surface (bottom of 110, fig 3)
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Paek into the structure of Jo to include the second end is exposed from a side of the passivation layer and away from the second surface as claimed.
The ordinary artisan would have been motivated to modify Jo based on the teaching of Paek in the above manner for the purpose of reducing parasitic crosstalk.
Re claim 2 Jo in view of Paek teaches, the packaging structure according to claim 1, further comprising a back-surface redistribution stack layer (800, fig 4) [Jo, 0075 ] disposed below the prefabricated interconnected silicon core stack structure (100):
wherein the back-surface redistribution stack layer (800) is disposed at a side of the passivation layer (130) away from the second surface (bottom surface of 110), and is electrically connected to the silicon interconnection layer (110) (800 may include 810 the third redistribution pattern may be configured to be connected to the first semiconductor chip pas 120) [Jo, 0076 ].
Re claim 4 Jo in view of Paek teaches the packaging structure according to claim 2, wherein the prefabricated interconnected silicon core stack structure (100, fig 4) further comprises a second prefabricated redistribution stack layer (440/430/380, fig 4) [Jo, 0105] that is disposed at a side (left side of 400) of the passivation layer (400) away from the second surface (bottom of 110) and is electrically connected (through 130)to the second end of each of the first prefabricated conductive pillars (bottom of 140) in the silicon interconnection layer (100).
Re claim 10 Jo teaches the packaging structure according to claim 1, further comprising a first redistribution stack layer (750, fig 4) [Jo, 0071] that is disposed between the upper package and the lower package and is electrically connected (through 80) to the upper package and the lower package (see fig 4)[Jo,0071].
Re claim 15 Jo in view of Paek teach the packaging structure according to claim 1,
Jo and Paek do not teach the lower package further comprises a first prefabricated substrate, the first prefabricated substrate comprises a third surface and a fourth surface facing away from each other, and the prefabricated interconnected silicon core stack structure is disposed on the third surface and/or the fourth surface and electrically connected to the first prefabricated substrate respectively,
wherein the prefabricated interconnected silicon core stack structure and the prefabricated substrate constitute a first prefabricated unit, and the first prefabricated unit is packaged by the first plastic packaging layer to form the lower package.
Jo different embodiment (fig 3) teaches the lower package (100/370/300/400, fig 4) further comprises a first prefabricated substrate (50, fig 4) [0047], the first prefabricated substrate (50, fig 4) [0047] comprises a third surface (top of 50) and a fourth surface (bottom of 50) facing away from each other, and the prefabricated interconnected silicon core stack structure (100) is disposed on the third surface (top of 50) and/or the fourth surface and electrically connected (160, fig 3) to the first prefabricated substrate (50, fig 3) [0047] respectively,
wherein the prefabricated interconnected silicon core stack structure (100) and the prefabricated substrate (50) [0047]constitute a first prefabricated unit,(100+50) and the first prefabricated unit (100+50) is packaged by the first plastic packaging layer (400, fig 3) [0041] to form the lower package (100/370/300/400, fig 4).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Jo and Paek to include the lower package further comprises a first prefabricated substrate, the first prefabricated substrate comprises a third surface and a fourth surface facing away from each other, and the prefabricated interconnected silicon core stack structure is disposed on the third surface and/or the fourth surface and electrically connected to the first prefabricated substrate respectively,
wherein the prefabricated interconnected silicon core stack structure and the prefabricated substrate constitute a first prefabricated unit, and the first prefabricated unit is packaged by the first plastic packaging layer to form the lower package as claimed.
The ordinary artisan would have been motivated modify Jo and Paek in the above manner for the purpose of protect the third redistribution pattern from external impact and may prevent an electrical short circuit [0070].
Re claim 16 Jo in view of Paek teaches the packaging structure according to claim 15, wherein the lower package further comprises an underfill layer filled (130, fig 3) [Jo,0014] between the prefabricated interconnected silicon core stack structure (Jo, 100, fig 3) and the first prefabricated substrate (50, fig 3) [0047].
Claims 3, 12, 14 are rejected under 35 U.S.C. 103 as being unpatentable over Jo modified by Paek as applied to claim 1 above and further in view of Wu et al (US20210375785A1).
Re claim 3 Jo in view of Paek teaches the packaging structure according to claim 2,
Jo and Paek do not teach an edge of the back-surface redistribution stack layer protrudes from an edge of the prefabricated interconnected silicon core stack structure and extends to be stacked on the first plastic packaging layer, and/or an edge of the passivation layer protrudes from an edge of the silicon interconnection layer and extends to be stacked on the first plastic packaging layer.
Wu teaches, an edge of the back-surface redistribution stack layer (224, fig 17) protrudes from an edge (an edge of 220A/B, fig 17) of the prefabricated interconnected silicon core stack structure (220A/B, fig 17) and extends to be stacked on the first plastic packaging layer (304, fig 17) [0057], and/or an edge of the passivation layer protrudes from an edge of the silicon interconnection layer and extends to be stacked on the first plastic packaging layer.
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Jo into the structure of Jo and Paek to include an edge of the back-surface redistribution stack layer protrudes from an edge of the prefabricated interconnected silicon core stack structure and extends to be stacked on the first plastic packaging layer, and/or an edge of the passivation layer protrudes from an edge of the silicon interconnection layer and extends to be stacked on the first plastic packaging layer as claimed.
The ordinary artisan would have been motivated to modify Jo and Paek based on the teaching of Jo in the above manner for the purpose of achieving greater stability to the structure [0080].
Re claim 12 Jo in view of Paek teaches the packaging structure according to claim 10,
Jo and Paek do not teach an auxiliary structure disposed at an edge and/or corner of the first redistribution stack layer.
Wu does teach an auxiliary structure (320, fig 29) [0066] disposed at an edge and/or corner of the first redistribution stack layer (100, fig 29) [0079].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Wu into the structure of Jo and Paek to include an auxiliary structure disposed at an edge and/or corner of the first redistribution stack layer as claimed.
The ordinary artisan would have been motivated to modify Jo and Paek based on the teaching of Wu in the above manner for the purpose to provide further mechanical support to reduce the warpage of the package structure [0066].
Re claim 14 Jo in view of Paek teaches the packaging structure according to claim 1,
Jo and Paek do not teach there are two or more prefabricated interconnected silicon core stack structures in the first plastic packaging layer, and two or more prefabricated interconnected silicon core stack structures are horizontally disposed side by side and all plastic-packaged by the first plastic packaging layer, wherein two or more prefabricated interconnected silicon core stack structures have same or different sizes.
Wu teaches there are two or more prefabricated interconnected silicon core stack structures (200B/200A, fig 29) [0054] in the first plastic packaging layer (224, fig 29), and two or more prefabricated interconnected silicon core stack structures (200B/200A, fig 29)[0054] are horizontally disposed side by side (see fig 29) and all plastic-packaged by the first plastic packaging layer (224, fig 29), wherein two or more prefabricated interconnected silicon core stack structures (200B/200A) have same or different sizes.(see fig 29).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Wu into the structure of Jo and Paek to include there are two or more prefabricated interconnected silicon core stack structures in the first plastic packaging layer, and two or more prefabricated interconnected silicon core stack structures are horizontally disposed side by side and all plastic-packaged by the first plastic packaging layer, wherein two or more prefabricated interconnected silicon core stack structures have same or different sizes as claimed.
The ordinary artisan would have been motivated to modify Jo and Paek based on the teaching of Wu in the above manner for the purpose of protecting the connectors and provide structural support for the package structure [0056].
Claims 5 is rejected under 35 U.S.C. 103 as being unpatentable over Jo modified by Paek as applied to claim 1 above and further in view of Yee et al (US20170062383A1).
Re claim 5 Jo in view of Paek teaches the packaging structure according to claim 4, wherein the upper package (500/600, fig 4) comprises a chip and/or device package (500, fig 4) in a thickness direction (vertical) of the packaging structure(fig 4) ;
Jo and Paek do not teach the lower package further comprises at least one first functional block and/or at least one second functional block;
the at least one first functional block is embedded in a first base material layer of the first prefabricated redistribution stack layer; and
the at least one second functional block is embedded in a second base material layer of the second prefabricated redistribution stack layer;
the at least one first functional block is stacked below the corresponding chip and/or device package; and the at least one second functional block is stacked below the corresponding chip and/or device package.
Yee teaches the lower package (104/106/116/118, fig 1/fig 15) further comprises at least one first functional block (left 1112, fig 15) [0055] and/or at least one second functional block (right 112, fig 15) [0055];
the at least one first functional block (left 1112) is embedded in a first base material layer (left 106, fig 15) [0041] of the first prefabricated redistribution stack layer (left 104/106/116, fig 15); and
the at least one second functional block (right 1112) is embedded in a second base material layer (right 106, fig 15) [0055] of the second prefabricated redistribution stack layer (right 104/106/116);
the at least one first functional block (left 1112) is stacked below the corresponding chip (102) and/or device package; and the at least one second functional block (right 1112) is stacked below the corresponding chip(102, fig15) and/or device package.
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Yee into the structure of Jo and Paek to include the lower package further comprises at least one first functional block and/or at least one second functional block;
the at least one first functional block is embedded in a first base material layer of the first prefabricated redistribution stack layer; and
the at least one second functional block is embedded in a second base material layer of the second prefabricated redistribution stack layer;
the at least one first functional block is stacked below the corresponding chip and/or device package; and the at least one second functional block is stacked below the corresponding chip and/or device package as claimed.
The ordinary artisan would have been motivated to modify Jo based on the teaching of Yee in the above manner for the purpose of improving data bandwidth and enable faster data access and data storage [0017].
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Jo and Paek in view of Wang et al (US 20170147851 A1).
Re claim 6 Jo in view of Paek teaches the packaging structure(fig 4) according to claim 4, wherein the lower package (100/300/370/400, fig 4) [0029] further comprises a prefabricated chip packaging layer (300/400, fig 4) [0029], the prefabricated chip packaging layer comprises a plurality of second prefabricated conductive pillars (430/380, fig 4) [0031], a first chip (300, fig 4) [0029] and a prefabricated plastic packaging layer (210), the plurality of second prefabricated conductive pillars (430/380, fig 4) and the first chip (300) are embedded in the prefabricated plastic packaging layer (210) respectively and
the first plastic packaging layer (400, fig 4) further covers an outer side of the prefabricated plastic packaging layer (210, fig 4),
wherein the prefabricated chip packaging layer (300/400, fig 4) is disposed at a side (top side) of the first prefabricated redistribution stack layer (100) away from the silicon interconnection layer (110); or
the prefabricated chip packaging layer (400, fig 4) is disposed at a side of the second prefabricated redistribution stack layer (440/430/380) away from the silicon interconnection layer (110, fig 4),
Jo and Paek do not teach the thickness of the prefabricated plastic packaging layer is 50 to 200 um;
Wang does teach the thickness of the prefabricated plastic packaging layer is 50 to 200 um (20 microns to 100 microns) [0009].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Wang into the structure of Jo to include the thickness of the prefabricated plastic packaging layer is 50 to 200 um as claimed.
The ordinary artisan would have been motivated to modify Jo and Paek based on the teaching of Wang in the above manner for purpose reducing manufacturing cost of the package structure [0030].
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Jo modified by Paek and Wang as applied to claims 1 and 6 further in view of Wu et al (US20210375785A1).
Re claim 7 Jo in view of Paek and Wang teaches the packaging structure according to claim 6,
Jo, Paek and Wang do not teach the lower package further comprises a third prefabricated redistribution stack layer that is disposed between the prefabricated chip packaging layer and the back-surface redistribution stack layer and is electrically connected to the prefabricated chip packaging layer and the back-surface redistribution stack layer.
Wu does teach the lower package further comprises a third prefabricated redistribution stack layer (108B, fig 10, 11/13 ) [0035] that is disposed between the prefabricated chip packaging layer (202/210/211, fig 11/13), and the back-surface redistribution stack layer (108A, fig 10, 13) [0035 and is electrically connected to the prefabricated chip packaging layer (through 220, fig 13) and the back-surface redistribution stack layer (108A, fig 10/13) [0035].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Wu into the structure of Jo, Paek and Wang to include the lower package further comprises a third prefabricated redistribution stack layer that is disposed between the prefabricated chip packaging layer and the back-surface redistribution stack layer and is electrically connected to the prefabricated chip packaging layer and the back-surface redistribution stack layer as claimed.
The ordinary artisan would have been motivated to modify Jo, Paek and Wang based on the teaching of Wu in the above manner for the purpose of improving the functionality of the device.
Furthermore, it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. (MPEP § 2144.04 VI. B.).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Jo modified by Paek and Wang et al (US 20170147851 A1) as applied to claim 6 above and further in view of Maeda et al (US 20080272829A1).
Re claim 8 Jo in view of Paek and Wang teaches the packaging structure according to claim 6,
Jo, Paek and Wang do not teach the prefabricated plastic packaging layer further comprises a third functional block embedded therein, and the third functional block and the first chip are horizontally disposed side by side in the prefabricated plastic packaging layer.
Maeda teaches the prefabricated plastic packaging layer (12, fig 9) [0021] further comprises a third functional block (40, fig 9) [0026] embedded therein, and the third functional block (40, fig 9) [0026] and the first chip (30, fig 9) [0022] are horizontally disposed side by side in the prefabricated plastic packaging layer (see fig 9).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Maeda into the structure of Jo and Wang to include the prefabricated plastic packaging layer further comprises a third functional block embedded therein, and the third functional block and the first chip are horizontally disposed side by side in the prefabricated plastic packaging layer as claimed because it has been held that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70 and/or it has been held that mere duplication of partshas no patentable significance unless a new and unexpected result is produced, In re Harza, 274 F. 2d 669, 124 USPQ 378(CCPA 1960).
The ordinary artisan would have been motivated to modify Jo, Paek, and Wang based on the teaching of Maeda in the above manner for the purpose to achieve lower power consumption and miniaturization, in addition to higher performance. [0004].
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Jo as modified by Paek as applied to claim 1, further in view of Takeichi et al (US 6903463 B1).
Re claim 9 Jo in view of Paek teaches the packaging structure according to claim 1,
the lower package (100/370/300/400, fig 4) [0013] further comprises a solder mask layer (750, 80, fig 4) disposed between the first prefabricated redistribution stack layer (370, fig 4) and the upper package(500/600, fig 4),
Jo and Paek do not teach the elastic modulus or tensile elongation at break of the solder mask layer is the same as or different from the elastic modulus or tensile elongation at break of a dielectric layer in the first prefabricated redistribution stack layer.
Takeichi teaches the elastic modulus or tensile elongation at break of the solder mask layer (connecting material 5, fig 1a) [col 7, lines 5-10] is the same as or different from the elastic modulus or tensile elongation at break of a dielectric layer (2, fig 1a) [col 7 lines 20-30] in the first prefabricated redistribution stack layer (1, fig 1a) [col 7, lines 5-10].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Takeichi into the structure of Jo and Paek to include the elastic modulus or tensile elongation at break of the solder mask layer is the same as or different from the elastic modulus or tensile elongation at break of a dielectric layer in the first prefabricated redistribution stack layer as claimed.
The ordinary artisan would have been motivated to modify Jo and Paek based on the teaching of Takeichi in the above manner for the purpose of providing a superior bonding strength and excellent electroconductive performance (Abstract, Takeichi).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Jo as modified by Paek as applied to claim 1 above and further in view of Lo et al (US20140021583A1) and Wu et al (US20210375785A1).
Re claim 11 Jo in view of Paek teaches the packaging structure according to claim 10, further comprising a second redistribution stack layer (710, fig 4) [0071] and an interconnected chip packaging layer (710, fig 4) [0071] that are disposed between the lower package ( 100/370/300/400, fig 4) [0013] and the first redistribution stack layer (750, fig 4) [0071], wherein the second redistribution stack layer (720) is disposed above the lower package 100/370/300/400, fig 4) [0013] ;
the interconnected chip packaging layer (710) is disposed above the second redistribution stack layer (720).
Jo and Paek do not teach the interconnected chip packaging layer comprises a plurality of conductive pillars , an interconnected chip and a second plastic packaging layer the plurality of conductive pillars and the interconnected chip are embedded in the second plastic packaging layer respectively, two opposite ends of each conductive pillar are electrically connected to the first redistribution stack layer and the second redistribution stack layer; and
the interconnected chip comprises an interconnected redistribution stack layer and a connection bump located above the interconnected redistribution stack layer, the connection bump (120) is electrically connected to the first redistribution stack layer (106) and the interconnected redistribution stack layer, and interconnected redistribution stack layer comprises at least one capacitor.
Lo teaches the interconnected chip packaging layer (102/104, fig 9) [0019] comprises a plurality of conductive pillars , an interconnected chip (102) [0019] and a second plastic packaging layer (66, fig 5) [0018] the plurality of conductive pillars (108, fig 9) [ 0019] and the interconnected chip (102) are embedded in the second plastic packaging layer (66) respectively, two opposite ends of each conductive pillar (108) are electrically connected to the first redistribution stack (106, fig 9) [0019] layer and the second redistribution stack layer (110, fig9) [0019], and; and
the interconnected chip (102) comprises an interconnected redistribution stack layer (50/42/22/20, fig 6) [0015] and a connection bump (54, fig 6) located above the interconnected redistribution stack layer (50/42, fig 8), the connection bump (120) is electrically connected to the first redistribution stack layer (106) and the interconnected redistribution stack layer (50/42/22/20), , and interconnected redistribution stack layer (50/42/22/20) comprises at least one capacitor (20, fig 6) [0021].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Lo into the structure of Jo to include the interconnected chip packaging layer comprises a plurality of conductive pillars , an interconnected chip and a second plastic packaging layer the plurality of conductive pillars and the interconnected chip are embedded in the second plastic packaging layer respectively, two opposite ends of each conductive pillar are electrically connected to the first redistribution stack layer and the second redistribution stack layer; and
the interconnected chip comprises an interconnected redistribution stack layer and a connection bump located above the interconnected redistribution stack layer, the connection bump is electrically connected to the first redistribution stack layer and the interconnected redistribution stack layer, and interconnected redistribution stack layer comprises at least one capacitor as claimed.
The ordinary artisan would have been motivated to modify Jo and Paek based on the teaching of Lo in the above manner for the purpose of providing integration density using various features [0003].
Jo, Paek and Lo do not teach the thickness of the second plastic packaging layer is 150 to 780 um and the minimum line width/line spacing of the interconnected redistribution stack layer is less than 2 um.
Wu does teach the thickness of the second plastic packaging layer is 150 to 780 um ( 212/213, fig 11) [0048]and the minimum line width/line spacing of the interconnected redistribution stack layer is less than 2 um (fig 24, 408B, about 2 um to about 15um)[0073].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Wu into the structure of Jo, Paek and Lo to include the thickness of the second plastic packaging layer is 150 to 780 um and the minimum line width/line spacing of the interconnected redistribution stack layer is less than 2 um as claimed.
The ordinary artisan would have been motivated to modify Jo, Paek and Lo based on the teaching of Wu in the above manner for the purpose of improving circuit efficiency and/or reducing heat generation and power consumption [0075].
Furthermore, it has been held in that the applicant must show that a particular range is critical generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir 1990).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Jo as modified by Paek as applied to claim 1 in view of Reefman et al (US 20090146760 A1).
Re claim 13 Jo in view of Paek teaches the packaging structure according to claim 1,
Jo and Paek do not teach the silicon interconnection layer further comprises a trench-type silicon capacitor electrically connected to the back-end redistribution stack layer.
Reefman teaches the silicon interconnection layer (100, fig 10) [0082] further comprises a trench-type silicon capacitor (0082, fig 10) electrically connected to the back-end redistribution stack layer (220/114/231, fig 10).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Reefman into the structure of Jo and Paek to include the silicon interconnection layer further comprises a trench-type silicon capacitor electrically connected to the back-end redistribution stack layer as claimed.
The ordinary artisan would have been motivated to modify Joand Paek based on the teaching of Reefman in the above manner for the purpose of as to reduce eddy currents and parasitic to a minimum [0011].
Claim 17 are rejected under 35 U.S.C. 103 as being unpatentable over Jo modified by Paek as applied to claim 1 above and further in view of Chang et al (US 20210057343A1).
Re claim 17 Jo in view of Paek teaches the packaging structure according to claim 1,
Jo and Paek do not teach, the lower package further comprises a second prefabricated substrate and/or a third prefabricated substrate, the second prefabricated substrate and/or the third prefabricated substrate are horizontally disposed side by side with respect to the prefabricated interconnected silicon core stack structure respectively to constitute a second prefabricated unit, and the second prefabricated unit is packaged by the first plastic packaging layer to form the lower
package, wherein base material layers of the second prefabricated substrate and the third prefabricated substrate are made of the same or different materials.
Chang does teach the lower package (131, fig 1H) [0032] further comprises a second prefabricated substrate (left 137a, fig 1H) [0036] and/or a third prefabricated substrate (right 137b), the second prefabricated substrate (left 137a, fig 1H) [0036] and/or the third prefabricated substrate (right 137b) are horizontally disposed side by side (see fig 1H) with respect to the prefabricated interconnected silicon core stack structure (127/129, fig 1H) [0032] respectively to constitute a second prefabricated unit (left 127/129+137a, fig 1H)[0032], and the second prefabricated unit is packaged by the first plastic packaging layer (143, fig 1H)[0045] to form the lower package,
wherein base material layers (left/right 141, fig 1H) of the second prefabricated substrate (left 137a) and the third prefabricated substrate (right 137b) are made of the same or different materials. [0040].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Chang into the structure of Jo to include the lower package further comprises a second prefabricated substrate and/or a third prefabricated substrate, the second prefabricated substrate and/or the third prefabricated substrate are horizontally disposed side by side with respect to the prefabricated interconnected silicon core stack structure respectively to constitute a second prefabricated unit, and the second prefabricated unit is packaged by the first plastic packaging layer to form the lower package, wherein base material layers of the second prefabricated substrate and the third prefabricated substrate are made of the same or different materials as claimed.
The ordinary artisan would have been motivated to modify Jo and Paek based on the teaching of Chang in the above manner for the purpose of to improve the density and functionality of semiconductor device [0003].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRATIKSHA J LOHAKARE whose telephone number is (571)270-1920. The examiner can normally be reached Monday - Friday 7.30 am-4.30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at 571-270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PRATIKSHA JAYANT LOHAKARE/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 2/19/26