DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed March 24, 2026 has been entered. Claims 1-3, 6-11, and 14-17 remain pending in the application. Applicant’s amendments to the Drawings have overcome each and every objection previously set forth in the Non-Final Office Action mailed January 13, 2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-3 and 6-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “the plurality of through holes” in line 8 on page 5. There is insufficient antecedent basis for this limitation in the claim. For purposes of Examination, Examiner will interpret the limitation of line 8 to mean “the plurality of second through holes” in keeping with the remainder of the amendment.
Claims 2-3 and 6-8 are also rejected as they are dependent on claim 1.
Claim 9 recites the limitation “the plurality of through holes” in line 7 on page 7. There is insufficient antecedent basis for this limitation in the claim. For purposes of Examination, Examiner will interpret the limitation of line 8 to mean “the plurality of second through holes” in keeping with the remainder of the amendment.
Claims 10-11 and 14-16 are also rejected as they are dependent on claim 9.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 7, 9-11, and 15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee (US 20220262876 A1).
Regarding claim 1, Lee teaches a display panel (Fig 2 display layer 100, [0059]), comprising an array substrate (Fig 3 base layer 110, [0062]), the array substrate (Fig 3 base layer 110, [0062]) having a plurality of pixels (not shown; However, Fig 3 shows one sub pixel PXA of a plural of pixels, [0097]), each of the plurality of pixels (not shown; However, Fig 3 shows one sub pixel PXA of a plural of pixels, [0097]) comprising a plurality of sub-pixels (not shown; However, Fig 3 shows one sub pixel PXA of a plural of pixels, [0097]; a display would need a plurality of these sub-pixels), each of the plurality of sub-pixels (not shown; However, Fig 3 shows one sub pixel PXA of a plural of pixels, [0097]; a display would need a plurality of these sub-pixels) comprising an opening region (Fig 3 first opening 70op1, [0091]) and a non-opening region (Fig 3 second opening 70op2, [0091]), an anode layer (Fig 3 pixel electrode AE, [0089]), a light emitting layer (Fig 3 light emitting functional layer EL, [0089]) and a portion of a cathode layer (Fig 3 common electrode CE over 70op1, [0089]) being laminated in sequence (Fig 3) in the opening region (Fig 3 first opening 70op1, [0091]) of the sub-pixel (Fig 3 portion with light emitting area PXA and a non-light-emitting area NPXA, [0093]), wherein the non-opening region (Fig 3 second opening 70op2, [0091]) is a region which does not allow light to pass through (the array substrate may be made of an opaque material that does not allow light to pass though, [0062]); and wherein, an auxiliary cathode layer (Fig 3 auxiliary electrode CE-A, [0092]) and another portion of the cathode layer (Fig 3 common electrode CE over 70op2, [0089]) are laminated in sequence (Fig 3) in the non-opening region (Fig 3 second opening 70op2, [0091]) of the sub-pixel (Fig 3 portion with light emitting area PXA and a non-light-emitting area NPXA, [0093]), the portion of the cathode layer (Fig 3 common electrode CE over 70op1, [0089]) in the opening region (Fig 3 first opening 70op1, [0091]) and the another portion of the cathode layer (Fig 3 common electrode CE over 70op2, [0089]) in the non-opening region (Fig 3 second opening 70op2, [0091]) of the sub-pixel (Fig 3 portion with light emitting area PXA and a non-light-emitting area NPXA, [0093]) are connected (Fig 3), and the auxiliary cathode layer (Fig 3 auxiliary electrode CE-A, [0092]) is spaced apart from (Fig 3) the anode layer (Fig 3 pixel electrode AE, [0089]); wherein each auxiliary cathode layer (Fig 3 auxiliary electrode CE-A, [0092]) is connected (Fig 3) to the another portion of the cathode layer (Fig 3 common electrode CE over 70op2, [0089]) of a respective one of the plurality of sub-pixels (Fig 3 portion with light emitting area PXA and a non-light-emitting area NPXA, [0093]); the display panel (Fig 2 display layer 100, [0059]) further comprising a pixel defining layer (Fig 3 pixel definition layer 70, [0091]), wherein, the pixel defining layer (Fig 3 pixel definition layer 70, [0091]) is arranged on (Fig 3) the array substrate (Fig 3 base layer 110, [0062]); the pixel defining layer (Fig 3 pixel definition layer 70, [0091]) defines a plurality of first through holes (Fig 3 first opening 70op1, [0091]), each of the plurality of first through holes (Fig 3 first opening 70op1, [0091]) exposing the anode layer (Fig 3 pixel electrode AE, [0089]) of a respective one of the plurality of sub-pixels (Fig 3 portion with light emitting area PXA and a non-light-emitting area NPXA, [0093]), wherein the anode layer (Fig 3 pixel electrode AE, [0089]) is arranged at a bottom of the (Fig 3) first through hole (Fig 3 first opening 70op1, [0091]); the light emitting layer (Fig 3 light emitting functional layer EL, [0089]) is arranged on the (Fig 3) anode layer (Fig 3 pixel electrode AE, [0089]) and a side wall (Fig 3 not labeled side wall of 70op1) of the first through hole (Fig 3 first opening 70op1, [0091]); and the cathode layer (Fig 3 common electrode CE over 70op1, [0089]) is arranged on the (Fig 3) light emitting layer (Fig 3 light emitting functional layer EL, [0089]); the pixel defining layer (Fig 3 pixel definition layer 70, [0091]) defines a plurality of second through holes (Fig 3 second opening 70op2, [0091]), each of the plurality of second through holes (Fig 3 second opening 70op2, [0091]) exposing the (Fig 3) entire auxiliary cathode layer (Fig 3 auxiliary electrode CE-A, [0092]) of the respective one of the plurality of sub-pixels (Fig 3 portion with light emitting area PXA and a non-light-emitting area NPXA, [0093]); the auxiliary cathode layer (Fig 3 auxiliary electrode CE-A, [0092]) is arranged at a bottom of (Fig 3) the second through hole (Fig 3 second opening 70op2, [0091]); and the cathode layer (Fig 3 common electrode CE over 70op2, [0089]) is arranged on the auxiliary cathode layer (Fig 3 auxiliary electrode CE-A, [0092]) and on a side wall (Fig 3 not labeled side wall of 70op2) of the second through hole (Fig 3 second opening 70op2, [0091]); every adjacent two sub-pixels (See annotated figure; not labeled; however, Examiner interprets the space as a sub-pixel since [0125] discloses referring to Fig 3 and 6A) of the plurality of sub-pixels (See annotated figure; Examiner interprets the space as a sub-pixel since [0125] discloses referring to Fig 3 and 6A) are spaced apart from each other by a respective one of the plurality of second through holes (Fig 4 not labeled, corresponds to mesh lines MS1 and MS2, which corresponds to Fig 3 second opening 70op2, [0091] since the auxiliary electrode is defined as being in the second through hole) having the auxiliary cathode layer (Fig 4 auxiliary electrode CE-A, [0092]) therein; the auxiliary cathode layer (Fig 4 auxiliary electrode CE-A, [0092]) in each of the plurality of second through holes (Fig 4 not labeled, corresponds to mesh lines MS1 and MS2, which corresponds to Fig 3 second opening 70op2, [0091] since the auxiliary electrode is defined as being in the second through hole) is conductively connected (Fig 3 they are the same layer) to the cathode layer (Fig 4 not labeled corresponds to Fig 3 common electrode CE over 70op2, [0089]) to enable auxiliary cathode layers (Fig 4 auxiliary electrode CE-A, [0092]) in every adjacent two (See annotated figure) of the plurality of through holes (Fig 4 not labeled, corresponds to mesh lines MS1 and MS2, which corresponds to Fig 3 second opening 70op2, [0091] since the auxiliary electrode is defined as being in the second through hole) to be directly conductively connected to each other (MS1 and MS2 intersect each other at CSA, [0128]) to form a plurality of auxiliary cathode rings (See annotated figure), and each of the plurality of auxiliary cathode rings (See annotated figure) surrounds a respective one of the plurality of sub-pixels (See annotated figure; Examiner interprets the space as a sub-pixel since [0125] discloses referring to Fig 3 and 6A).
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Regarding claim 2, Lee teaches the plurality of sub-pixels (Fig 3 portion with light emitting area PXA and a non-light-emitting area NPXA, [0093]) are a R sub-pixel (the light emitting layers may emit a red color, [0097]), a G sub-pixel (the light emitting layers may emit a green color, [0097]) and a B sub-pixel (the light emitting layers may emit a blue color, [0097]); a plurality of auxiliary cathode rings (Fig 6 mesh lines MS1 and MS2 intersect each other) cooperatively form a grid (Fig 6) of the auxiliary cathode layer (Fig 3 auxiliary electrode CE-A, [0092]).
Regarding claim 3, Lee teaches the plurality of sub-pixels (Fig 3 portion with light emitting area PXA and a non-light-emitting area NPXA, [0093]) are a R sub-pixel (the light emitting layers may emit a red color, [0097]), a G sub-pixel (the light emitting layers may emit a green color, [0097]), a B sub-pixel (the light emitting layers may emit a blue color, [0097]) and a W sub-pixel (the light emitting layers may provide a white light, [0097]); the sub-pixels (Fig 3 portion with light emitting area PXA and a non-light-emitting area NPXA, [0093]) at an edge row (Fig 6A top row of sub pixels) have a non-opening region (Fig 6A not labeled; however, second opening 70op2 corresponds with CE-A/MS1, [0091]) at an edge (Fig 6A), and the auxiliary cathode layer (Fig 3 auxiliary electrode CE-A, [0092]) is arranged in the non-opening region (Fig 6A not labeled; however, second opening 70op2 corresponds with CE-A/MS1, [0091]) at the edge (Fig 6A not labeled; however, second opening 70op2 corresponds with CE-A/MS1, [0091]).
Regarding claim 7, Lee teaches the auxiliary cathode layer (Fig 3 auxiliary electrode CE-A, [0092]) and the anode layer (Fig 3 pixel electrode AE, [0089]) are arranged on a same layer (Fig 3) and are spaced apart from each other (Fig 3).
Regarding claim 9, Lee teaches an electronic device (Fig 1 display device 1000, [0054]), comprising: a circuit substrate (Fig 2 circuit layer 120, [0065]) and a display panel (Fig 2 light emitting layer 130, [0066]) arranged on (Fig 2) and electrically connected ([0066]) to the circuit substrate(Fig 2 circuit layer 120, [0065]), wherein the circuit substrate (Fig 2 circuit layer 120, [0065]) is configured to supply power and a drive voltage (the circuit layer 120 controls or drives the light emitting layer 130, [0066]) for the display panel (Fig 2 light emitting layer 130, [0066]), and the display panel (Fig 2 light emitting layer 130, [0066]) comprises: an array substrate (Fig 3 base layer 110, [0062]), the array substrate (Fig 3 base layer 110, [0062]) having a plurality of pixels (not shown; However, Fig 3 shows one sub pixel PXA of a plural of pixels, [0097]), each of the plurality of pixels (not shown; However, Fig 3 shows one sub pixel PXA of a plural of pixels, [0097]) comprising a plurality of sub-pixels (not shown; However, Fig 3 shows one sub pixel PXA of a plural of pixels, [0097]; a display would need a plurality of these sub-pixels), each of the plurality of sub-pixels (not shown; However, Fig 3 shows one sub pixel PXA of a plural of pixels, [0097]; a display would need a plurality of these sub-pixels) comprising an opening region (Fig 3 first opening 70op1, [0091]) and a non-opening region (Fig 3 second opening 70op2, [0091]), an anode layer (Fig 3 pixel electrode AE, [0089]), a light emitting layer (Fig 3 light emitting functional layer EL, [0089]) and a portion of a cathode layer (Fig 3 common electrode CE over 70op1, [0089]) being laminated in sequence (Fig 3) in the opening region (Fig 3 first opening 70op1, [0091]) of the sub-pixel (Fig 3 portion with light emitting area PXA and a non-light-emitting area NPXA, [0093]), wherein the non-opening region (Fig 3 second opening 70op2, [0091]) is a region which does not allow light to pass through (the array substrate may be made of an opaque material that does not allow light to pass though, [0062]); and wherein, an auxiliary cathode layer (Fig 3 auxiliary electrode CE-A, [0092]) and another portion of the cathode layer (Fig 3 common electrode CE over 70op2, [0089]) are laminated in sequence (Fig 3) in the non-opening region (Fig 3 second opening 70op2, [0091]) of the sub-pixel (Fig 3 portion with light emitting area PXA and a non-light-emitting area NPXA, [0093]), the portion of the cathode layer (Fig 3 common electrode CE over 70op1, [0089]) in the opening region (Fig 3 first opening 70op1, [0091]) and the another portion of the cathode layer (Fig 3 common electrode CE over 70op2, [0089]) in the non-opening region (Fig 3 second opening 70op2, [0091]) of the sub-pixel (Fig 3 portion with light emitting area PXA and a non-light-emitting area NPXA, [0093]) are connected (Fig 3), and the auxiliary cathode layer (Fig 3 auxiliary electrode CE-A, [0092]) is spaced apart from (Fig 3) the anode layer (Fig 3 pixel electrode AE, [0089]); wherein each auxiliary cathode layer (Fig 3 auxiliary electrode CE-A, [0092]) is connected to the another portion of the cathode layer (Fig 3 common electrode CE over 70op2, [0089]) of a respective one of the plurality of sub-pixels (Fig 3 portion with light emitting area PXA and a non-light-emitting area NPXA, [0093]); the display panel (Fig 2 display layer 100, [0059]) further comprising a pixel defining layer (Fig 3 pixel definition layer 70, [0091]), wherein, the pixel defining layer (Fig 3 pixel definition layer 70, [0091]) is arranged on (Fig 3) the array substrate (Fig 3 base layer 110, [0062]); the pixel defining layer (Fig 3 pixel definition layer 70, [0091]) defines a plurality of first through holes (Fig 3 first opening 70op1, [0091]), each of the first through holes (Fig 3 first opening 70op1, [0091]) exposing the anode layer (Fig 3 pixel electrode AE, [0089]) of a respective one of the plurality of sub-pixels (Fig 3 portion with light emitting area PXA and a non-light-emitting area NPXA, [0093]), wherein the anode layer (Fig 3 pixel electrode AE, [0089]) is arranged at a bottom of the (Fig 3) first through hole (Fig 3 first opening 70op1, [0091]); the light emitting layer (Fig 3 light emitting functional layer EL, [0089]) is arranged on the (Fig 3) anode layer (Fig 3 pixel electrode AE, [0089]) and a side wall (Fig 3 not labeled side wall of 70op1) of the first through hole (Fig 3 first opening 70op1, [0091]); and the cathode layer (Fig 3 common electrode CE over 70op1, [0089]) is arranged on the (Fig 3) light emitting layer (Fig 3 light emitting functional layer EL, [0089]); the pixel defining layer (Fig 3 pixel definition layer 70, [0091]) defines a plurality of second through holes (Fig 3 second opening 70op2, [0091]) each of the plurality of second through holes (Fig 3 second opening 70op2, [0091]), exposing the (Fig 3) entire auxiliary cathode layer (Fig 3 auxiliary electrode CE-A, [0092]) of the respective one of the plurality of sub-pixels (Fig 3 portion with light emitting area PXA and a non-light-emitting area NPXA, [0093]); the auxiliary cathode layer (Fig 3 auxiliary electrode CE-A, [0092]) is arranged at a bottom of (Fig 3) the second through hole (Fig 3 second opening 70op2, [0091]); and the cathode layer (Fig 3 common electrode CE over 70op2, [0089]) is arranged on the auxiliary cathode layer (Fig 3 auxiliary electrode CE-A, [0092]) and on a side wall (Fig 3 not labeled side wall of 70op2) of the second through hole (Fig 3 second opening 70op2, [0091] ); every adjacent two sub-pixels (See annotated figure; not labeled; however, Examiner interprets the space as a sub-pixel since [0125] discloses referring to Fig 3 and 6A) of the plurality of sub-pixels (See annotated figure; Examiner interprets the space as a sub-pixel since [0125] discloses referring to Fig 3 and 6A) are spaced apart from each other by a respective one of the plurality of second through holes (Fig 4 not labeled, corresponds to mesh lines MS1 and MS2, which corresponds to Fig 3 second opening 70op2, [0091] since the auxiliary electrode is defined as being in the second through hole) having the auxiliary cathode layer (Fig 4 auxiliary electrode CE-A, [0092]) therein; the auxiliary cathode layer (Fig 4 auxiliary electrode CE-A, [0092]) in each of the plurality of second through holes (Fig 4 not labeled, corresponds to mesh lines MS1 and MS2, which corresponds to Fig 3 second opening 70op2, [0091] since the auxiliary electrode is defined as being in the second through hole) is conductively connected (Fig 3 they are the same layer) to the cathode layer (Fig 4 not labeled corresponds to Fig 3 common electrode CE over 70op2, [0089]) to enable auxiliary cathode layers (Fig 4 auxiliary electrode CE-A, [0092]) in every adjacent two (See annotated figure) of the plurality of through holes (Fig 4 not labeled, corresponds to mesh lines MS1 and MS2, which corresponds to Fig 3 second opening 70op2, [0091] since the auxiliary electrode is defined as being in the second through hole) to be directly conductively connected to each other (MS1 and MS2 intersect each other at CSA, [0128]) to form a plurality of auxiliary cathode rings (See annotated figure), and each of the plurality of auxiliary cathode rings (See annotated figure) surrounds a respective one of the plurality of sub-pixels (See annotated figure; Examiner interprets the space as a sub-pixel since [0125] discloses referring to Fig 3 and 6A).
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Regarding claim 10, Lee teaches the plurality of sub-pixels (Fig 3 portion with light emitting area PXA and a non-light-emitting area NPXA, [0093]) are a R sub-pixel (the light emitting layers may emit a red color, [0097]), a G sub-pixel (the light emitting layers may emit a green color, [0097]) and a B sub-pixel (the light emitting layers may emit a blue color, [0097]); a plurality of auxiliary cathode rings (Fig 6 mesh lines MS1 and MS2 intersect each other) cooperatively form a grid (Fig 6) of the auxiliary cathode layer (Fig 3 auxiliary electrode CE-A, [0092]).
Regarding claim 11, Lee teaches the plurality of sub-pixels (Fig 3 portion with light emitting area PXA and a non-light-emitting area NPXA, [0093]) are a R sub-pixel (the light emitting layers may emit a red color, [0097]), a G sub-pixel (the light emitting layers may emit a green color, [0097]), a B sub-pixel (the light emitting layers may emit a blue color, [0097]) and a W sub-pixel (the light emitting layers may provide a white light, [0097]); the sub-pixels (Fig 3 portion with light emitting area PXA and a non-light-emitting area NPXA, [0093]) at an edge row (Fig 6A top row of sub pixels) have a non-opening region (Fig 6A not labeled; however, second opening 70op2 corresponds with CE-A/MS1, [0091]) at an edge (Fig 6A), and the auxiliary cathode layer (Fig 3 auxiliary electrode CE-A, [0092]) is arranged in the non-opening region (Fig 6A not labeled; however, second opening 70op2 corresponds with CE-A/MS1, [0091]) at the edge (Fig 6A not labeled; however, second opening 70op2 corresponds with CE-A/MS1, [0091]).
Regarding claim 15, Lee teaches the auxiliary cathode layer (Fig 3 auxiliary electrode CE-A, [0092]) and the anode layer (Fig 3 pixel electrode AE, [0089]) are arranged on a same layer (Fig 3) and are spaced apart from each other (Fig 3).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20220262876 A1), in view of Kim et. al. (US 20230110744 A1), hereinafter Kim.
Regarding claim 6, Lee fails to teach a conductive metal post is arranged on the pixel defining layer and corresponds to the auxiliary cathode layer; and the cathode layer is connected to the auxiliary cathode layer through the conductive metal post.
However, Kim teaches a conductive metal post (Fig 7 conductive layer COL, [0120]) is arranged on the pixel defining layer (Fig 7 bank layer BNL, [0135] corresponds to Lee: Fig 3 pixel definition layer 70, [0091]) and corresponds to the auxiliary cathode layer (Fig 7 auxiliary electrode AXE, [0120] corresponds to Lee: Fig 3 auxiliary electrode CE-A, [0092]); and the cathode layer (Fig 7 cathode electrode CAT, [0120] corresponds to Lee: Fig 3 common electrode CE over 70op2, [0089]) is connected to (Fig 7) the auxiliary cathode layer (Fig 7 auxiliary electrode AXE, [0120] corresponds to Lee: Fig 3 auxiliary electrode CE-A, [0092]) through the conductive metal post (Fig 7 conductive layer COL, [0120]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Lee to incorporate the teachings of Kim by having a conductive metal post to connect the cathode layer to the auxiliary cathode layer. This would aid in lowering the resistance of the cathode electrode ([0143]).
Regarding claim 14, Lee fails to teach a conductive metal post is arranged on the pixel defining layer and corresponds to the auxiliary cathode layer; and the cathode layer is connected to the auxiliary cathode layer through the conductive metal post.
However, Kim teaches a conductive metal post (Fig 7 conductive layer COL, [0120]) is arranged on the pixel defining layer (Fig 7 bank layer BNL, [0135] corresponds to Lee: Fig 3 pixel definition layer 70, [0091]) and corresponds to the auxiliary cathode layer (Fig 7 auxiliary electrode AXE, [0120] corresponds to Lee: Fig 3 auxiliary electrode CE-A, [0092]); and the cathode layer (Fig 7 cathode electrode CAT, [0120] corresponds to Lee: Fig 3 common electrode CE over 70op2, [0089]) is connected to (Fig 7) the auxiliary cathode layer (Fig 7 auxiliary electrode AXE, [0120] corresponds to Lee: Fig 3 auxiliary electrode CE-A, [0092]) through the conductive metal post (Fig 7 conductive layer COL, [0120]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Lee to incorporate the teachings of Kim by having a conductive metal post to connect the cathode layer to the auxiliary cathode layer. This would aid in lowering the resistance of the cathode electrode ([0143]).
Claims 8 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20220262876 A1).
Regarding claim 8, Lee fails to teach material of the auxiliary cathode layer is the same as material of the anode layer.
However, one having ordinary skill in the art before the effective filing date of the claimed invention would recognize that in having the materials of the anode and auxiliary cathode layer being the same there would be reduced material costs.
Regarding claim 16, Lee fails to teach material of the auxiliary cathode layer is the same as material of the anode layer.
However, one having ordinary skill in the art before the effective filing date of the claimed invention would recognize that in having the materials of the anode and auxiliary cathode layer being the same there would be reduced material costs.
Allowable Subject Matter
Claim 17 is allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The closest art is Lee (US 20220262876 A1).
Lee teaches a method of manufacturing ([0072]-[0100]) the display panel according to claim 1 (Examiner interprets the preamble limitation of depending claim 1 loosely), comprising: providing the array substrate (Fig 3 base layer 110, [0062]), forming ([0090]) the anode layer (Fig 3 pixel electrode AE, [0089]) and the ([0092]) auxiliary cathode layer (Fig 3 auxiliary electrode CE-A, [0092]) on the array substrate (Fig 3 base layer 110, [0062]), wherein the anode layer (Fig 3 pixel electrode AE, [0089]) and the auxiliary cathode layer (Fig 3 auxiliary electrode CE-A, [0092]) are spaced apart from each other (Fig 3); forming ([0094]) the light emitting layer (Fig 3 light emitting functional layer EL, [0089]) on the anode layer (Fig 3 pixel electrode AE, [0089]); and forming ([0098]) the cathode layer (Fig 3 common electrode CE, [0098]) on the light emitting layer (Fig 3 light emitting functional layer EL, [0089]) and the auxiliary cathode layer (Fig 3 auxiliary electrode CE-A, [0092]); wherein after providing the array substrate (Fig 3 base layer 110, [0062]), forming ([0090]) the anode layer (Fig 3 pixel electrode AE, [0089]) and the ([0092]) auxiliary cathode layer (Fig 3 auxiliary electrode CE-A, [0092]) on the array substrate (Fig 3 base layer 110, [0062]), and before forming ([0098]) the cathode layer (Fig 3 common electrode CE, [0098]) on the light emitting layer (Fig 3 light emitting functional layer EL, [0089]) and the auxiliary cathode layer (Fig 3 auxiliary electrode CE-A, [0092]) the method further comprises: forming ([0091]) a pixel defining layer (Fig 3 pixel definition layer 70, [0091]) on the array substrate (Fig 3 base layer 110, [0062]), defining ([0091]) a first through hole (Fig 3 first opening 70op1, [0091]) in the pixel defining layer (Fig 3 pixel definition layer 70, [0091]) to face directly the anode layer (Fig 3 pixel electrode AE, [0089]) and to expose the anode layer (Fig 3 pixel electrode AE, [0089]); and the forming ([0098]) a cathode layer (Fig 3 common electrode CE, [0098]) on the light emitting layer (Fig 3 light emitting functional layer EL, [0089]) and the auxiliary cathode layer (Fig 3 auxiliary electrode CE-A, [0092]), comprises: forming ([0098]) the cathode layer (Fig 3 common electrode CE, [0098]) on the light emitting layer (Fig 3 light emitting functional layer EL, [0089]), the pixel defining layer (Fig 3 pixel definition layer 70, [0091]), a side wall (Fig 3 not labeled side wall of 70op1) of the first through hole (Fig 3 first opening 70op1, [0091]), a side wall (Fig 3 not labeled side wall of 70op2) of the second through hole (Fig 3 second opening 70op2, [0091]), and the auxiliary cathode layer (Fig 3 auxiliary electrode CE-A, [0092]).
Lee fails to teach defining a second through hole in the pixel defining layer to face directly the auxiliary cathode layer and to expose the entire auxiliary cathode layer.
Examiner notes that Lee teaches the auxiliary electrode is disposed and formed in the second opening after the pixel electrode AE ([0092]). There being no rationale to form the auxiliary electrode at the same time as the pixel electrode AE to later be fully exposed by a through hole.
Response to Arguments
Applicant’s arguments, see 35 USC §112 section on page 9, filed March 24, 2026, with respect to amendments to claim 1 and 9 have been fully considered and are persuasive. The 35 USC §112 of claims 1-3, 6-11, and 14-18 has been withdrawn.
Applicant’s arguments, see Allowable Subject matter section on page 11, filed March 24, 2026, with respect to the rejection of claims 1-3, 6-11, and 14-18 under 35 USC §102 and 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of a different embodiment in Lee.
Applicant’s arguments, see Allowable Subject matter section on page 12, filed March 24, 2026, with respect to the amendment of allowable subject matter have been fully considered and are persuasive. The 35 USC §102 of claim 17 has been withdrawn.
Examiner notes the preamble of claim 17 is loosely interpreted as dependent on claim 1. That is the method of claim 17 does not require all limitations of claim 1. Should all the limitations of claim 1 be required then claim 17 would be treated as a product-by-process claim.
Conclusion
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALVIN L LEE whose telephone number is (703)756-1921. The examiner can normally be reached Monday - Friday 8:30 am - 5 pm (ET).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, STEVEN GAUTHIER can be reached at (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ALVIN L LEE/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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