DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see remarks, filed 05/22/2026, with respect to the rejection(s) of claims under 35 USC 102 and/or 103 have been fully considered and are persuasive amendments of “the second semiconductor subfin region extends above a topmost surface of the second dielectric layer” and “a top surface of the semiconductor fin is higher than a top surface of a topmost nanoribbon of the plurality of semiconductor nanoribbons” overcome the prior art rejections. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made incorporating US 20220223720 A1 Yang and “US 20210375683 A1” Lin et al.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “a top surface of the semiconductor fin is higher than a top surface of a topmost nanoribbon of the plurality of semiconductor nanoribbons” of claim 15 and dependent claims must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Although support for this limitation is provide within paragraph [0048], only the embodiment of “top surface of the topmost nanoribbon 224 is substantially coplanar with a top surface of fin 213” [paragraph 0048] appear to be illustrated within the figures.
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Instant application Fig. 1 A: annotated to highlight the coplanar surfaces
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Instant application Fig. 2k: annotated to highlight the coplanar surfaces
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-8, 15-18, 20-21 and 23 are rejected under 35 U.S.C. 103as being obvious over US 20210225839 A1 Lin et al hereafter “Lin” and in further view of US 20220223720 A1 Yang et al hereafter “Yang” and “US 20210375683 A1” Lin et al hereafter “Lin S”.
Claim 1 Lin teaches an integrated circuit comprising:
a first semiconductor device (206c Fig. 18 and fig. 3) having a semiconductor fin (212c Fig. 18 and fig. 3) extending in a first direction (Y Fig. 18 and fig. 3) from a first source region (sufficiently illustrated Fig 5B 240 -Y) to a first drain region (sufficiently illustrated Fig 5B 240 +Y), and a first gate structure (comprising 272 and 250C of region 204 fig. 18) extending in a second direction (X fig. 18) over the semiconductor fin, the first gate structure having a first gate dielectric structure (250C fig. 18) and a first gate electrode (272 of region 204 fig. 18) on the first gate dielectric structure; and
a second semiconductor device (comprising 206a and/or 206 b fig. 18 and fig. 3) having a plurality of semiconductor bodies (220 fig. 18) extending in the first direction (illustrated fig. 18 , fig. 3 and fig. 6A) from a second source region (sufficiently illustrated Fig 5A 240 -Y) to a second drain region (sufficiently illustrated Fig 5A 240 +Y), and a second gate structure (comprising 272 and 250a and/or 250b of region 202 fig. 18) extending in the second direction over the plurality of semiconductor bodies, the second gate structure having a second gate dielectric structure (250a and/or 250b fig. 18) and a second gate electrode (272 of region 202 fig. 18) on the second gate dielectric structure;
a first semiconductor subfin region (illustrated fig. 18, see annotation below ) under the semiconductor fin;
a first dielectric layer (210 in region 204 fig. 18) adjacent to the first semiconductor subfin region;
a second semiconductor subfin region (see annotation below) under the plurality of semiconductor bodies; and
a second dielectric layer (210 in region 202 fig. 18) adjacent to at least a portion of the second subfin region; and
wherein the first gate dielectric structure includes a first gate oxide layer [ 230 fig. 18 Paragraph 0024 “The interfacial layer 230 may include a dielectric material such as an oxide layer”] and the second gate dielectric structure includes a second gate oxide layer [ 252a and/or 252b fig. 18, Paragraph 0033 “The interfacial layers 252a and 252b may include a dielectric material such as an oxide layer”], wherein the first gate oxide layer is at least 2 nm thicker than the second gate oxide layer [paragraph 0033 discloses with sufficient specificity wherein the second gate oxide layer 252a and/or 252b have a range of thickness between 12 Å to 14 Å, while the first gate oxide layer has a thickness between 20 Å to about 50 Å, See MPEP 2131.03 II. ].
Lin does not teach the second dielectric layer having a greater thickness than the first dielectric layer; Nor the second semiconductor subfin region extends above a topmost surface of the second dielectric layer
Yang teaches a first dielectric layer (IM2 fig. 1-2) adjacent to a first semiconductor subfin region (F2 fig. 1-2) ; a second semiconductor subfin region (IM1 fig. 1-2 ) under a second semiconductor subfin region (F1 fig. 1-2); the second dielectric layer having a greater thickness than the first dielectric layer [sufficiently illustrated fig. 2 IM1 is thicker then IM2 by H]
It would have been obvious to one of ordinary skill in the art before the effect filing date of the claimed invention to change the relative size of the second dielectric layer Lin teaches in further view of Yang such that “the second dielectric layer having a greater thickness than the first dielectric layer” to increase the effective insulation between second semiconductor device and adjacent device and/or to prevent shorting and/or decrease parasitic capacitance [sufficiently disclosed Yang paragraph 0003 “SiGe bridge may occur, causing short circuit problems” in view of “It is one object of the present invention to provide an improved semiconductor structure and its manufacturing method to solve the above-mentioned shortcomings or deficiencies of the prior art” paragraph 0004 wherein the improved semiconductor structure includes “the second isolation trench has a step height” Paragraph 0005], and/or to improve the operating efficiency [Paragraph 0002 Yang].
In addition, changes in relative size and/or proportion are prima facie type obviousness [See MPEP 2144.04 IV. A,].
Lin S. teaches a second semiconductor subfin region (105 of 130 and/or 140 fig. 11A) extends above a topmost surface (top most surface of 401 fig. 11A) of an isolation region (401 fig. 11A). In addition, Lin S. teaches explicitly teaches measurements related to the top most surface of the isolation region’s position [H1 fig. 11A].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Lin in view of Yang in further view of Lin S. such that “the second semiconductor subfin region extends above a topmost surface of the second dielectric layer”.
A person of ordinary skill in the art would have been motivated to make this modification to prevent high leakage currents, improve efficiency of device performance of the multichannel device, prevent operating voltage that are too high and allow for operating voltage that is not to low [Paragraph 0132 Lin S.]
In addition, combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case combining similar multichannel semiconductor devices for the purpose of forming circuit components and elements thereon is prima facie type obviousness.
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Annotated fig. 18: highlighting the subfin regions
Claim 2 Lin in view of Yang and Lin S. teaches as shown above the integrated circuit of claim 1, wherein the first gate dielectric structure includes a first layer of high-k material [254c fig. 18, sufficiently Disclosed Paragraph 0032 “high-k”] and the second gate dielectric structure includes a second layer of high-k material [254a and/or 254 b fig. 18, sufficiently Disclosed Paragraph 0032 “high-k”].
Claim 3 Lin in view of Yang and Lin S. teaches as shown above the integrated circuit of claim 2, wherein the first layer of high-k material and the second layer of high-k material each have substantially the same thickness [disclosed with sufficient specificity in paragraph 0032, “the high-k dielectric layers 254a, 254b, 254c (collectively, high-k dielectric layer 254)” and Paragraph 0034 “the high-k dielectric layer 254 has a thickness ranging from about 15 Å to about 30 Å”].
Claim 4 Lin in view of Yang and Lin S. teaches as shown above the integrated circuit of claim 2, wherein the first layer of high-k material and the second layer of high-k material each comprise hafnium and oxygen [disclosed with sufficient specificity in paragraph 0032 “the high-k dielectric layers 254a, 254b, 254c (collectively, high-k dielectric layer 254)” and Paragraph 0034 “The high-k dielectric layer 254 may include a metal oxide... HfZrO, HfLaO, HfTaO, HfTiO… a metal silicate… HfSiO”].
Claim 5 Lin in view of Yang and Lin S. teaches as shown above the integrated circuit of claim 1, wherein a topmost surface of the semiconductor fin is substantially coplanar with a topmost surface of a topmost semiconductor body of the plurality of semiconductor bodies [sufficiently illustrated fig. 18, see annotation below].
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Annotated fig. 18: highlighting the coplanar plane of claim 5
Claim 7 Lin in view of Yang and Lin S. teach as shown above the integrated circuit of claim 1, further comprising a substrate (208 fig. 18) wherein the semiconductor fin is part of the substrate and the plurality of semiconductor bodies are over the substrate [illustrated fig. 18].
Claim 8 Lin in view of Yang and Lin S. teaches as shown above a printed circuit board comprising the integrated circuit of claim 1 [illustrated fig. 1A Sufficiently disclosed paragraph 0018 “An I/O area refers to a device area that interfaces between a core device area and external/peripheral circuitry, such as the circuit on the printed circuit board (PCB) on which the semiconductor device 200 is mounted” ].
Claim 15 Lin teaches an integrated circuit comprising:
a substrate (208 fig. 18) including a first semiconductor subfin region [see annotation below] and a second semiconductor subfin region [see annotation below];
a first semiconductor device (206c fig. 18) having a semiconductor fin (212c fig. 18) above the first semiconductor subfin region and extending in a first direction (Y fig. 18, fig. 3 and fig. 5b) between a first source region (sufficiently disclosed fig. 5b 240 -Y) and a first drain region (sufficiently disclosed fig. 5b 240 +Y), and a first gate structure (comprising 272 in region 204 and 250c fig. 18) extending in a second direction (X fig. 18) over the semiconductor fin, the first gate structure having a first gate dielectric structure (250c fig. 18) and a first gate electrode (272 in region 204 fig. 18) on the first gate dielectric structure;
a second semiconductor device (206a and/or 206b fig. 18) having a plurality of semiconductor nanoribbons (220 fig. 18) above the second semiconductor subfin region and extending in the first direction between a second source region (sufficiently disclosed fig. 5A 240 -Y) and a second drain region (sufficiently disclosed fig. 5A 240 +Y) , and a second gate structure (comprising 272 in region 202 and 250a and/or 250b fig. 18) extending in the second direction over the plurality of semiconductor nanoribbons, the second gate structure having a second gate dielectric structure (250a and/or 250b fig. 18) and a second gate electrode (272 in region 202) on the second gate dielectric structure;
a first dielectric layer (210 in region 204 fig. 18) adjacent to the first semiconductor subfin region [sufficiently illustrated fig. 18], and
a second dielectric layer (210 in region 202 fig. 18) adjacent to at least a portion of the second semiconductor subfin region [sufficiently illustrated fig. 18],
Lin does not teach the second dielectric layer having a greater thickness than the first dielectric layer; a top surface of the semiconductor fin is higher than a top surface of a topmost nanoribbon of the plurality of semiconductor nanoribbons
Yang teaches a first dielectric layer (IM2 fig. 1-2) adjacent to a first semiconductor subfin region (F2 fig. 1-2) ; a second semiconductor subfin region (IM1 fig. 1-2 ) under a second semiconductor subfin region (F1 fig. 1-2); the second dielectric layer having a greater thickness than the first dielectric layer [sufficiently illustrated fig. 2 IM1 is thicker then IM2 by H]
It would have been obvious to one of ordinary skill in the art before the effect filing date of the claimed invention to change the relative size of the second dielectric layer Lin teaches in further view of Yang such that “the second dielectric layer having a greater thickness than the first dielectric layer” to increase the effective insulation between second semiconductor device and adjacent device and/or to prevent shorting and/or decrease parasitic capacitance [sufficiently disclosed Yang paragraph 0003 “SiGe bridge may occur, causing short circuit problems” in view of “It is one object of the present invention to provide an improved semiconductor structure and its manufacturing method to solve the above-mentioned shortcomings or deficiencies of the prior art” paragraph 0004 wherein the improved semiconductor structure includes “the second isolation trench has a step height” Paragraph 0005], and/or to improve the operating efficiency [Paragraph 0002 Yang].
In addition, changes in relative size and/or proportion are prima facie type obviousness [See MPEP 2144.04 IV. A,].
Lin S. teaches a top surface of a semiconductor fin (top surface of 803 fig. 11A) is higher than a top surface of a topmost nanoribbon of a plurality of semiconductor nanoribbons (topmost surface of 601 fig. 11A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Lin in view of Yang in further view of Lin S. such that “a top surface of the semiconductor fin is higher than a top surface of a topmost nanoribbon of the plurality of semiconductor nanoribbons”.
A person of ordinary skill in the art would have been motivated to make this modification to prevent high leakage currents, improve efficiency of device performance of the multichannel device, prevent operating voltage that are too high and allow for operating voltage that is not too low [Paragraph 0132 Lin S.]
In addition, combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case combining similar multichannel semiconductor devices for the purpose of forming circuit components and elements thereon is prima facie type obviousness.
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Annotated fig. 18: highlighting the subfin regions of claim 15
Claim 16 modified Lin in view of Yang and Lin S. teaches as shown above the integrated circuit of claim 15, wherein the first gate dielectric structure includes a first layer of high-k material and the second gate dielectric structure includes a second layer of high-k material [disclosed with sufficient specificity in paragraph 0032 “the high-k dielectric layers 254a, 254b, 254c (collectively, high-k dielectric layer 254)” and Paragraph 0034 “The high-k dielectric layer 254 may include a metal oxide... HfZrO, HfLaO, HfTaO, HfTiO… a metal silicate… HfSiO”].
Claim 17 modified Lin in view of Yang and Lin S. teaches as shown above the integrated circuit of claim 16, wherein the first layer of high-k material and the second layer of high-k material each have substantially the same thickness [disclosed with sufficient specificity in paragraph 0032, “the high-k dielectric layers 254a, 254b, 254c (collectively, high-k dielectric layer 254)” and Paragraph 0034 “the high-k dielectric layer 254 has a thickness ranging from about 15 Å to about 30 Å”].
Claim 18 modified Lin in view of Yang and Lin S. teaches as shown above the integrated circuit of claim 16, wherein the first layer of high-k material and the second layer of high-k material each comprise hafnium and oxygen [disclosed with sufficient specificity in paragraph 0032 “the high-k dielectric layers 254a, 254b, 254c (collectively, high-k dielectric layer 254)” and Paragraph 0034 “The high-k dielectric layer 254 may include a metal oxide... HfZrO, HfLaO, HfTaO, HfTiO… a metal silicate… HfSiO”].
Claim 20 modified Lin in view of Yang and Lin S. teaches as shown above the integrated circuit of claim 15, wherein the first gate dielectric structure includes a first gate oxide layer (230 fig. 18, Paragraph 0024 “The interfacial layer 230 may include a dielectric material such as an oxide layer (e.g., SiO.sub.2)”) and the second gate dielectric structure includes a second gate oxide layer (252a and/or 252b fig. 18, Paragraph 0033 “The interfacial layers 252a and 252b may include a dielectric material such as an oxide layer (e.g., SiO.sub.2)”), wherein the first gate oxide layer is at least 2 nm thicker than the second gate oxide layer [paragraph 0033 discloses with sufficient specificity wherein the second gate oxide layer 252a and/or 252b have a range of thickness between 12 Å to 14 Å, while the first gate oxide layer has a thickness between 20 Å to about 50 Å, See MPEP 2131.03 II. ].
Claim 21 Lin in view of Yang and Lin S. teaches as shown above the integrated circuit of claim 1.
Lin does not teach a top surface of the semiconductor fin is higher than a top surface of a topmost semiconductor body of the plurality of semiconductor bodies.
Lin S. teaches a top surface of a semiconductor fin (top surface of 803 fig. 11A) is higher than a top surface of a topmost nanoribbon of a plurality of semiconductor nanoribbons (topmost surface of 601 fig. 11A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Lin in view of Yang in further view of Lin S. such that “a top surface of the semiconductor fin is higher than a top surface of a topmost nanoribbon of the plurality of semiconductor nanoribbons”.
A person of ordinary skill in the art would have been motivated to make this modification to prevent high leakage currents, improve efficiency of device performance of the multichannel device, prevent operating voltage that are too high and allow for operating voltage that is not too low [Paragraph 0132 Lin S.]
In addition, combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case combining similar multichannel semiconductor devices for the purpose of forming circuit components and elements thereon is prima facie type obviousness.
Claim 23 Lin in view of Yang and Lin S. teaches as shown above the integrated circuit of claim 15,
Lin does not teach wherein the second semiconductor subfin region extends above a topmost surface of the second dielectric layer.
Lin S. teaches a second semiconductor subfin region (105 of 130 and/or 140 fig. 11A) extends above a topmost surface (top most surface of 401 fig. 11A) of an isolation region (401 fig. 11A). In addition, Lin S. teaches explicitly teaches measurements related to the top most surface of the isolation region’s position [H1 fig. 11A].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Lin in view of Yang and Lin S. such that “the second semiconductor subfin region extends above a topmost surface of the second dielectric layer”.
A person of ordinary skill in the art would have been motivated to make this modification to prevent high leakage currents, improve efficiency of device performance of the multichannel device, prevent operating voltage that are too high and allow for operating voltage that is not to low [Paragraph 0132 Lin S.]
In addition, combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case combining similar multichannel semiconductor devices for the purpose of forming circuit components and elements thereon is prima facie type obviousness.
Claims 9-14 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Lin as applied to the claims above, and further in view of US 10553495 B2 Cheng et al hereafter “Cheng”.
Claim 9 Lin teaches an electronic device, comprising:
a substrate (208 fig. 18 and fig. 3);
a first semiconductor device (206c fig. 18 and fig. 3) on the substrate and having a semiconductor fin (212c fig. 18, fig. 3 and fig. 5B) extending in a first direction (Y fig. fig. 18, fig. 3 and fig. 5B) between a first source region (sufficiently illustrated fig. 5B 240 -Y) and a first drain region ( sufficiently illustrated fig. 5B 240 +Y), and a first gate structure (comprising 272 in region 204 and 250c fig. 18) extending in a second direction (X fig. 18) over the semiconductor fin, the first gate structure having a first gate dielectric structure (250c fig. 18) and a first gate electrode (272 in region 204 fig. 18) on the first gate dielectric structure; and
a second semiconductor device (206a and/or 206b fig. 18, fig. 3 and fig. 5A) on the substrate and having a plurality of semiconductor nanoribbons (220 fig. 18, fig. 3 and fig. 5A) extending in the first direction between a second source region (sufficiently disclosed 240 -Y fig. 5A) and a second drain region (sufficiently disclosed 240 +Y fig. 5A), and a second gate structure (272 in region 202 and 250a and/or 250b fig. 18) extending in the second direction over the plurality of semiconductor nanoribbons, the second gate structure having a second gate dielectric structure (250a and/or 250b fig. 18) and a second gate electrode (272 in region 202 fig. 18) on the second gate dielectric structure;
wherein the semiconductor fin includes a first semiconductor subfin [see annotation below, sufficiently illustrated fig. 18] having a first dielectric layer [210 adjacent to the first semiconductor subfin, sufficiently illustrated fig. 18] adjacent to the first semiconductor subfin;
wherein the plurality of semiconductor nanoribbons includes a second semiconductor subfin [see annotation below, sufficiently illustrated fig. 18] having a second dielectric layer [210 adjacent to the second semiconductor subfin, sufficiently illustrated fig. 18] adjacent to at least a portion of the second semiconductor subfin [sufficiently illustrated fig. 18], and
wherein the first gate dielectric structure includes a first gate oxide layer (230 fig. 18, Paragraph 0024, “the interfacial layer 230 may include a dielectric material such as an oxide layer”) and the second gate dielectric structure includes a second gate oxide layer (252a and/or 252b fig. 18, Paragraph 0033 “The interfacial layers 252a and 252b may include a dielectric material such as an oxide layer”), wherein the first gate oxide layer is at least 2 nm thicker than the second gate oxide layer [paragraph 0033 discloses with sufficient specificity wherein the second gate oxide layer 252a and/or 252b have a range of thickness between 12 Å to 14 Å, while the first gate oxide layer has a thickness between 20 Å to about 50 Å, See MPEP 2131.03 II. ].
Lin does not explicitly teach a chip package comprising one or more dies, at least one of the one or more dies comprising the electronic device as shown above; nor the second dielectric layer having a greater thickness than the first dielectric layer;
wherein the second semiconductor subfin extends above a topmost surface of the second dielectric layer,
Yang teaches a first dielectric layer (IM2 fig. 1-2) adjacent to a first semiconductor subfin region (F2 fig. 1-2) ; a second semiconductor subfin region (IM1 fig. 1-2 ) under a second semiconductor subfin region (F1 fig. 1-2); the second dielectric layer having a greater thickness than the first dielectric layer [sufficiently illustrated fig. 2 IM1 is thicker then IM2 by H]
It would have been obvious to one of ordinary skill in the art before the effect filing date of the claimed invention to change the relative size of the second dielectric layer Lin teaches in further view of Yang such that “the second dielectric layer having a greater thickness than the first dielectric layer” to increase the effective insulation between second semiconductor device and adjacent device and/or to prevent shorting and/or decrease parasitic capacitance [sufficiently disclosed Yang paragraph 0003 “SiGe bridge may occur, causing short circuit problems” in view of “It is one object of the present invention to provide an improved semiconductor structure and its manufacturing method to solve the above-mentioned shortcomings or deficiencies of the prior art” paragraph 0004 wherein the improved semiconductor structure includes “the second isolation trench has a step height” Paragraph 0005], and/or to improve the operating efficiency [Paragraph 0002 Yang].
In addition, changes in relative size and/or proportion are prima facie type obviousness [See MPEP 2144.04 IV. A,].
Lin S. teaches a second semiconductor subfin region (105 of 130 and/or 140 fig. 11A) extends above a topmost surface (top most surface of 401 fig. 11A) of an isolation region (401 fig. 11A). In addition, Lin S. teaches explicitly teaches measurements related to the top most surface of the isolation region’s position [H1 fig. 11A].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Lin in view of Yang in further view of Lin S. such that “the second semiconductor subfin region extends above a topmost surface of the second dielectric layer”.
A person of ordinary skill in the art would have been motivated to make this modification to prevent high leakage currents, improve efficiency of device performance of the multichannel device, prevent operating voltage that are too high and allow for operating voltage that is not to low [Paragraph 0132 Lin S.]
In addition, combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case combining similar multichannel semiconductor devices for the purpose of forming circuit components and elements thereon is prima facie type obviousness.
Cheng teaches a multichip package comprising a plurality of chips in bare die and/or packaged form comprising an integrated circuit chip [sufficiently disclosed Column 9 lines 18-35].
It would have been obvious to one of ordinary skill in the art to substitute integrated circuit and/or the chip and/or die of Cheng with the Integrated circuit and/or chip and/or die as taught by Lin in view of Yang and Lin S. such that “a chip package comprising one or more dies, at least one of the one or more dies” comprising the electronic device as shown above substituting equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06] in this case the purpose being a logic circuit and/or integrated circuit.
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Annotated fig. 18: highlighting the subfin regions
Claim 10 Lin in view of Yang, Lin S. and Cheng teaches as shown above the electronic device of claim 9, wherein the first gate dielectric structure includes a first layer of high-k material (254c fig. 18, Paragraph 0032 “high-k”) and the second gate dielectric structure includes a second layer of high-k material. (254a and/or 254b fig. 18, Paragraph 0032 “high-k”)
Claim 11 Lin in view of Yang, Lin S. and Cheng teaches as shown above the electronic device of claim 10, wherein the first layer of high-k material and the second layer of high-k material each comprise hafnium and oxygen [disclosed with sufficient specificity in paragraph 0032 “the high-k dielectric layers 254a, 254b, 254c (collectively, high-k dielectric layer 254)” and Paragraph 0034 “The high-k dielectric layer 254 may include a metal oxide... HfZrO, HfLaO, HfTaO, HfTiO… a metal silicate… HfSiO”].
Claim 12 Lin in view of Yang, Lin S. and Cheng teaches as shown above the electronic device of claim 9, where a top surface of the semiconductor fin is substantially coplanar with a top surface of a topmost nanoribbon of the plurality of semiconductor nanoribbons [sufficiently illustrated fig. 18, see annotation below].
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Annotated fig. 18: highlighting the coplanar plane of claim 12
Claim 14 Lin in view of Yang, Lin S. and Cheng teaches as shown above the electronic device of claim 9, wherein the semiconductor fin is part of the substrate and the plurality of semiconductor nanoribbons are over the substrate [illustrated fig. 18].
Claim 22 Lin in view of Yang, Lin S. Cheng the electronic device of claim 9.
Lin does not teach a top surface of the semiconductor fin is higher than a top surface of a topmost nanoribbon of the plurality of semiconductor nanoribbons.
Lin S. teaches a top surface of a semiconductor fin (top surface of 803 fig. 11A) is higher than a top surface of a topmost nanoribbon of a plurality of semiconductor nanoribbons (topmost surface of 601 fig. 11A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Lin in view of Yang in further view of Lin S. such that “a top surface of the semiconductor fin is higher than a top surface of a topmost nanoribbon of the plurality of semiconductor nanoribbons”.
A person of ordinary skill in the art would have been motivated to make this modification to prevent high leakage currents, improve efficiency of device performance of the multichannel device, prevent operating voltage that are too high and allow for operating voltage that is not too low [Paragraph 0132 Lin S.]
In addition, combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case combining similar multichannel semiconductor devices for the purpose of forming circuit components and elements thereon is prima facie type obviousness.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/WCT/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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