DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 and 7-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20210225839 A1 Lin et al hereafter “Lin”.
Claim 1 Lin teaches an integrated circuit comprising:
a first semiconductor device (206c Fig. 18 and fig. 3) having a semiconductor fin (212c Fig. 18 and fig. 3) extending in a first direction (Y Fig. 18 and fig. 3) from a first source region (sufficiently illustrated Fig 5B 240 -Y) to a first drain region (sufficiently illustrated Fig 5B 240 +Y), and a first gate structure (comprising 272 and 250C of region 204 fig. 18) extending in a second direction (X fig. 18) over the semiconductor fin, the first gate structure having a first gate dielectric structure (250C fig. 18) and a first gate electrode (272 of region 204 fig. 18) on the first gate dielectric structure; and
a second semiconductor device (comprising 206a and/or 206 b fig. 18 and fig. 3) having a plurality of semiconductor bodies (220 fig. 18) extending in the first direction (illustrated fig. 18 , fig. 3 and fig. 6A) from a second source region (sufficiently illustrated Fig 5A 240 -Y) to a second drain region (sufficiently illustrated Fig 5A 240 +Y), and a second gate structure (comprising 272 and 250a and/or 250b of region 202 fig. 18) extending in the second direction over the plurality of semiconductor bodies, the second gate structure having a second gate dielectric structure (250a and/or 250b fig. 18) and a second gate electrode (272 of region 202 fig. 18) on the second gate dielectric structure;
wherein the first gate dielectric structure includes a first gate oxide layer [ 230 fig. 18 Paragraph 0024 “The interfacial layer 230 may include a dielectric material such as an oxide layer”] and the second gate dielectric structure includes a second gate oxide layer [ 252a and/or 252b fig. 18, Paragraph 0033 “The interfacial layers 252a and 252b may include a dielectric material such as an oxide layer”], wherein the first gate oxide layer is at least 2 nm thicker than the second gate oxide layer [paragraph 0033 discloses with sufficient specificity wherein the second gate oxide layer 252a and/or 252b have a range of thickness between 12 Å to 14 Å, while the first gate oxide layer has a thickness between 20 Å to about 50 Å, See MPEP 2131.03 II. ].
Claim 2 Lin teaches as shown above the integrated circuit of claim 1, wherein the first gate dielectric structure includes a first layer of high-k material [254c fig. 18, sufficiently Disclosed Paragraph 0032 “high-k”] and the second gate dielectric structure includes a second layer of high-k material [254a and/or 254 b fig. 18, sufficiently Disclosed Paragraph 0032 “high-k”].
Claim 3 Lin teaches as shown above the integrated circuit of claim 2, wherein the first layer of high-k material and the second layer of high-k material each have substantially the same thickness [disclosed with sufficient specificity in paragraph 0032, “the high-k dielectric layers 254a, 254b, 254c (collectively, high-k dielectric layer 254)” and Paragraph 0034 “the high-k dielectric layer 254 has a thickness ranging from about 15 Å to about 30 Å”].
Claim 4 Lin teaches as shown above the integrated circuit of claim 2, wherein the first layer of high-k material and the second layer of high-k material each comprise hafnium and oxygen [disclosed with sufficient specificity in paragraph 0032 “the high-k dielectric layers 254a, 254b, 254c (collectively, high-k dielectric layer 254)” and Paragraph 0034 “The high-k dielectric layer 254 may include a metal oxide... HfZrO, HfLaO, HfTaO, HfTiO… a metal silicate… HfSiO”].
Claim 5 Lin teaches as shown above the integrated circuit of claim 1, where a topmost surface of the semiconductor fin is substantially coplanar with a topmost surface of a topmost semiconductor body of the plurality of semiconductor bodies [sufficiently illustrated fig. 18, see annotation below].
PNG
media_image1.png
633
824
media_image1.png
Greyscale
Annotated fig. 18: highlighting the coplanar plane of claim 5
Claim 7 Lin teach as shown above the integrated circuit of claim 1, further comprising a substrate (208 fig. 18) wherein the semiconductor fin is part of the substrate and the plurality of semiconductor bodies are over the substrate [illustrated fig. 18].
Claim 8 Lin teaches as shown above a printed circuit board comprising the integrated circuit of claim 1 [illustrated fig. 1A Sufficiently disclosed paragraph 0018 “An I/O area refers to a device area that interfaces between a core device area and external/peripheral circuitry, such as the circuit on the printed circuit board (PCB) on which the semiconductor device 200 is mounted” ].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Lin as applied to the claims above.
Claim 6 Lin teaches the integrated circuit of claim 1, comprising:
a first subfin region (illustrated fig. 18, see annotation below ) under the semiconductor fin;
a first dielectric layer (210 in region 204 fig. 18) adjacent to the first subfin region;
a second subfin region (see annotation below) under the plurality of semiconductor bodies; and
a second dielectric layer (210 in region 202 fig. 18) adjacent to at least a portion of the second subfin region.
Lin does not teach the second dielectric layer having a greater thickness than the first dielectric layer.
It would have been obvious to one of ordinary skill in the art before the effect filing date of the claimed invention to change the relative size of the second dielectric layer Lin teaches such that “the second dielectric layer having a greater thickness than the first dielectric layer” to increase the effective insulation between second semiconductor device and adjacent device and/or to prevent shorting and/or decrease parasitic capacitance and/or changes in relative size and/or proportion is prima facie type obviousness [See MPEP 2144.04 IV. A]
PNG
media_image2.png
633
824
media_image2.png
Greyscale
Annotated fig. 18: highlighting the subfin regions of claim 6
Claims 9-14 are rejected under 35 U.S.C. 103 as being unpatentable over Lin as applied to the claims above, and further in view of US 10553495 B2 Cheng et al hereafter “Cheng”.
Claim 9 Lin teaches an electronic device, comprising:
a substrate (208 fig. 18 and fig. 3);
a first semiconductor device (206c fig. 18 and fig. 3) on the substrate and having a semiconductor fin (212c fig. 18, fig. 3 and fig. 5B) extending in a first direction (Y fig. fig. 18, fig. 3 and fig. 5B) between a first source region (sufficiently illustrated fig. 5B 240 -Y) and a first drain region ( sufficiently illustrated fig. 5B 240 +Y), and a first gate structure (comprising 272 in region 204 and 250c fig. 18) extending in a second direction (X fig. 18) over the semiconductor fin, the first gate structure having a first gate dielectric structure (250c fig. 18) and a first gate electrode (272 in region 204 fig. 18) on the first gate dielectric structure; and
a second semiconductor device (206a and/or 206b fig. 18, fig. 3 and fig. 5A) on the substrate and having a plurality of semiconductor nanoribbons (220 fig. 18, fig. 3 and fig. 5A) extending in the first direction between a second source region (sufficiently disclosed 240 -Y fig. 5A) and a second drain region (sufficiently disclosed 240 +Y fig. 5A), and a second gate structure (272 in region 202 and 250a and/or 250b fig. 18) extending in the second direction over the plurality of semiconductor nanoribbons, the second gate structure having a second gate dielectric structure (250a and/or 250b fig. 18) and a second gate electrode (272 in region 202 fig. 18) on the second gate dielectric structure;
wherein the first gate dielectric structure includes a first gate oxide layer (230 fig. 18, Paragraph 0024, “the interfacial layer 230 may include a dielectric material such as an oxide layer”) and the second gate dielectric structure includes a second gate oxide layer (252a and/or 252b fig. 18, Paragraph 0033 “The interfacial layers 252a and 252b may include a dielectric material such as an oxide layer”), wherein the first gate oxide layer is at least 2 nm thicker than the second gate oxide layer [paragraph 0033 discloses with sufficient specificity wherein the second gate oxide layer 252a and/or 252b have a range of thickness between 12 Å to 14 Å, while the first gate oxide layer has a thickness between 20 Å to about 50 Å, See MPEP 2131.03 II. ].
Lin does not explicitly teach a chip package comprising one or more dies, at least one of the one or more dies comprising the electronic device as shown above.
Cheng teaches a multichip package comprising a plurality of chips in bare die and/or packaged form comprising an integrated circuit chip [sufficiently disclosed Column 9 lines 18-35].
It would have been obvious to one of ordinary skill in the art to substitute integrated circuit and/or the chip and/or die of Cheng with the Integrated circuit and/or chip and/or die as taught by Lin and that “a chip package comprising one or more dies, at least one of the one or more dies” comprising the electronic device as shown above substituting equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06] in this case the purpose being a logic circuit and/or integrated circuit.
Claim 10 Lin in view of Cheng teaches as shown above the electronic device of claim 9, wherein the first gate dielectric structure includes a first layer of high-k material (254c fig. 18, Paragraph 0032 “high-k”) and the second gate dielectric structure includes a second layer of high-k material. (254a and/or 254b fig. 18, Paragraph 0032 “high-k”)
Claim 11 Lin in view of Cheng teaches as shown above the electronic device of claim 10, wherein the first layer of high-k material and the second layer of high-k material each comprise hafnium and oxygen [disclosed with sufficient specificity in paragraph 0032 “the high-k dielectric layers 254a, 254b, 254c (collectively, high-k dielectric layer 254)” and Paragraph 0034 “The high-k dielectric layer 254 may include a metal oxide... HfZrO, HfLaO, HfTaO, HfTiO… a metal silicate… HfSiO”].
Claim 12 Lin in view of Cheng teaches as shown above the electronic device of claim 9, where a top surface of the semiconductor fin is substantially coplanar with a top surface of a topmost nanoribbon of the plurality of semiconductor nanoribbons [sufficiently illustrated fig. 18, see annotation below].
PNG
media_image1.png
633
824
media_image1.png
Greyscale
Annotated fig. 18: highlighting the coplanar plane of claim 12
Claim 13 Lin in view of Cheng teaches as shown above the electronic device of claim 9, wherein the semiconductor fin includes a first subfin region [illustrated fig. 18, see annotation below] having a first dielectric layer (210 in region 204 fig. 18) adjacent to the first subfin region and the plurality of semiconductor nanoribbons includes a second subfin region [illustrated fig. 18, see annotation below] having a second dielectric layer (210 in region 202 fig. 18) adjacent to at least a portion of the second subfin region.
Lin does not teach the second dielectric layer having a greater thickness than the first dielectric layer.
It would have been obvious to one of ordinary skill in the art before the effect filing date of the claimed invention to change the relative size of the second dielectric layer Lin teaches such that “the second dielectric layer having a greater thickness than the first dielectric layer” to increase the effective insulation between second semiconductor device and adjacent device and/or to prevent shorting and/or decrease parasitic capacitance and/or changes in relative size and/or proportion is prima facie type obviousness [See MPEP 2144.04 IV. A]
PNG
media_image2.png
633
824
media_image2.png
Greyscale
Annotated fig. 18: highlighting the subfin regions of claim 13
Claim 14 Lin in view of Cheng teaches as shown above the electronic device of claim 9, wherein the semiconductor fin is part of the substrate and the plurality of semiconductor nanoribbons are over the substrate [illustrated fig. 18].
Claims 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin as applied to the claims above.
Claim 15 Lin teaches an integrated circuit comprising:
a substrate (208 fig. 18) including a first subfin region [see annotation below] and a second subfin region [see annotation below];
a first semiconductor device (206c fig. 18) having a semiconductor fin (212c fig. 18) above the first subfin region and extending in a first direction (Y fig. 18, fig. 3 and fig. 5b) between a first source region (sufficiently disclosed fig. 5b 240 -Y) and a first drain region (sufficiently disclosed fig. 5b 240 +Y), and a first gate structure (comprising 272 in region 204 and 250c fig. 18) extending in a second direction (X fig. 18) over the semiconductor fin, the first gate structure having a first gate dielectric structure (250c fig. 18) and a first gate electrode (272 in region 204 fig. 18) on the first gate dielectric structure;
a second semiconductor device (206a and/or 206b fig. 18) having a plurality of semiconductor nanoribbons (220 fig. 18) above the second subfin region and extending in the first direction between a second source region (sufficiently disclosed fig. 5A 240 -Y) and a second drain region (sufficiently disclosed fig. 5A 240 +Y) , and a second gate structure (comprising 272 in region 202 and 250a and/or 250b fig. 18) extending in the second direction over the plurality of semiconductor nanoribbons, the second gate structure having a second gate dielectric structure (250a and/or 250b fig. 18) and a second gate electrode (272 in region 202) on the second gate dielectric structure;
a first dielectric layer (210 in region 204 fig. 18) adjacent to the first subfin region [sufficiently illustrated fig. 18], and
a second dielectric layer (210 in region 202 fig. 18) adjacent to at least a portion of the second subfin region [sufficiently illustrated fig. 18],
Lin does not teach the second dielectric layer having a greater thickness than the first dielectric layer.
It would have been obvious to one of ordinary skill in the art before the effect filing date of the claimed invention to change the relative size of the second dielectric layer Lin teaches such that “the second dielectric layer having a greater thickness than the first dielectric layer” to increase the effective insulation between second semiconductor device and adjacent device and/or to prevent shorting and/or decrease parasitic capacitance and/or changes in relative size and/or proportion is prima facie type obviousness [See MPEP 2144.04 IV. A]
PNG
media_image2.png
633
824
media_image2.png
Greyscale
Annotated fig. 18: highlighting the subfin regions of claim 15
Claim 16 modified Lin teaches as shown above the integrated circuit of claim 15, wherein the first gate dielectric structure includes a first layer of high-k material and the second gate dielectric structure includes a second layer of high-k material [disclosed with sufficient specificity in paragraph 0032 “the high-k dielectric layers 254a, 254b, 254c (collectively, high-k dielectric layer 254)” and Paragraph 0034 “The high-k dielectric layer 254 may include a metal oxide... HfZrO, HfLaO, HfTaO, HfTiO… a metal silicate… HfSiO”].
Claim 17 modified Lin teaches as shown above the integrated circuit of claim 16, wherein the first layer of high-k material and the second layer of high-k material each have substantially the same thickness [disclosed with sufficient specificity in paragraph 0032, “the high-k dielectric layers 254a, 254b, 254c (collectively, high-k dielectric layer 254)” and Paragraph 0034 “the high-k dielectric layer 254 has a thickness ranging from about 15 Å to about 30 Å”].
Claim 18 modified Lin teaches as shown above the integrated circuit of claim 16, wherein the first layer of high-k material and the second layer of high-k material each comprise hafnium and oxygen [disclosed with sufficient specificity in paragraph 0032 “the high-k dielectric layers 254a, 254b, 254c (collectively, high-k dielectric layer 254)” and Paragraph 0034 “The high-k dielectric layer 254 may include a metal oxide... HfZrO, HfLaO, HfTaO, HfTiO… a metal silicate… HfSiO”].
Claim 19 modified Lin as shown above teaches the integrated circuit of claim 15, where a top surface of the semiconductor fin is substantially coplanar with a top surface of a topmost nanoribbon of the plurality of semiconductor nanoribbons [sufficiently illustrated fig. 18, see annotation below].
PNG
media_image1.png
633
824
media_image1.png
Greyscale
Annotated fig. 18: highlighting the coplanar plane of claim 12
Claim 20 modified Lin teaches as shown above the integrated circuit of claim 15, wherein the first gate dielectric structure includes a first gate oxide layer (230 fig. 18, Paragraph 0024 “The interfacial layer 230 may include a dielectric material such as an oxide layer (e.g., SiO.sub.2)”) and the second gate dielectric structure includes a second gate oxide layer (252a and/or 252b fig. 18, Paragraph 0033 “The interfacial layers 252a and 252b may include a dielectric material such as an oxide layer (e.g., SiO.sub.2)”), wherein the first gate oxide layer is at least 2 nm thicker than the second gate oxide layer [paragraph 0033 discloses with sufficient specificity wherein the second gate oxide layer 252a and/or 252b have a range of thickness between 12 Å to 14 Å, while the first gate oxide layer has a thickness between 20 Å to about 50 Å, See MPEP 2131.03 II. ].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to William C Trice whose telephone number is (703)756-1875. The examiner can normally be reached M-F 8:30am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/WCT/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893