Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the Applicant Election filled on 03/05/2026. Currently, claims 1-13 and 21-27 are pending in the application. Claims 14-20 have been withdrawn and cancelled from consideration. Claims 21-27 have been added new.
Election/Restrictions
Applicant's election with traverse of group I and Species IA, claims 1-13 and 21-27, in the reply filed on 03/05/2026 is acknowledged, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6, 21-14 and 26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Colombeau et al (US 20210119021 A1).
Regarding claim 1, Figures 2 and 11A-11F of Colombeau disclose an integrated circuit comprising:
a first semiconductor device (with smaller width gate region of 200, Figure 2/11E/F) having a first semiconductor region (112, [0022]) extending in a first direction (X direction, please also see Figure 2) between a first source region (320, on left side of narrow width gate 1330, Figure 11E, [0030]) and a first drain region (320, on right side of narrow width gate 1330, Figure 11E), and a first gate structure (1320+1330, right side one, not labeled) extending in a second direction (Z) over the first semiconductor region (112, [0022]), the first gate structure having a first width along the first direction (X direction); and
a second semiconductor device (with wider gate, Figure 2 and 11E/F) having a second semiconductor region (112, please see Figure 2) extending in the first direction (X) between a second source region (320, on left side of wider gate, Figure 11E) and a second drain region (320, on right side of wider gate, Figure 11E, [0030]), and a second gate structure (1330, left one in the Figure 2 or 11E/F) extending in the second direction (Z) over the second semiconductor region, the second gate structure having a second width along the first direction (X), where the second width is greater than the first width (Figure 11E/F, 1330 is wider on left side device);
wherein the first gate structure includes a first conductive layer (1320, [0045]), right one in Figure 11E/F) and a first conductive fill (1330, [0046]) on the first conductive layer, the first conductive layer extending above the first semiconductor region (112) to a first height, and the second gate structure includes a second conductive layer (1320, with wider gate) and a second conductive fill (1330 with wider gate, [0045]), left one in Figure 11E/F) on the second conductive layer, the second conductive layer extending above the second semiconductor region to a second height that is within 2 nm of the first height (equal based on the Figure 11).
Regarding claim 2, Figures 2 and 11A-11F of Colombeau disclose that the integrated circuit of claim 1, wherein the first semiconductor region comprises a plurality of first semiconductor nanoribbons and the second semiconductor region comprises a plurality of second semiconductor nanoribbons (112 comprising nanoribbon shaped, [0019]) .
Regarding claim 3, Figures 2 and 11A-11F of Colombeau disclose that the integrated circuit of claim 1, wherein the first gate structure includes a first gate dielectric around the first semiconductor region, and the second gate structure includes a second gate dielectric around the second semiconductor region (1310 with wider and narrow gate, Figure 11B, [0044]).
Regarding claim 4, Figures 2 and 11A-11F of Colombeau disclose that the integrated circuit of claim 3, wherein the first gate dielectric is directly between the first semiconductor region and the first conductive layer (1320), and the second gate dielectric is directly between the second semiconductor region and the second conductive layer (1310 is between 112 and 1320 in both wider and narrow gate, Figure 11, [0044]).
Regarding claim 6, Figures 2 and 11A-11F of Colombeau disclose that the integrated circuit of claim 1, wherein the second width is at least two times greater than the first width (gate width, [0060]).
Regarding claim 21, Figures 2 and 11A-11F of Colombeau disclose an integrated circuit comprising:
a first semiconductor device (right one with narrow gate region, Figure 2 or Figure 11E/F) having a first semiconductor region (112, [0022]) extending in a first direction (X) between a first source region (320, left one for narrow gate device, Figure 11, [0030]) and a first drain region (320, right one for narrow gate device, Figure 11), and a first gate structure (1320+1330, narrow one, Figure 11E/F) extending in a second direction (Z) over the first semiconductor region (112), the first gate structure including a first conductive layer (1320, [0046]) and a first conductive fill (1330, [0046]) on the first conductive layer; and
a second semiconductor device (right one with wider gate region, Figure 2 or Figure 11E/F) having a second semiconductor region (112, [0022]) extending in the first direction (X) between a second source region (320, left one for wider gate device, Figure 11) and a second drain region (320, left one for wider gate device, Figure 11), and a second gate structure (1320+1330, wider one, Figure 11E/F) extending in the second direction (Z direction) over the second semiconductor region, the second gate structure including a second conductive layer (1320, [0046]) and a second conductive fill (1330, [0046]) on the second conductive layer;
wherein the first conductive fill (1330) has a first portion over the first semiconductor region having a first width along the first direction, and a second portion over the first portion and having a second width along the first direction (X direction) greater than the first width, wherein the second conductive fill has a third portion over the second semiconductor region having a third width along the first direction, and a fourth portion over the third portion and having a fourth width along the first direction greater than the third width, and wherein the third width is greater than the first width, and the fourth width is greater than the second width (1330 in the wider and the narrow gate having total narrow width at the bottom portion in X direction due to the shape of the gate structure in the Figure 11E/F).
Regarding claim 22, Figures 2 and 11A-11F of Colombeau disclose that the integrated circuit of claim 21, wherein the first semiconductor region (112) comprises a plurality of first semiconductor nanoribbons and the second semiconductor region comprises a plurality of second semiconductor nanoribbons ([0019]).
Regarding claim 23, Figures 2 and 11A-11F of Colombeau disclose integrated circuit of claim 21, wherein the first gate structure includes a first gate dielectric around the first semiconductor region, and the second gate structure includes a second gate dielectric around the second semiconductor region (1310 with the narrow and wider gate structure, [0045]).
Regarding claim 24, Figures 2 and 11A-11F of Colombeau disclose integrated circuit of claim 23, wherein the first gate dielectric (1310) is directly between the first semiconductor region (112) and the first conductive layer (1320, narrow gate region), and the second gate dielectric is directly between the second semiconductor region and the second conductive layer (1320, wider gate region).
Regarding claim 26, Figures 2 and 11A-11F of Colombeau disclose integrated circuit of claim 21, wherein the third width is at least two times greater than the first width, and the fourth width is at least two times greater than the second width ([0060]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 7-13, 25 and 27 are rejected under 35 U.S.C. 103 as being obvious over Colombeau et al (US 20210119021 A1) in view of BOMBERGER et al (US 20200303502 A1).
Regarding claims 5 and 25, Figures 2 and 11A-11F of Colombeau do not explicitly teach that the integrated circuit of claim 1, wherein the first conductive layer (1320, narrow gate region) and the second conductive layer (1320, wider gate region) comprise titanium or tungsten. Or
The integrated circuit of claim 21, wherein the first conductive layer and the second conductive layer comprise titanium or tungsten.
However, BOMBERGER is a pertinent art which teaches a semiconductor device with gate-all-around transistor with nanowires channel, wherein the gate electrode is composed of a non-workfunction-setting fill material formed above a metal workfunction-setting layer. The gate electrode layer may consist of a P-type workfunction metal or an N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a conductive fill layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide ([0085]).
Thus, it would have been obvious to try by one of ordinary skill in the art before the effective filing date of the claimed invention to use the first conductive layer (1320, narrow gate region) and the second conductive layer (1320, wider gate region) comprise titanium or tungsten according to the teaching of BOMBERGER in order to have proper work-function in the device of Colombeau, since it has been held that choosing from a finite number of identified, predictable solutions such as the claimed materials used to form the device, with a reasonable expectation of success is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007).
Regarding claims 7 and 27, Figures 2 and 11A-11F of Colombeau does not explicitly teach a printed circuit board comprising the integrated circuit of claim 1. Or
A printed circuit board comprising the integrated circuit of claim 21.
However, BOMBERGER is a pertinent art which teaches a semiconductor device with gate-all-around transistor with nanowires channel, wherein Figure 10 teaches a printed circuit board comprising an integrated circuit comprising the semiconductor device with gate-all-around transistor with nanowires channel in order to form an motherboard of a computing device ([0135]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to use the integrated circuit of claim 1 in a printed circuit board according to the teaching of BOMBERGER in order to make a computing device.
Regarding claim 8, Figures 2 and 11A-11F of Colombeau disclose an electronic device, comprising:
a first semiconductor device having a first semiconductor region (112, right one with narrow gate region, Figure 2 or Figure 11E/F, [0022]) extending in a first direction (X direction) between a first source region (320, left one for narrow gate device, Figure 11, [0030]) and a first drain region (320, right one for narrow gate device, Figure 11), and a first gate structure (1320+1330, narrow one, Figure 11E/F) extending in a second direction (Z direction) over the first semiconductor region, the first gate structure having a first width along the first direction (X direction); and
a second semiconductor device having a second semiconductor region (112, right one with wider gate region, Figure 2 or Figure 11E/F, [0022]) extending in the first direction (X direction) between a second source region (320, left one for wider gate device, Figure 11) and a second drain region (320, right one for wider gate device, Figure 11), and a second gate structure (1320+1330, wider one, Figure 11E/F, [0046]) extending in the second direction (Z direction) over the second semiconductor region, the second gate structure having a second width along the first direction, where the second width is greater than the first width (gate is narrow in the left side than the right side device, Figure 2/11);
wherein the first gate structure includes a first conductive layer (1320 at narrow gate, Figure 11 [0046]) and a first conductive fill (1330 at narrow gate, Figure 11, [0046]) on the first conductive layer, the first conductive layer extending above the first semiconductor region (of 112) to a first height, and the second gate structure includes a second conductive layer (1320 at wider gate, [0046]) and a second conductive fill (1330 at wider gate, [0046]) on the second conductive layer, the second conductive layer extending above the second semiconductor region to a second height that is substantially the same as the first height (based on the Figure 11).
Colombeau does not explicitly teach a chip package comprising one or more dies, at least one of the one or more dies comprising the first semiconductor device and the second semiconductor device.
However, BOMBERGER is a pertinent art which teaches a semiconductor device with gate-all-around transistor with nanowires channel, wherein Figure 10 teaches a printed circuit board comprising one or more dies (chips) comprising integrated circuits comprising the semiconductor device with gate-all-around transistor with nanowires channel in order to form an motherboard of a computing device ([0135]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to use a chip package comprising one or more dies, at least one of the one or more dies comprising the first semiconductor device and the second semiconductor device according to the teaching of BOMBERGER in order to make a computing device.
Regarding claim 9, Figures 2 and 11A-11F of Colombeau disclose that the electronic device of claim 8, wherein the first semiconductor region comprises a plurality of first semiconductor nanoribbons (112, on right side of Figure 11, [0019] and [0022]) and the second semiconductor region comprises a plurality of second semiconductor nanoribbons (112, on left side of Figure 11, [0019] and [0022]).
Regarding claim 10, Figures 2 and 11A-11F of Colombeau disclose that the electronic device of claim 8, wherein the first gate structure includes a first gate dielectric around the first semiconductor region, and the second gate structure includes a second gate dielectric around the second semiconductor region (1310, gate dielectric on both narrow and wide gate, [0045]).
Regarding claim 11, Figures 2 and 11A-11F of Colombeau do not teach electronic device of claim 8, wherein the first conductive layer (1320 at narrow gate) and the second conductive layer (1320 at wider gate) comprise titanium or tungsten.
However, BOMBERGER is a pertinent art which teaches a semiconductor device with gate-all-around transistor with nanowires channel, wherein the gate electrode is composed of a non-workfunction-setting fill material formed above a metal workfunction-setting layer. The gate electrode layer may consist of a P-type workfunction metal or an N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a conductive fill layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide ([0085]).
Thus, it would have been obvious to try by one of ordinary skill in the art before the effective filing date of the claimed invention to use the first conductive layer (1320, narrow gate region) and the second conductive layer (1320, wider gate region) comprise titanium or tungsten according to the teaching of BOMBERGER in order to have proper work-function in the device of Colombeau, since it has been held that choosing from a finite number of identified, predictable solutions such as the claimed materials used to form the device, with a reasonable expectation of success is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007).
Regarding claim 12, Figures 2 and 11A-11F of Colombeau disclose that the electronic device of claim 8, wherein the second width is at least two times greater than the first width ([0060]).
Regarding claim 13, Figures 2 and 11A-11F of Colombeau in view of BOMBERGER teach that the electronic device of claim 8, further comprising a printed circuit board, wherein the chip package is coupled to the printed circuit board (Figure 10 of BOMBERGER).
Examiner Notes
A reference to specific paragraphs, columns, pages, or figures in a cited prior art reference is not limited to preferred embodiments or any specific examples. It is well settled that a prior art reference, in its entirety, must be considered for all that it expressly teaches and fairly suggests to one having ordinary skill in the art. Stated differently, a prior art disclosure reading on a limitation of Applicant's claim cannot be ignored on the ground that other embodiments disclosed were instead cited. Therefore, the Examiner's citation to a specific portion of a single prior art reference is not intended to exclusively dictate, but rather, to demonstrate an exemplary disclosure commensurate with the specific limitations being addressed. In re Heck, 699 F.2d 1331, 1332-33,216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). In re: Upsher-Smith Labs. v. Pamlab, LLC, 412 F.3d 1319, 1323, 75 USPQ2d 1213, 1215 (Fed. Cir. 2005); In re Fritch, 972 F.2d 1260, 1264, 23 USPQ2d 1780, 1782 (Fed. Cir. 1992); Merck& Co. v. BiocraftLabs., Inc., 874 F.2d 804, 807, 10 USPQ2d 1843, 1846 (Fed. Cir. 1989); In re Fracalossi, 681 F.2d 792,794 n.1, 215 USPQ 569, 570 n.1 (CCPA 1982); In re Lamberti, 545 F.2d 747, 750, 192 USPQ 278, 280 (CCPA 1976); In re Bozek, 416 F.2d 1385, 1390, 163 USPQ 545, 549 (CCPA 1969).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday-Friday, 8:00 AM - 5:00 PM (Eastern Time).
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/KHAJA AHMAD/Primary Examiner, Art Unit 2813
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