DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 7, 9, 11, 13, 15, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Vorbach et al. (US Patent No. 7,844,796 B2), hereinafter referred to as VORBACH.
Consider Claim 7,
VORBACH teaches a system comprising:
a first plurality of registers to store first activation data and first tag bits (VORBACH, e.g., Col 4:67-Col 5:2, first subset of n registers (RD0…RDm-1) include data and a valid bit. The examiner notes that “activation data” is interpreted as data with an intended use.);
wherein the first plurality of registers respectively outputs the first activation data when a first tag bit has a first value and does not output the first activation data when the first tag bit has a second value (VORBACH, e.g., Col 5:2-10, data can only be read if valid bit is set.).
Consider Claim 9,
VORBACH further teaches:
a second plurality of registers to store second activation data and second tag bits (VORBACH, e.g., Col 4:67-Col 5:2, second subset of n registers (RDm…RDn) include data and a valid bit. The examiner notes that “activation data” is interpreted as data with an intended use.);
wherein the second plurality of registers respectively outputs the second activation data when a second tag bit has a first value and does not output the second activation data when the second tag bit has a second value (VORBACH, e.g., Col 5:2-10, data can only be read if valid bit is set.).
Consider Claim 11,
VORBACH teaches a method comprising:
outputting, by a first plurality of registers, activation data when a first set of tag bits respectively contain a first value; and not outputting, by the first plurality of registers, activation data when the first set of tag bits respectively contain a second value (VORBACH, e.g., Col 4:67-Col 5:2, first subset of n registers (RD0…RDm-1) include data and a valid bit; Col 5:2-10, data can only be read if valid bit is set. The examiner notes that “activation data” is interpreted as data with an intended use.).
Consider Claim 13,
VORBACH further teaches outputting, by a second plurality of registers, second activation data when a second set of tag bits contains a first value; and not outputting, by the second plurality of registers, second activation data when the second set of tag bits contains a second value (VORBACH, e.g., Col 4:67-Col 5:2, second subset of n registers (RDm…RDn) include data and a valid bit; Col 5:2-10, data can only be read if valid bit is set.).
Consider Claim 15,
VORBACH teaches a system comprising:
a first plurality of registers to store first activation data and first tag bits, wherein the first plurality of registers respectively output first activation data when a stored first tag bit has a first value and does not output first activation data when the stored first tag bit has a second value (VORBACH, e.g., Col 4:67-Col 5:2, first subset of n registers (RD0…RDm-1) include data and a valid bit; Col 5:2-10, data can only be read if valid bit is set. The examiner notes that “activation data” is interpreted as data with an intended use.); and
a second plurality of registers to store second activation data and second tag bits, wherein the second plurality of registers respectively output second activation data when a stored second tag bit has a first value and does not output second activation data when the stored second tag bit has a second value (VORBACH, e.g., Col 4:67-Col 5:2, second subset of n registers (RDm…RDn) include data and a valid bit; Col 5:2-10, data can only be read if valid bit is set. The examiner notes that “activation data” is interpreted as data with an intended use.).
Consider Claim 17,
VORBACH teaches a method comprising:
outputting, by a first plurality of registers, first activation data in response to a first set of tag bits (VORBACH, e.g., Col 4:67-Col 5:2, first subset of n registers (RD0…RDm-1) include data and a valid bit; Col 5:2-10, data can only be read if valid bit is set. The examiner notes that “activation data” is interpreted as data with an intended use.); and
outputting, by a second plurality of registers, second activation data in response to a second set of tag bits (VORBACH, e.g., Col 4:67-Col 5:2, first subset of n registers (RDm…RDn) include data and a valid bit; Col 5:2-10, data can only be read if valid bit is set.).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3, 4, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Jones et al. (US Patent No. 7,675,925 B2), hereinafter referred to as JONES, in view of PENNEY (US Patent No. 10,366,742 B1).
Consider Claim 1,
JONES teaches a system comprising:
a plurality of address decoders (JONES, e.g., Fig 7:81/74, each PBRAM includes circuitry to decode received address information; Col 11:14-34, plural PBRAM operating together (i.e., a plurality of address decoders).) to receive an address (JONES, e.g., Col 12:45-49, receive queue ID;Col 8:57-60, queue descriptor is an address.) and output a plurality of row enabling signals in response to the address (JONES, e.g., Col 8:10-12, multibank architectures use simultaneous row accesses. The examiner notes that access to plural banks requires plural signals to enable the rows of individual banks.);
a first plurality of registers to store, sequentially, activation data in response to the plurality of row enabling signals (JONES, e.g., Col 8:15-20, store data; Fig 7:72, serial registers; Fig 8:72, shows data stored sequentially. The examiner notes that “activation data” is interpreted as data with an intended use.); and
transmit, in parallel, activation data received from the first plurality of registers (JONES, e.g., Fig 7:73;Col 7:9-10, output ports operate in parallel; Col 8:15-20, data ports receive data from serial registers.).
JONES fails to expressly teach a second plurality of registers to store the data from the first plurality of registers. PENNEY describes systems and methods for moving data between a first location and second location and is considered analogous prior art. PENNEY does teach a second plurality of registers to store the data from the first plurality of registers (PENNEY, e.g., Fig 2:96; Col 6:12-16, describes loading parallel registers from the first set of serial registers.). It would have been obvious to a person of ordinary skill in the art, prior to the effective filing date of the claimed invention, to modify the system of JONES with the cited teachings of PENNEY because it mitigates timing issues associated with the conversion of serial data to parallel data and is considered a matter of design choice (PENNEY, e.g., Col 2:12-46).
Consider Claim 3,
The system of JONES and PENNEY, as combined, teaches the system of claim 1, above, but fails to additionally teach a static random access memory to provide the activation data to store in the first plurality of registers. The examiner takes official notice of the fact that SRAM is notoriously well-known in the art and is one of a limited number of commonly used computer memory types. It would have been obvious to a person of ordinary skill in the art to modify the system of JONES and PENNEY, as combined, to use SRAM to provide the activation data to store in the first plurality of registers as a matter of design choice based on speed, cost, and silicon area.
Consider Claim 4,
JONES teaches a method comprising:
outputting, by a plurality of address decoders (JONES, e.g., Fig 7:81/74, each PBRAM includes circuitry to decode received address information; Col 11:14-34, plural PBRAM operating together (i.e., a plurality of address decoders).), a plurality of row enabling signals in response to an address (JONES, e.g., Col 12:45-49, receive queue ID;Col 8:57-60, queue descriptor is an address; Col 8:10-12, multibank architectures use simultaneous row accesses. The examiner notes that access to plural banks requires plural signals to enable the rows of individual banks.);
storing sequentially, by a first plurality of registers, activation data in response to the plurality of row enabling signals (JONES, e.g., Col 8:15-20, store data; Fig 7:72, serial registers; Fig 8:72, shows data stored sequentially. The examiner notes that “activation data” is interpreted as data with an intended use.); and
transmitting, in parallel, activation data received from the first plurality of registers (JONES, e.g., Fig 7:73;Col 7:9-10, output ports operate in parallel; Col 8:15-20, data ports receive data from serial registers.).
JONES fails to expressly teach a second plurality of registers to store the data from the first plurality of registers. PENNEY describes systems and methods for moving data between a first location and second location and is considered analogous prior art. PENNEY does teach a second plurality of registers to store the data from the first plurality of registers (PENNEY, e.g., Fig 2:96; Col 6:12-16, describes loading parallel registers from the first set of serial registers.). It would have been obvious to a person of ordinary skill in the art, prior to the effective filing date of the claimed invention, to modify the system of JONES with the cited teachings of PENNEY because it mitigates timing issues associated with the conversion of serial data to parallel data and is considered a matter of design choice (PENNEY, e.g., Col 2:12-46).
Consider Claim 6,
The system of JONES and PENNEY, as combined, teaches the method of claim 4, above, but fails to additionally teach wherein the storing sequentially comprises receiving the activation data by the first plurality of registers from a static random access memory. The examiner takes official notice of the fact that SRAM is notoriously well-known in the art and is one of a limited number of commonly used computer memory types. It would have been obvious to a person of ordinary skill in the art to modify the system of JONES and PENNEY, as combined, to use SRAM to provide the activation data to store in the first plurality of registers as a matter of design choice based on speed, cost, and silicon area.
Allowable Subject Matter
Claims 2, 5, 8, 10, 12, 14, 16, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Gary W Cygiel whose telephone number is (571)270-1170. The examiner can normally be reached Monday - Thursday 11am-3pm PST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan P Savla can be reached at (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Gary W. Cygiel/Primary Examiner, Art Unit 2137