Prosecution Insights
Last updated: April 19, 2026
Application No. 18/077,763

OLED DISPLAY PANEL AND PREPARATION METHOD THEREFOR

Non-Final OA §103
Filed
Dec 08, 2022
Examiner
PRASAD, NEIL R
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co. Ltd.
OA Round
3 (Non-Final)
85%
Grant Probability
Favorable
3-4
OA Rounds
2y 3m
To Grant
94%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allow Rate
591 granted / 694 resolved
+17.2% vs TC avg
Moderate +9% lift
Without
With
+9.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
26 currently pending
Career history
720
Total Applications
across all art units

Statute-Specific Performance

§103
56.1%
+16.1% vs TC avg
§102
28.7%
-11.3% vs TC avg
§112
4.7%
-35.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 694 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/6/2026 has been entered. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-3 and 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Kang (US Publication No. 2019/0115403) in view of Zhang et al. (US Publication No. 2020/0127225), and further in view of Tang et al. (US Publication No. 2019/0115561). Regarding claim 1, Kang discloses an OLED display panel, comprising: a substrate (SUB) a second metal layer (ANO) disposed on the substrate (SUB) an anode layer (ANO) disposed on a side of the second metal layer (ACT) away from the substrate (SUB), wherein the anode layer (ANO) includes an anode and an auxiliary electrode (CT) disposed in a same layer (PAS), and the auxiliary electrode (CT) is disposed in an overlapping area (A) a cathode layer (CAT) disposed on a side of the electron transport layer away from the substrate (SUB) wherein the auxiliary electrode (ACT) is provided with a groove (OH), an opening of the groove is disposed toward the cathode layer (CAT) Kang does not disclose an electron transport layer disposed on a side of the anode layer away from the substrate and the auxiliary electrode extends through the electron transport layer and is electrically connected to the cathode layer. However, Zhang discloses an electron transport layer (640) on a side of an anode layer (310) away from the substrate (110) and the auxiliary electrode (320) extends through the electron transport layer (640) and is electrically connected to the cathode layer (700) (Figure 7). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the display of Kang to include the auxiliary electrode extending through the electron transport layer to the cathode layer, as taught by Zhang, since it the mura effect due to IR drop of the cathode electrode can be improved (paragraphs 133-134). Kang does not disclose the auxiliary electrode is disposed in a three-layer stacked structure which is decreased gradually away from the substrate and the grooves are provided in each layer to form a scratching chamfer structure at an upper edge of each groove. However, Tang discloses a three layer stacked structure (320/540/550) which decreases away from the substrate, and each layer forms a scratching chamfer structure at an upper edge of each groove (Figure 6). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the auxiliary electrode to be formed in this shape, as taught by Tang, since it can improve uneven display problems due to IR drop of the cathode (paragraph 131). Regarding claim 2, Kang discloses the auxiliary electrode (CT) further comprises a first auxiliary electrode (CT) disposed in a non-display area (A) and a second auxiliary electrode (CAT above PN) disposed in a display area (EA), wherein the cathode layer (CAT) is electrically connected to the second metal layer (ACT) through the first auxiliary electrode (CT) in the non-display area (A), and the second auxiliary electrode is electrically connected to the cathode (CAT) in parallel in the display area (EA). Regarding claim 3, it would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified Kang in view of Zhang as stated above in the rejection of claim 2 above. Additionally, Zhang discloses wherein the first auxiliary electrode (220) has at least one first scratching chamfer structure (400 left), and the second auxiliary electrode (320) has at least one second scratching chamfer structure (400 right), wherein the first scratching chamfer structure contacts with the cathode layer (700), and the second scratching chamfer structure contacts with the cathode layer (Figure 8). Regarding claim 6, Zhang discloses the groove comprises a first groove (400 left) and a second groove (400 right), the first auxiliary electrode (220) is provided with the first groove, the second auxiliary electrode (320) is provided with the second groove, wherein a depth of the first groove is less than or equal to a thickness of the first auxiliary electrode, and a depth of the second groove is less than or equal to a thickness of the second auxiliary electrode (Figures 6 and 8). Regarding claim 7, Kang/Zhang discloses the limitations as discussed in the rejection of claim 1 above. Kang/Zhang is silent regarding the electron transport layer has a thickness of 10 nm to 20 nm. However, it would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the thickness of the electron transport layer to be within this range to optimize the voltage by which the metal electrodes burn a portion of the transport layer to the injection layer at the corners, thereby improving the mura effect of the OLED (paragraph 134), since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Regarding claim 8, Kang discloses the anode layer (ANO) is disposed in a three-layer stacked structure (PAS/OC/BN). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NEIL R PRASAD whose telephone number is (571) 270-3129. The examiner can normally be reached M-F 9am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /N.R.P/ 1/18/2026Examiner, Art Unit 2897 /JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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Prosecution Timeline

Dec 08, 2022
Application Filed
Jul 04, 2025
Non-Final Rejection — §103
Sep 29, 2025
Response Filed
Oct 06, 2025
Final Rejection — §103
Jan 06, 2026
Request for Continued Examination
Jan 14, 2026
Response after Non-Final Action
Jan 19, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12598873
DISPLAY PANEL AND ELECTRONIC DEVICE INCLUDING THE SAME
2y 5m to grant Granted Apr 07, 2026
Patent 12599014
PACKAGE DEVICE AND MANUFACTURING METHOD THEREOF
2y 5m to grant Granted Apr 07, 2026
Patent 12575287
Foldable Display Apparatus
2y 5m to grant Granted Mar 10, 2026
Patent 12568836
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
2y 5m to grant Granted Mar 03, 2026
Patent 12563727
SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE
2y 5m to grant Granted Feb 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
85%
Grant Probability
94%
With Interview (+9.2%)
2y 3m
Median Time to Grant
High
PTA Risk
Based on 694 resolved cases by this examiner. Grant probability derived from career allow rate.

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