DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner’s Remark
Applicant is advised of the following:
Should claim 13 be found allowable, claim 18 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. Examiner notes that it is likely that this claim should depend on claim 17.
Should claim 24 be found allowable, claim 33 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. Examiner notes that it is likely that this claim should depend on one of claims 30-32.
When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. Applicant has not complied with one or more conditions for receiving the benefit of an earlier filing date under 35 U.S.C. 119(e) as follows: The later-filed application must be an application for a patent for an invention which is also disclosed in the prior application (the parent or original nonprovisional application or provisional application). The disclosure of the invention in the parent application and in the later-filed application must be sufficient to comply with the requirements of 35 U.S.C. 112(a) or the first paragraph of pre-AIA 35 U.S.C. 112, except for the best mode requirement. See Transco Products, Inc. v. Performance Contracting, Inc., 38 F.3d 551, 32 USPQ2d 1077 (Fed. Cir. 1994).
The disclosure of the prior-filed application, Application No. 63/409,140 (hereinafter Prior Application), fails to provide adequate support or enablement in the manner provided by 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph for one or more claims of this application. The Prior Application figure 40 and related paragraph 169, does not disclose Column Tag bits, Accumulator, the parts that composes the Accumulator, and the output block comprising multiple current-to-voltage converter and analog-to-digital converter. Accordingly, claims 2-8, 12-18, 20-38 are not entitled to the benefit of the Prior Application.
Information Disclosure Statement
The information disclosure statement (IDS) filed 12/10/2025 recites “WO-2020149889-A1” which was already considered in the IDS filed 07/06/2023.
The information disclosure statement (IDS) filed 03/19/2026 recites “TW-201921282” which was already considered in the IDS filed 07/16/2024 and “TW-202131205” which was already considered in the IDS filed 07/16/2024.
On 04/13/2026, 03/19/2025, and 12/10/2025, applicant filed 2 copies of the IDS on each date. Only one copy of each date has been signed by the examiner and are attached to this office action. Examiner note that if the applicant files any more IDS in this case, they should file only 1 copy.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: item 100 in figure 1.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following:
“an output block
“a second output register to store the second digital output during the second time period”, figure 40A does not clearly show a direct connection from 4001/4002 to 4004.
“a second output register to store the second digital output”
“a first current-to-voltage converter… and a first analog-to-digital converter…; and a second current-to-voltage converter… and a second analog-to-digital converter…;”
“the first current-to-voltage converter and the first analog-to-digital converter comprises a first column tag bit; and the second current-to-voltage converter and the second analog-to-digital converter a second column tag bit”
“wherein the accumulator receives data when the column tag bit has a first value…. has a second value”
must be shown or the features canceled from the claims. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to as failing to comply with 37 CFR 1.71(a) because of the following informalities:
Par.153, ll.1-2, “3401. . Input” should read as “3401. Input”
Par.159, ll.2, “sub- block” should read as “sub-block”
Par.159, ll.1, “figure 38” should read as “figure 38A”.
Par.166, ll.1-2, there are redundant spacing or there is a missing paragraph number.
Par.167, ll.10, “buffers 3903 1” should read as “buffers 3903”.
Par.185, ll.9, “If no” should read as “If not”.
Appropriate correction is required.
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
“a first current-to-voltage converter… and a first analog-to-digital converter…; and a second current-to-voltage converter… and a second analog-to-digital converter…;”
“the first current-to-voltage converter and the first analog-to-digital converter comprises a first column tag bit; and the second current-to-voltage converter and the second analog-to-digital converter a second column tag bit”
“(2) the first output register during the first time period and the first output register during the second time period”
“the accumulator receives data when the column tag bit has a first value and does not receive data when the column tag bit has a second value”
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 28, 30-32 and 34-38 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding new claim 28, the claim recites ““the accumulator receives data when the column tag bit has a first value and does not receive data when the column tag bit has a second value”. However, the specification never discloses that “the accumulator receives data when the column tag bit has a first value and does not receive data when the column tag bit has a second value”. See specification paragraphs 174-179 and figures 40A-C. The applicant has not pointed out where the new claim is supported.
Regarding new claim 30, the claim recites “a first current-to-voltage converter… and a first analog-to-digital converter…; and a second current-to-voltage converter… and a second analog-to-digital converter…;”. However, the specification never discloses a “first” or “second” current-to-voltage converter or first analog-to-digital converter. See specification paragraphs 174-179 and figures 40A-C. The applicant has not pointed out where the new claim is supported.
Claims 31-32 effectively depends on claim 30 and are rejected for the reasons given above. Additionally, the specification nor the figures discloses a first and second column tag bits for their respective current-to-voltage converter and analog-to-digital converter.
Regarding new claim 34, the claim recites “an accumulator to sum data received from one of … (2) the first output register during the first time period and the first output register during the second time period.” However, the specification never discloses the accumulator receiving from “the first output register during the first time period and the first output register during the second time period”. See specification paragraphs 174-179 and figures 40A-C. The applicant has not pointed out where the new claim is supported.
Claims 35-38 effectively depends on claim 34 and are rejected for the reasons given above
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 25-26, and 29 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 25 recites the limitation " the first output register, and the second output register " in lines 2-3. There is insufficient antecedent basis for this limitation as claims 21 and 20 does not recite such output registers. For purposes of examination claim 25 will depend on claim 24 as claim 24 introduces the registers.
Claim 26 recites the limitations " the first digital output" and “the second digital output” in lines 2 and 4. There is insufficient antecedent basis for this limitation. Additionally claim 29 effectively depends on claim 26, and is rejected for the reason given for 26.
Claim 29 also recites the limitation of “the output block” in line 2. There is insufficient antecedent basis for this limitation as claim 26 does not recite such output block.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 9-11, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (US 2021/0125045 A1, from IDS filed 7/6/2023), hereinafter Jang, and in view of Zhang et al. (NPL: "Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks”), hereinafter Zhang.
Regarding claim 1, Jang discloses:
A system comprising:
An array of non-volatile memory [NVM] cells arranged into rows and columns [Fig.7, Synapse array; fig.9B shows rows and columns];
an output block to convert current from columns of the array into a digital output [Fig.7, 340+350, Current-to-Voltage Converter IVC and Analog-to-Digital Converter ADC; see par.74-75].
However, Jang does not explicitly disclose:
an output block to convert current from columns of the array into a first digital output during a first time period and a second digital output during a second time period
a first output register to store the first digital output during the first time period and to output the stored first digital output during the second time period; and
a second output register to store the second digital output during the second time period and to output the stored second digital output during a third time period.
In the analogous art of Neural Network Acceleration and Parallelization, Zhang teaches:
A compute engine producing the first and second digital outputs [Fig.11, compute engine];
a first output register to store the first digital output during the first time period and to output the stored first digital output during the second time period; and a second output register to store the second digital output during the second time period and to output the stored second digital output during a third time period [Fig.11, discloses two output buffer sets after the compute engine; Fig.12 discloses Ping-Pong/Double output buffers; “Double buffer sets are used to realize ping-pong operations…. This is the ping-pong operation of output feature maps.”Sec.4.3]
It would have been obvious to one of ordinary skill in the art, having the teachings of Jang and Zhang before him before the effective filing date of the claimed invention to include the double buffer taught by Zhang into the system of Jang in order to implement double buffering of the digital outputs allowing the overlapping of data transfer time and computation time [Zhang: Sec.3.1 and 4.3]. The combination of both Jang and Zhang discloses an output block to convert current from columns of the array into a first digital output during a first time period and a second digital output during a second time period; a first output register to store the first digital output during the first time period and to output the stored first digital output during the second time period; and a second output register to store the second digital output during the second time period and to output the stored second digital output during a third time period.
Regarding claim 9, Jang and Zhang disclose the invention substantially as claimed. See the discussion of claim 1 above.
Jang discloses wherein the output block comprises a current-to-voltage converter to convert the current from the columns of the array into a voltage and an analog-to-digital converter to convert the voltage into the digital output [Fig.7, 340+350, IVC and ADC; see par.74-75].
Where Zhang discloses first and second digital outputs, see claim 1 above.
Regarding claim 10, Jang discloses:
A method comprising:
converting, by an output block, current from columns of an array of non-volatile memory cells into a digital output [Fig.7, Synapse array; fig.9B shows rows and columns; Fig.7, 340+350, IVC and ADC; see par.74-75].
However, Jang does not explicitly disclose:
during a first time period: converting, by an output block, current from columns of an array of non-volatile memory cells into a first digital output; and storing, in a first output register, the first digital output; and
during a second time period: converting, by the output block, current from columns of an array of non-volatile memory cells into a second digital output; storing, in a second output register, the second digital output; and outputting, from the first output register, the stored first digital output.
In the analogous art of Neural Network Acceleration and Parallelization, Zhang teaches:
during a first time period: A compute engine producing a first digital output; and storing, in a first output register, the first digital output [Fig.11, compute engine; Fig. 12 shows outputting into buff 0]; and
during a second time period: A compute engine producing a second digital output; storing, in a second output register, the second digital output; and outputting, from the first output register, the stored first digital output [Fig.11, compute engine; Fig. 12 shows outputting into buff 1 and storing output buff 0].
It would have been obvious to one of ordinary skill in the art, having the teachings of Jang and Zhang before him before the effective filing date of the claimed invention to include the double buffer taught by Zhang into the system of Jang in order to implement double buffering of the digital outputs allowing the overlapping of data transfer time and computation time [Zhang: Sec.3.1 and 4.3]. The combination of both Jang and Zhang discloses during a first time period: converting, by an output block, current from columns of an array of non-volatile memory cells into a first digital output; and storing, in a first output register, the first digital output; and during a second time period: converting, by the output block, current from columns of an array of non-volatile memory cells into a second digital output; storing, in a second output register, the second digital output; and outputting, from the first output register, the stored first digital output.
Regarding claim 11, Jang and Zhang disclose the invention substantially as claimed. See the discussion of claim 10 above.
Jang discloses: converting, by an output block, current from columns of an array of non-volatile memory cells into a digital output [Fig.7, Synapse array; fig.9B shows rows and columns; Fig.7, 340+350, IVC and ADC; see par.74-75].
However, Jang does not explicitly disclose the additional limitations of claim 11.
In the analogous art of Neural Network Acceleration and Parallelization, Zhang teaches the use of ping-pong/double-buffering i.e. the alternating use of load and store operations [“Note that those two independent channel for load and store operation mechanism work for any other data reuse situation in this framework.” Sec.4.3]. It would have been obvious to one of ordinary skill in the art that figure 12 will keep repeating in order to “ping-pong” the two buffers [“This is the ping-pong operation of output feature maps.” Sec.4.3].
As such, Zhang discloses:
during a third time period:
converting, by the output block, current from columns of an array of non-volatile memory cells into a third digital output; storing, in the first output register, the third digital output; and outputting, from the second output register, the stored second digital output [Fig.11, compute engine; Fig. 12 shows outputting into buff 0 and storing output buff 1].
As such, It would have been obvious to one of ordinary skill in the art, having the teachings of Jang and Zhang before him before the effective filing date of the claimed invention to include the double buffer taught by Zhang into the system of Jang in order to implement double buffering of the digital outputs allowing the overlapping of data transfer time and computation time [Zhang: Sec.3.1 and 4.3].
Regarding claim 19, Jang and Zhang disclose the invention substantially as claimed. See the discussion of claim 10 above.
Jang discloses wherein the output block comprises a current-to-voltage converter to convert the current from the columns of the array into a voltage and an analog-to-digital converter to convert the voltage into the digital output [Fig.7, 340+350, IVC and ADC; see par.74-75].
Where Zhang discloses first and second digital outputs, see claim 10 above.
Claims 2, 12, 26, and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Gallo et al. (NPL: “A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference”), hereinafter Gallo, and in view of Zhang.
Regarding claim 2, Gallo discloses:
A system comprising:
an array of non-volatile memory cells arranged into rows and columns [Fig.1, (1) PCM array];
an output block to convert current from columns of the array into a digital output [Fig.1, (4) ADC arrays; Extended Data Fig.2, “The resulting bit line (BL) currents are summed up on the blue wires and read by the ADCs”];
an output buffer to store the digital output [Fig.1, (6) ADC register arrays; “the results are transmitted from each ADC to the local digital processing unit (LDPU) for post-processing. In the first step, the results are transferred to a register array, such that the operation becomes fully pipelined” Sec.II].
an accumulator to sum data received from one or more of the output block and output registers [Fig.1, (8) Activation function block + (9) Link controller; “the links can transfer data across the LDPUs of multiple cores to realize fully on-chip intra-layer partial sum accumulation” Sec.II].
However, Gallo does not explicitly disclose:
an output block to convert current from columns of the array into a first digital output during a first time period and a second digital output during a second time period;
a first output register to store the first digital output during the first time period and to output the stored first digital output during the second time period; and a second output register to store the second digital output during the second time period and to output the stored second digital output during a third time period.
In the analogous art of Neural Network Acceleration and Parallelization, Zhang teaches:
A compute engine producing the first and second digital outputs [Fig.11, compute engine];
a first output register to store the first digital output during the first time period and to output the stored first digital output during the second time period; and a second output register to store the second digital output during the second time period and to output the stored second digital output during a third time period [Fig.11, discloses two output buffer sets after the compute engine; Fig.12 discloses Ping-Pong/Double output buffers; “Double buffer sets are used to realize ping-pong operations…. This is the ping-pong operation of output feature maps.”Sec.4.3]
It would have been obvious to one of ordinary skill in the art, having the teachings of Gallo and Zhang before him before the effective filing date of the claimed invention to modify the ADC register array of Gallo to utilize the double-buffering as taught by Zhang in order to implement double buffering of the digital outputs allowing the overlapping of data transfer time and computation time [Zhang: Sec.3.1 and 4.3].
Regarding claim 12, Gallo discloses:
A method comprising:
converting, by an output block, current from columns of an array of non-volatile memory cells into a digital output [Fig.1, (4) ADC arrays; Fig.2, “The resulting bit line (BL) currents are summed up on the blue wires and read by the ADCs”];
However, Gallo does not explicitly disclose:
during a first time period: converting, by an output block, current from columns of an array of non-volatile memory cells into a first digital output; and storing, in a first output register, the first digital output; and
during a second time period: converting, by the output block, current from columns of an array of non-volatile memory cells into a second digital output; storing, in a second output register, the second digital output; and outputting, from the first output register, the stored first digital output.
In the analogous art of Neural Network Acceleration and Parallelization, Zhang teaches:
during a first time period: A compute engine producing a first digital output; and storing, in a first output register, the first digital output [Fig.11, compute engine; Fig. 12 shows outputting into buff 0]; and
during a second time period: A compute engine producing a second digital output; storing, in a second output register, the second digital output; and outputting, from the first output register, the stored first digital output [Fig.11, compute engine; Fig. 12 shows outputting into buff 1 and storing output buff 0].
Furthermore, Zhang teaches the use of ping-pong/double-buffering i.e. the alternating use of load and store operations [“Note that those two independent channel for load and store operation mechanism work for any other data reuse situation in this framework.” Sec.4.3]. It would have been obvious to one of ordinary skill in the art that figure 12 will keep repeating in order to “ping-pong” the two buffers [“This is the ping-pong operation of output feature maps.” Sec.4.3].
As such, Zhang discloses:
during a third time period: converting, by the output block, current from columns of an array of non-volatile memory cells into a third digital output; storing, in the first output register, the third digital output; and outputting, from the second output register, the stored second digital output [Fig.11, compute engine; Fig. 12 shows outputting into buff 0 and storing output buff 1].
It would have been obvious to one of ordinary skill in the art, having the teachings of Gallo and Zhang before him before the effective filing date of the claimed invention to modify the ADC register array of Gallo to utilize the double-buffering as taught by Zhang in order to implement double buffering of the digital outputs allowing the overlapping of data transfer time and computation time [Zhang: Sec.3.1 and 4.3].
Regarding claim 26, Gallo discloses:
A system comprising:
an array of non-volatile memory cells arranged into rows and columns [Fig.1, (1) PCM array];
an output buffer to store the digital output [Fig.1, (6) ADC register arrays; “the results are transmitted from each ADC to the local digital processing unit (LDPU) for post-processing. In the first step, the results are transferred to a register array, such that the operation becomes fully pipelined” Sec.II].
an accumulator to sum data received from the output registers [Fig.1, (8) Activation function block + (9) Link controller; “the links can transfer data across the LDPUs of multiple cores to realize fully on-chip intra-layer partial sum accumulation” Sec.II].
However, Gallo does not explicitly disclose:
a first output register to store the first digital output during the first time period and to output the stored first digital output during the second time period; and a second output register to store the second digital output during the second time period and to output the stored second digital output during a third time period; and the accumulator to sum data received from the first output register and the second output register.
In the analogous art of Neural Network Acceleration and Parallelization, Zhang teaches:
A compute engine producing the first and second digital outputs [Fig.11, compute engine];
a first output register to store the first digital output during the first time period and to output the stored first digital output during the second time period; and a second output register to store the second digital output during the second time period and to output the stored second digital output during a third time period [Fig.11, discloses two output buffer sets after the compute engine; Fig.12 discloses Ping-Pong/Double output buffers; “Double buffer sets are used to realize ping-pong operations…. This is the ping-pong operation of output feature maps.”Sec.4.3]
It would have been obvious to one of ordinary skill in the art, having the teachings of Gallo and Zhang before him before the effective filing date of the claimed invention to modify the ADC register array of Gallo to utilize the double-buffering as taught by Zhang in order to implement double buffering of the digital outputs allowing the overlapping of data transfer time and computation time [Zhang: Sec.3.1 and 4.3].
Regarding claim 34, Gallo discloses:
A system comprising:
an array of non-volatile memory cells arranged into rows and columns [Fig.1, (1) PCM array];
an output buffer to store the digital output [Fig.1, (6) ADC register arrays; “the results are transmitted from each ADC to the local digital processing unit (LDPU) for post-processing. In the first step, the results are transferred to a register array, such that the operation becomes fully pipelined” Sec.II].
an accumulator to sum data received from the output registers [Fig.1, (8) Activation function block + (9) Link controller; “the links can transfer data across the LDPUs of multiple cores to realize fully on-chip intra-layer partial sum accumulation” Sec.II].
However, Gallo does not explicitly disclose:
a first output register to store the first digital output during the first time period and to output the stored first digital output during the second time period; and a second output register to store the second digital output during the second time period and to output the stored second digital output during a third time period; and the accumulator to sum data received from one of (i) the first output register during the first time period and the second output register during the second time period, or (2) the first output register during the first time period and the first output register during the second time period.
In the analogous art of Neural Network Acceleration and Parallelization, Zhang teaches:
A compute engine producing the first and second digital outputs [Fig.11, compute engine];
a first output register to store the first digital output during the first time period and to output the stored first digital output during the second time period; and a second output register to store the second digital output during the second time period and to output the stored second digital output during a third time period [Fig.11, discloses two output buffer sets after the compute engine; Fig.12 discloses Ping-Pong/Double output buffers; “Double buffer sets are used to realize ping-pong operations…. This is the ping-pong operation of output feature maps.”Sec.4.3]
It would have been obvious to one of ordinary skill in the art, having the teachings of Gallo and Zhang before him before the effective filing date of the claimed invention to modify the ADC register array of Gallo to utilize the double-buffering as taught by Zhang in order to implement double buffering of the digital outputs allowing the overlapping of data transfer time and computation time [Zhang: Sec.3.1 and 4.3]. the combination disclosing: a first output register to store the first digital output during the first time period and to output the stored first digital output during the second time period; and a second output register to store the second digital output during the second time period and to output the stored second digital output during a third time period; and the accumulator to sum data received from the first output register during the first time period and the second output register during the second time period
Claims 3, 13, 18, 20, and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Gallo, and Zhang, in view of San Francisco State University (NPL: “Analog Circuit Systems for Memristor-based Neuromorphic System”), hereinafter SFSU.
Regarding claim 3, Gallo and Zhang disclose the invention substantially as claimed. See the discussion of claim 2 above.
Gallo does not explicitly disclose wherein the output block comprises a current- to-voltage converter to convert the current from the columns of the array into a voltage and an analog-to-digital converter to convert the voltage into the first digital output.
In the analogous art of analog circuit architectures for memristors systems, SFSU teaches Memristor producing current [Fig.1, MCA] and the use of a transimpedance Amp into SAR-ADC to convert current into digital [Fig.3].
It would have been obvious to one of ordinary skill in the art, having the teachings of Gallo and SFSU before him before the effective filing date of the claimed invention to modify the ADC of Gallo to use the Transimpedance Amp and SAR-ADC as taught by SFSU, in order to support parallel operations of a memristor array while optimizing power consumption, chip area, and errors for analog output circuitry [SFSU: Sec.1.0, 2.0, 3.3, 4.2, and 5].
Regarding claim 13, the claim is directed to claim 3. A mere change in statutory class is obvious. Claim 13 is rejected for the reasons given in claim 3
Regarding claim 18, the claim recites identical limitations as claim 13. Claim 18 is rejected for the reasons given in identical claim 13.
Regarding claim 20, Gallo discloses:
A system comprising:
an array of non-volatile memory cells arranged into rows and columns [Fig.1, (1) PCM array];
an output block to convert current from columns of the array into a digital output [Fig.1, (4) ADC arrays; Extended Data Fig.2, “The resulting bit line (BL) currents are summed up on the blue wires and read by the ADCs”];
an output buffer to store the digital output [Fig.1, (6) ADC register arrays; “the results are transmitted from each ADC to the local digital processing unit (LDPU) for post-processing. In the first step, the results are transferred to a register array, such that the operation becomes fully pipelined” Sec.II].
an accumulator to sum data received from one or more of the output block and output registers [Fig.1, (8) Activation function block + (9) Link controller; “the links can transfer data across the LDPUs of multiple cores to realize fully on-chip intra-layer partial sum accumulation” Sec.II].
However, Gallo does not explicitly disclose:
an output block to convert current from columns of the array into a first digital output during a first time period and a second digital output during a second time period;
the output block comprises a current-to-voltage converter to convert the current from the columns of the array into a voltage and an analog-to-digital converter to convert the voltage into the first digital output and the second digital output.
an accumulator to sum data received from the output block during the first time period and the second time period
In the analogous art of Neural Network Acceleration and Parallelization, Zhang teaches:
A compute engine producing the first and second digital outputs [Fig.11, compute engine];
A ping-pong output of the compute engine of a first and second time periods[Fig.11; Fig.12 discloses Ping-Pong/Double outputs; “This is the ping-pong operation of output feature maps... Note that those two independent channel for load and store operation mechanism work for any other data reuse situation in this framework.”Sec.4.3]
It would have been obvious to one of ordinary skill in the art, having the teachings of Gallo and Zhang before him before the effective filing date of the claimed invention to modify the ADC register array of Gallo to utilize the double-buffering as taught by Zhang in order to implement double buffering of the digital outputs allowing the overlapping of data transfer time and computation time [Zhang: Sec.3.1 and 4.3].
In the analogous art of analog circuit architectures for memristors systems, SFSU teaches Memristor producing current [Fig.1, MCA] and the use of a transimpedance Amp into SAR-ADC to convert current into digital [Fig.3].
It would have been obvious to one of ordinary skill in the art, having the teachings of Gallo and SFSU before him before the effective filing date of the claimed invention to modify the ADC of Gallo to use the Transimpedance Amp and SAR-ADC as taught by SFSU, in order to support parallel operations of a memristor array while optimizing power consumption, chip area, and errors for analog output circuitry [SFSU: Sec.1.0, 2.0, 3.3, 4.2, and 5].
Regarding claim 35, Gallo, Zhang, and SFSU disclose the invention substantially as claimed. See the discussion of claim 34 above.
Zhang discloses time periods [see claim 34 and fig.12]
However, Gallo and Zhang, does not explicitly disclose wherein the output block comprises a current-to- voltage converter to convert the current from the columns of the array into a voltage and an analog-to-digital converter to convert the voltage into the first digital output during the first time period.
In the analogous art of analog circuit architectures for memristors systems, SFSU teaches Memristor producing current [Fig.1, MCA] and the use of a transimpedance Amp into SAR-ADC to convert current into digital [Fig.3].
It would have been obvious to one of ordinary skill in the art, having the teachings of Gallo, Zhang, and SFSU before him before the effective filing date of the claimed invention to modify the ADC of the combination of Gallo and Zhang to use the Transimpedance Amp and SAR-ADC as taught by SFSU, in order to support parallel operations of a memristor array while optimizing power consumption, chip area, and errors for analog output circuitry [SFSU: Sec.1.0, 2.0, 3.3, 4.2, and 5]. The combination discloses the limitations of the claim.
Claims 4-6, 14-16, 21-34, 27-28, 33, and 36-38 are rejected under 35 U.S.C. 103 as being unpatentable over Gallo, Zhang, and SFSU, in view of Hoang et al. (US 11,568,200 B2), hereinafter Hoang.
Regarding claim 4, Gallo, Zhang, and SFSU disclose the invention substantially as claimed. See the discussion of claim 3 above. Gallo, Zhang, and SFSU does not explicitly disclose wherein the current-to-voltage converter and analog-to-digital converter comprises a column tag bit.
In the analogous art of memristor architectures, Hoang teaches wherein the output block comprises a column tag bit [Fig.16, Zero Column Index (ZCI) used to de-activate components of the output circuitry; See Col.13,ll.4-47 and Col.15,ll.5-37].
It would have been obvious to one of ordinary skill in the art, having the teachings of Gallo, SFSU, and Hoang before him before the effective filing date of the claimed invention to modify the Transimpedance Amp and SAR-ADC of the combination of Gallo and SFSU to use the ZCI/Zero skipping as taught by Hoang, in order to improve performance and reduce power consumption by skipping or de-activating outputs of the output circuitry [Hoang: Col.2,ll.25-63, Col.11,ll.47-57, Col.12,ll.30-34, and Col.14,ll.61-65]
Regarding claim 5, Gallo, Zhang, and SFSU disclose the invention substantially as claimed. See the discussion of claim 4 above. Gallo, Zhang, and SFSU does not explicitly disclose wherein the current-to-voltage converter outputs data when the column tag bit has a first value and does not output data when the column tag bit has a second value.
In the analogous art of memristor architectures, Hoang teaches wherein the output block outputs data when the column tag bit has a first value and does not output data when the column tag bit has a second value. [Fig.16, ZCI; “so that if the index ZCI=O the corresponding S&H 1405 is de-activated (indicated by an X) and if the index ZCI=l the corresponding S&H 1405 is activated.” Col.13,ll.18-24].
It would have been obvious to one of ordinary skill in the art, having the teachings of Gallo, SFSU, and Hoang before him before the effective filing date of the claimed invention to modify the Transimpedance Amp and SAR-ADC of the combination of Gallo and SFSU to use the ZCI/Zero skipping as taught by Hoang, in order to improve performance and reduce power consumption by skipping or de-activating outputs of the output circuitry [Hoang: Col.2,ll.25-63, Col.11,ll.47-57, Col.12,ll.30-34, and Col.14,ll.61-65]
Regarding claim 6, Gallo, Zhang, and SFSU disclose the invention substantially as claimed. See the discussion of claim 4 above. Gallo, Zhang, and SFSU does not explicitly disclose wherein the analog-to-digital converter outputs data when the column tag bit has a first value and does not output data when the column tag bit has a second value.
In the analogous art of memristor architectures, Hoang teaches wherein the output block outputs data when the column tag bit has a first value and does not output data when the column tag bit has a second value. [Fig.16, ZCI; “so that if the index ZCI=O the corresponding S&H 1405 is de-activated (indicated by an X) and if the index ZCI=l the corresponding S&H 1405 is activated.” Col.13,ll.18-24].
It would have been obvious to one of ordinary skill in the art, having the teachings of Gallo, SFSU, and Hoang before him before the effective filing date of the claimed invention to modify the Transimpedance Amp and SAR-ADC of the combination of Gallo and SFSU to use the ZCI/Zero skipping as taught by Hoang, in order to improve performance and reduce power consumption by skipping or de-activating outputs of the output circuitry [Hoang: Col.2,ll.25-63, Col.11,ll.47-57, Col.12,ll.30-34, and Col.14,ll.61-65]
Regarding claims 14-16, the claims are directed to claims 4-6, respectively. A mere change in statutory class is obvious. Claims 14-16 are rejected for the reasons given above for claims 4-6, respectively.
Regarding claims 21-23, the claims are directed to claims 4-6, respectively. Claims 21-23 are rejected for the reasons given above for claims 4-6, respectively.
Regarding claim 24, Gallo, Zhang, SFSU, and Hoang disclose the invention substantially as claimed. See the discussion of claim 21 above. Gallo discloses: an output buffer to store the digital output [Fig.1, (6) ADC register arrays; “the results are transmitted from each ADC to the local digital processing unit (LDPU) for post-processing. In the first step, the results are transferred to a register array, such that the operation becomes fully pipelined” Sec.II].
However, Gallo does not explicitly disclose: a first output register to store the first digital output during the first time period and to output the stored first digital output during the second time period; and a second output register to store the second digital output during the second time period and to output the stored second digital output during a third time period.
In the analogous art of Neural Network Acceleration and Parallelization, Zhang teaches:
A compute engine producing the first and second digital outputs [Fig.11, compute engine];
a first output register to store the first digital output during the first time period and to output the stored first digital output during the second time period; and a second output register to store the second digital output during the second time period and to output the stored second digital output during a third time period [Fig.11, discloses two output buffer sets after the compute engine; Fig.12 discloses Ping-Pong/Double output buffers; “Double buffer sets are used to realize ping-pong operations…. This is the ping-pong operation of output feature maps.”Sec.4.3]
It would have been obvious to one of ordinary skill in the art, having the teachings of Gallo and Zhang before him before the effective filing date of the claimed invention to modify the ADC register array of Gallo to utilize the double-buffering as taught by Zhang in order to implement double buffering of the digital outputs allowing the overlapping of data transfer time and computation time [Zhang: Sec.3.1 and 4.3].
Regarding claim 27, Gallo, Zhang, and SFSU disclose the invention substantially as claimed. See the discussion of claim 20. Gallo, Zhang, and SFSU does not disclose the additional limitations in the claim.
In the analogous art of memristor architectures, Hoang teaches wherein the output block outputs data when the column tag bit has a first value and does not output data when the column tag bit has a second value. [Fig.16, ZCI; “so that if the index ZCI=O the corresponding S&H 1405 is de-activated (indicated by an X) and if the index ZCI=l the corresponding S&H 1405 is activated.” Col.13,ll.18-24].
It would have been obvious to one of ordinary skill in the art, having the teachings of Gallo, SFSU, and Hoang before him before the effective filing date of the claimed invention to modify the system of the combination of Gallo and SFSU to use the ZCI/Zero skipping as taught by Hoang, in order to improve performance and reduce power consumption by skipping or de-activating outputs of the output circuitry [Hoang: Col.2,ll.25-63, Col.11,ll.47-57, Col.12,ll.30-34, and Col.14,ll.61-65]
Regarding claim 28, Gallo, Zhang, SFSU, and Hoang disclose the invention substantially as claimed. See the discussion of claim 21. Gallo, Zhang, and SFSU does not disclose the additional limitations in the claim.
In the analogous art of memristor architectures, Hoang teaches wherein the output block outputs data when the column tag bit has a first value and does not output data when the column tag bit has a second value. [Fig.16, ZCI; “so that if the index ZCI=O the corresponding S&H 1405 is de-activated (indicated by an X) and if the index ZCI=l the corresponding S&H 1405 is activated.” Col.13,ll.18-24].
It would have been obvious to one of ordinary skill in the art, having the teachings of Gallo, SFSU, and Hoang before him before the effective filing date of the claimed invention to modify the Transimpedance Amp and SAR-ADC of the combination of Gallo and SFSU to use the ZCI/Zero skipping as taught by Hoang, in order to improve performance and reduce power consumption by skipping or de-activating outputs of the output circuitry [Hoang: Col.2,ll.25-63, Col.11,ll.47-57, Col.12,ll.30-34, and Col.14,ll.61-65]. As such, It would have been obvious to one of ordinary skill in the art, that the Transimpedance Amp and SAR-ADC would be disabled prior to the accumulator.
Regarding claim 33, the claim recites identical limitations of claim 24 and is rejected for the reasons given in claim 24.
Regarding claim 36, Gallo, Zhang, and SFSU disclose the invention substantially as claimed. See the discussion of claim 35 above.
In the analogous art of analog circuit architectures for memristors systems, SFSU teaches Memristor producing current [Fig.1, MCA] and the use of a transimpedance Amp into SAR-ADC to convert current into digital [Fig.3].
It would have been obvious to one of ordinary skill in the art, having the teachings of Gallo and SFSU before him before the effective filing date of the claimed invention to modify the ADC of Gallo to use the Transimpedance Amp and SAR-ADC as taught by SFSU, in order to support parallel operations of a memristor array while optimizing power consumption, chip area, and errors for analog output circuitry [SFSU: Sec.1.0, 2.0, 3.3, 4.2, and 5].
However, Gallo, Zhang, and SFSU does not explicitly disclose wherein the current-to-voltage converter and analog-to-digital converter comprises a column tag bit.
In the analogous art of memristor architectures, Hoang teaches wherein the output block comprises a column tag bit [Fig.16, Zero Column Index (ZCI) used to de-activate components of the output circuitry; See Col.13,ll.4-47 and Col.15,ll.5-37].
It would have been obvious to one of ordinary skill in the art, having the teachings of Gallo, SFSU, and Hoang before him before the effective filing date of the claimed invention to modify the Transimpedance Amp and SAR-ADC of the combination of Gallo and SFSU to use the ZCI/Zero skipping as taught by Hoang, in order to improve performance and reduce power consumption by skipping or de-activating outputs of the output circuitry [Hoang: Col.2,ll.25-63, Col.11,ll.47-57, Col.12,ll.30-34, and Col.14,ll.61-65]
Regarding claim 37, Gallo, Zhang, and SFSU disclose the invention substantially as claimed. See the discussion of claim 36 above. Gallo, Zhang, and SFSU does not explicitly disclose wherein the current-to-voltage converter outputs data when the column tag bit has a first value and does not output data when the column tag bit has a second value.
In the analogous art of memristor architectures, Hoang teaches wherein the output block outputs data when the column tag bit has a first value and does not output data when the column tag bit has a second value. [Fig.16, ZCI; “so that if the index ZCI=O the corresponding S&H 1405 is de-activated (indicated by an X) and if the index ZCI=l the corresponding S&H 1405 is activated.” Col.13,ll.18-24].
It would have been obvious to one of ordinary skill in the art, having the teachings of Gallo, SFSU, and Hoang before him before the effective filing date of the claimed invention to modify the Transimpedance Amp and SAR-ADC of the combination of Gallo and SFSU to use the ZCI/Zero skipping as taught by Hoang, in order to improve performance and reduce power consumption by skipping or de-activating outputs of the output circuitry [Hoang: Col.2,ll.25-63, Col.11,ll.47-57, Col.12,ll.30-34, and Col.14,ll.61-65].
Regarding claim 38, Gallo, Zhang, and SFSU disclose the invention substantially as claimed. See the discussion of claim 36 above. Gallo, Zhang, and SFSU does not explicitly disclose wherein the analog-to-digital converter outputs data when the column tag bit has a first value and does not output data when the column tag bit has a second value.
In the analogous art of memristor architectures, Hoang teaches wherein the output block outputs data when the column tag bit has a first value and does not output data when the column tag bit has a second value. [Fig.16, ZCI; “so that if the index ZCI=O the corresponding S&H 1405 is de-activated (indicated by an X) and if the index ZCI=l the corresponding S&H 1405 is activated.” Col.13,ll.18-24].
It would have been obvious to one of ordinary skill in the art, having the teachings of Gallo, SFSU, and Hoang before him before the effective filing date of the claimed invention to modify the Transimpedance Amp and SAR-ADC of the combination of Gallo and SFSU to use the ZCI/Zero skipping as taught by Hoang, in order to improve performance and reduce power consumption by skipping or de-activating outputs of the output circuitry [Hoang: Col.2,ll.25-63, Col.11,ll.47-57, Col.12,ll.30-34, and Col.14,ll.61-65].
Claims 7, 17, and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Gallo and Zhang, in view of Yue et al. (NPL: “STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse”), hereinafter Yue.
Regarding claim 7, Gallo and Zhang disclose the invention substantially as claimed. See the discussion of claim 2 above.
Gallo discloses: an accumulation operation [Fig.1, (8) Activation function block + (9) Link controller; “the links can transfer data across the LDPUs of multiple cores to realize fully on-chip intra-layer partial sum accumulation” Sec.II] using:
a multiplier to receive data from the output register and to generate a first output [Fig.1, (8), bottom FP16 FMA with scale];
an adder to receive and sum the first output and a second output to generate a third output [Fig.1, (8), top FP16 FMA]; and
an controller to receive and store the third output and provide the third output as the second output to the adder [Fig.1, (9)].
However, Gallo does not explicitly discloses a shifter, or an accumulator within the accumulator.
In the analogous art of memristor architectures and optimizations, Yue teaches:
The accumulator comprising: a shifter, an adder, and an accumulation register [Fig.5]
It would have been obvious to one of ordinary skill in the art, having the teachings of Gallo and Yue before him before the effective filing date of the claimed invention to modify the post processing components of the Gallo to use the Intra-macro accumulation circuitry as taught by Yue, in order to allow for completing operations in a macro, while also reducing memory access, improving energy efficiency and allowing adaptive precision [Yue: Sec. III and IV.B].
Regarding claim 17, the claim is directed to claim 7. A mere change in statutory class Is obvious. Claim 17 is rejected for the reasons given in claim 7.
Regarding claim 29, Gallo and Zhang disclose the invention substantially as claimed. See the discussion of claim 26 above.
Gallo discloses: an accumulation operation [Fig.1, (8) Activation function block + (9) Link controller; “the links can transfer data across the LDPUs of multiple cores to realize fully on-chip intra-layer partial sum accumulation” Sec.II] using:
a multiplier to receive data from the output register and to generate a first output [Fig.1, (8), bottom FP16 FMA with scale];
an adder to receive and sum the first output and a second output to generate a third output [Fig.1, (8), top FP16 FMA]; and
an controller to receive and store the third output and provide the third output as the second output to the adder [Fig.1, (9)].
However, Gallo does not explicitly discloses a shifter, or an accumulator within the accumulator.
In the analogous art of memristor architectures and optimizations, Yue teaches:
The accumulator comprising: a shifter, an adder, and an accumulation register [Fig.5]
It would have been obvious to one of ordinary skill in the art, having the teachings of Gallo and Yue before him before the effective filing date of the claimed invention to modify the post processing components of the Gallo to use the Intra-macro accumulation circuitry as taught by Yue, in order to allow for completing operations in a macro, while also reducing memory access, improving energy efficiency and allowing adaptive precision [Yue: Sec. III and IV.B].
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Gallo, Zhang, and Yue, in view of SFSU.
Regarding claim 8, Gallo, Zhang, and Yue disclose the invention substantially as claimed. See the discussion of claim 7 above.
Gallo, Zhang, and Yue does not explicitly disclose wherein the output block comprises a current- to-voltage converter to convert the current from the columns of the array into a voltage and an analog-to-digital converter to convert the voltage into the first digital output.
In the analogous art of analog circuit architectures for memristors systems, SFSU teaches Memristor producing current [Fig.1, MCA] and the use of a transimpedance Amp into SAR-ADC to convert current into digital [Fig.3].
It would have been obvious to one of ordinary skill in the art, having the teachings of Gallo and SFSU before him before the effective filing date of the claimed invention to modify the ADC of Gallo to use the Transimpedance Amp and SAR-ADC as taught by SFSU, in order to support parallel operations of a memristor array while optimizing power consumption, chip area, and errors for analog output circuitry [SFSU: Sec.1.0, 2.0, 3.3, 4.2, and 5].
Claim 25 are rejected under 35 U.S.C. 103 as being unpatentable over Gallo, Zhang, SFSU, and Hoang, in view of Yue.
Regarding claim 25, Gallo, Zhang, SFSU, and Hoang disclose the invention substantially as claimed. See the discussion of claim 24 above.
Gallo discloses: an accumulation operation [Fig.1, (8) Activation function block + (9) Link controller; “the links can transfer data across the LDPUs of multiple cores to realize fully on-chip intra-layer partial sum accumulation” Sec.II] using:
a multiplier to receive data from the output register and to generate a first output [Fig.1, (8), bottom FP16 FMA with scale];
an adder to receive and sum the first output and a second output to generate a third output [Fig.1, (8), top FP16 FMA]; and
an controller to receive and store the third output and provide the third output as the second output to the adder [Fig.1, (9)].
However, Gallo does not explicitly discloses a shifter, or an accumulator within the accumulator.
In the analogous art of memristor architectures and optimizations, Yue teaches:
The accumulator comprising: a shifter, an adder, and an accumulation register [Fig.5]
It would have been obvious to one of ordinary skill in the art, having the teachings of Gallo and Yue before him before the effective filing date of the claimed invention to modify the post processing components of the Gallo to use the Intra-macro accumulation circuitry as taught by Yue, in order to allow for completing operations in a macro, while also reducing memory access, improving energy efficiency and allowing adaptive precision [Yue: Sec. III and IV.B].
Claims 30-32 are rejected under 35 U.S.C. 103 as being unpatentable over Hoang, further in view of Bayat et al. (US 2020/0081711 A1, from the IDS filed 07/06/2023), hereinafter Bayat, and further in view of SFSU, and further in view of Zhang.
Regarding claim 30, Hoang discloses:
A system comprising:
an array of non-volatile memory cells arranged into rows and columns [Fig.9; shows an NVM array with rows and columns]
an output block comprising:
a first a first analog-to-digital converter to convert the first voltage into a first digital output; and a second current-to-voltage converter to convert current from the columns of the array into a second voltage and a second analog-to-digital converter to convert the second voltage into a second digital output [Fig.9, 907 and fig.16, 1607; “sample and hold circuits can use current based sensing to provide an analog output, and are in turn connected to an analog to digital converter ADC 907.” Col.10,ll.1-3]; and
an accumulator to sum the digital outputs. [“shift and add circuit 909 is used to perform accumulation operations from the values received from the ADC 907..” Col.10,ll.3-5; see fig.9/16];
However, Hoang does not explicitly disclose a first current-to-voltage converter to convert current from the columns of the array into a first voltage and a first analog-to-digital converter to convert the first voltage into a first digital output during a first time period; and a second current-to-voltage converter to convert current from the columns of the array into a second voltage and a second analog-to-digital converter to convert the second voltage into a second digital output during a second time period; and an accumulator to sum the first digital output and the second digital output.
Bayat discloses:
A system comprising:
an array of non-volatile memory cells arranged into rows and columns [Fig.2A];
a first ADC to generate a first digital output and a first register; a second ADC to generate a second digital output and a second register [Fig.2A, 106a-b ADC and 108a-b registers]; and
an neural network to handle the outputs of the buffers [Fig.1, 115; “A result of the VMM may be used for additional processing such as in neural networks.” Par.19].
It would have been obvious to one of ordinary skill in the art, having the teachings of Hoang and Bayat before him before the effective filing date of the claimed invention to include the registers after the ADCs as taught by Bayat into the system of Hoang to allow for pipelining the ADC outputs and increase performance of the matrix multiplication and allowing parallel operations of ADCs [Bayat: par.22 and 41]
However Hoang and Bayat does not explicitly disclose:
a first current-to-voltage converter to convert current from the columns of the array into a first voltage and a first analog-to-digital converter to convert the first voltage into a first digital output during a first time period; and a second current-to-voltage converter to convert current from the columns of the array into a second voltage and a second analog-to-digital converter to convert the second voltage into a second digital output during a second time period; and an accumulator to sum the first digital output and the second digital output.
In the analogous art of analog circuit architectures for memristors systems, SFSU teaches Memristor producing current [Fig.1, MCA] and the use of a transimpedance Amp into SAR-ADC to convert current into digital [Fig.3].
It would have been obvious to one of ordinary skill in the art, having the teachings of Hoang and SFSU before him before the effective filing date of the claimed invention to modify the ADC of Hoang to use the Transimpedance Amp and SAR-ADC as taught by SFSU, in order to support parallel operations of a memristor array while optimizing power consumption, chip area, and errors for analog output circuitry [SFSU: Sec.1.0, 2.0, 3.3, 4.2, and 5]. The combination disclosing: a first a first analog-to-digital converter to convert the first voltage into a first digital output; and a second current-to-voltage converter to convert current from the columns of the array into a second voltage and a second analog-to-digital converter to convert the second voltage into a second digital output
However Hoang, Bayat, and SFSU does not explicitly disclose:
a first current-to-voltage converter to convert current from the columns of the array into a first voltage and a first analog-to-digital converter to convert the first voltage into a first digital output during a first time period; and a second current-to-voltage converter to convert current from the columns of the array into a second voltage and a second analog-to-digital converter to convert the second voltage into a second digital output during a second time period; and an accumulator to sum the first digital output and the second digital output.
In the analogous art of Neural Network Acceleration and Parallelization, Zhang teaches:
A compute engine producing the first and second digital outputs [Fig.11, compute engine];
a first output register to store the first digital output during the first time period and to output the stored first digital output during the second time period; and a second output register to store the second digital output during the second time period and to output the stored second digital output during a third time period [Fig.11, discloses two output buffer sets after the compute engine; Fig.12 discloses Ping-Pong/Double output buffers; “Double buffer sets are used to realize ping-pong operations…. This is the ping-pong operation of output feature maps.”Sec.4.3]
It would have been obvious to one of ordinary skill in the art, having the teachings of Hoang, Bayat, and Zhang before him before the effective filing date of the claimed invention to modify the registers after the ADCs disclosed by Hoang and Bayat, utilize the double-buffering as taught by Zhang in order to implement double buffering of the digital outputs allowing the overlapping of data transfer time and computation time [Zhang: Sec.3.1 and 4.3].
Regarding claim 31, Hoang, Bayat, SFSU, and Zhang disclose the invention substantially as claimed. See the discussion of claim 30 above.
Hoang teaches wherein the output block comprises a column tag bit for each ADC [Fig.16, Zero Column Index (ZCI) used to de-activate components of the output circuitry; See Col.13,ll.4-47 and Col.15,ll.5-37].
In the analogous art of analog circuit architectures for memristors systems, SFSU teaches Memristor producing current [Fig.1, MCA] and the use of a transimpedance Amp into SAR-ADC to convert current into digital [Fig.3].
It would have been obvious to one of ordinary skill in the art, having the teachings of Hoang and SFSU before him before the effective filing date of the claimed invention to modify the ADC of Hoang to use the Transimpedance Amp and SAR-ADC as taught by SFSU, in order to support parallel operations of a memristor array while optimizing power consumption, chip area, and errors for analog output circuitry [SFSU: Sec.1.0, 2.0, 3.3, 4.2, and 5].
Regarding claim 32, Hoang, Bayat, SFSU, and Zhang disclose the invention substantially as claimed. See the discussion of claim 31 above.
Hoang discloses wherein the output block outputs data when the column tag bit has a first value and does not output data when the column tag bit has a second value. [Fig.16, ZCI; “so that if the index ZCI=O the corresponding S&H 1405 is de-activated (indicated by an X) and if the index ZCI=l the corresponding S&H 1405 is activated.” Col.13,ll.18-24].
In the analogous art of analog circuit architectures for memristors systems, SFSU teaches Memristor producing current [Fig.1, MCA] and the use of a transimpedance Amp into SAR-ADC to convert current into digital [Fig.3].
It would have been obvious to one of ordinary skill in the art, having the teachings of Hoang and SFSU before him before the effective filing date of the claimed invention to modify the ADC of Hoang to use the Transimpedance Amp and SAR-ADC as taught by SFSU, in order to support parallel operations of a memristor array while optimizing power consumption, chip area, and errors for analog output circuitry [SFSU: Sec.1.0, 2.0, 3.3, 4.2, and 5].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Houshmand et al. (NPL: “DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge”) discloses a pipelined memristor array + ADC into an SIMD for accumulation with an output buffer in between, with 3 time periods. See figure 8.
Ueyoshi et al. (NPL: “DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC”) discloses a pipelined memristor array + ADC into an SIMD for accumulation. See figure 15.6.3.
Texas Instruments (NPL: “How to Use the Smart Analog Combo and Transimpedance Amplifier on MSP430FR2311”) discloses the use of an current to voltage converter prior to an ADC. See pages 1-2.
Mittal (NPL: “A Survey of Cache Bypassing Techniques”) discloses various bypassing techniques such as Adaptive Bypassing. See p.6-8.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew T Caldwell can be reached at (571)272-3702. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KENNY K. BUI/Patent Examiner, Art Unit 2182 (571)270-0604
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
Prosecution Insights