DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims presented have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9, 11-14, 17, 21 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US11482497B2) in view of Hung et al. (US11302600B2).
Regarding claim 1, Fig.4 of Lin teaches a package device, comprising:
a substrate PM2/PM3/RDL2/RDL3 (col.14, lines 17-18, wherein figure 4 is inverted); a plurality of conductive pillars 110 (col.10, lines 45-46) disposed on the substrate PM2/PM3/RDL2/RDL3 side by side;
at least one bridge chip 10b/115 (col.14, lines 4-5) disposed on the substrate PM2/PM3/RDL2/RDL3, wherein the bridge chip 10b/115 has a plurality of pads 18 (Fig.2D, col.13, lines 36-37);
a photosensitive encapsulation layer 116 (col.9, lines 60-61) surrounding the bridge chip 10b/115 and the conductive pillars 110, wherein a distance between a top surface of the bridge chip 10b/115 and a top surface of the photosensitive encapsulation layer 116 is less than a distance between a top surface of one of the conductive pillars 110 and the top surface of the photosensitive encapsulation layer 116 (wherein the top surface of the conductive vias 110 contacts the connectors 104 and the top surface of the bridge chip (die 10b and underfill layer 115) is the surface of underfill layer 115 where it contacts dielectric layer 108 and having figure 4 inverted);
a redistribution layer 102/103/104/105/108/112 (col.9, lines 23-24,47, col.10, line 47) disposed on the photosensitive encapsulation layer 116, wherein the redistribution layer 102/103/104/105/108/112 directly contacts the pads 18 of the bridge chip 10b/115;
at least two active chips 101 (col.15, line 36) disposed on the redistribution layer 102/103/104/105/108/112, wherein the bridge chip 1/115 is coupled between the active chips 101; and
an encapsulant 106 (col.15, line 29) disposed on the redistribution layer 102/103/104/105/108/112, and the encapsulant 106 surrounding the active chips 101.
Lin does not teach an underfill layer disposed between the photosensitive encapsulation layer and the substrate; and
wherein the underfill layer directly contacts a sidewall of the photosensitive encapsulation layer, a sidewall of the redistribution layer, and a sidewall of the encapsulant.
Fig.1B of Hung teaches wherein an underfill 320 is disposed between the semiconductor package 200 and the circuit substrate 100 to protect the conductive terminals 310 from thermal and mechanical stresses (col.5, lines 33-36); and wherein in the underfill contacts the sidewall of the semiconductor package 200 that includes an interconnection structure 223 and an encapsulant 250.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include Hung’s underfill 320 in the teachings of Lin in order to provide protection from thermal and mechanical stresses (Hung, [col.5, lines 33-36]).
Regarding claim 2, Lin further teaches the package device as claimed in claim 1, further comprising an adhesive layer PM1 (col.14, line 17) disposed between the bridge chip 10b/115 (col.14, lines 4-5) and the substrate PM2/PM3/RDL2/RDL3 (col.14, lines 17-18).
Regarding claim 3, Lin further teaches the package device as claimed in claim 1, wherein the photosensitive encapsulation layer 116 (col.9, lines 60-61) has a plurality of first through holes (col.11, lines 3-5, wherein vias 110 are positioned in first through holes which are part of openings 108a) and a plurality of second through holes (col.11, lines 3-5, wherein pads 112 are positioned in second through holes which are part of openings 108b), one of the first through holes exposes one of the conductive pillars 110 (col.11, lines 3-5), and one of the second through holes exposes one of the pads 8 (Fig.2D, col.13, lines 36-37).
Regarding claim 4, Lin further teaches the package device as claimed in claim 3, wherein a width of one of the first through holes is greater than a width of one of the second through holes (col.11, lines 3-5, wherein vias 110 are positioned in first through holes which are part of openings 108a and have a greater width than the through holes in which conductive pads 112 are positioned).
Regarding claim 5, Lin further teaches the package device as claimed in claim 3, wherein a depth of one of the first through holes is greater than a depth of one of the second through holes (col.11, lines 3-5, wherein vias 110 are positioned in first through holes which are part of openings 108a and have greater depth than the through holes in which conductive pads 112 are positioned).
Regarding claim 6, Lin further teaches the package device as claimed in claim 1, wherein the photosensitive encapsulation layer 116 (col.9, lines 60-61) is disposed between the bridge chip 10b/115 (col.14, lines 4-5) and the redistribution layer 102/103/104/105/108/112 (col.9, lines 23-24,47, col.10, line 47).
Regarding claim 7, Lin further teaches the package device as claimed in claim 1, wherein the bridge chip 10b/115 (col.14, lines 4-5) has no bump.
Regarding claim 9, Lin further teaches the package device as claimed in claim 1, wherein the redistribution layer 102/103/104/105/108/112 (col.9, lines 23-24,47, col.10, line 47) is disposed between the bridge chip 10b/115 (col.14, lines 4-5) and the active chips 101 (col.15, line 36).
Regarding claim 11, Fig.4 of Lin teaches a manufacturing method of a package device, comprising:
forming a plurality of conductive pillars 110 (col.10, lines 45-46) and disposing at least one bridge chip 10b/115 (col.14, lines 4-5, wherein figure 4 is inverted) on a carrier 20 (col.6, line 60), wherein the bridge chip 10b/115 has a plurality of pads 18 (Fig.2D, col.13, lines 36-37);
forming a photosensitive encapsulation layer 116 (col.9, lines 60-61) on the conductive pillars 110 and the bridge chip 10b/115, wherein the photosensitive encapsulation layer 116 surrounds the bridge chip 10b/115 and the conductive pillars 110, and a distance between a top surface of the bridge chip 10b/115 and a top surface of the photosensitive encapsulation layer 116 is less than a distance between a top surface of one of the conductive pillars 110 and the top surface of the photosensitive encapsulation layer 116 (wherein the top surface of the conductive vias 110 is contacts the connectors 104 and the top surface of the bridge chip (die 10b and underfill layer 115) is the surface of underfill layer 115 where it contacts dielectric layer 108 and having Fig.4 inverted);
forming a redistribution layer 102/103/104/105/108/112 (col.9, lines 23-24,47, col.10, line 47) on the photosensitive encapsulation layer 116, wherein the redistribution layer 102/103/104/105/108/112 directly contacts the pads 18 of the bridge chip 10b/115;
disposing at least two active chips 101 (col.15, line 36) on the redistribution layer 102/103/104/105/108/112;
forming an encapsulant 106 (col.15, line 29) on the redistribution layer 102/103/104/105/108/112, wherein the encapsulant 106 surrounds the active chips 101;
removing the carrier 20 (col.6, line 62); forming a plurality of conductive terminals RDL1 (col.14, line 18) on surfaces of the conductive pillars 110 opposite to the redistribution layer 102/103/104/105/108/112;
disposing the conductive terminals RDL1 on a substrate PM2/PM3/RDL2/RDL3 (col.14, lines 17-18).
Lin does not teach forming an underfill layer between the photosensitive encapsulation layer and the substrate, wherein the underfill layer directly contacts a sidewall of the photosensitive encapsulation layer, a sidewall of the redistribution layer, and a sidewall of the encapsulant.
Fig.1B of Hung teaches wherein an underfill 320 is disposed between the semiconductor package 200 and the circuit substrate 100 to protect the conductive terminals 310 from thermal and mechanical stresses (col.5, lines 33-36); and wherein in the underfill contacts the sidewall of the semiconductor package 200 that includes an interconnection structure 223 and an encapsulant 250.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include Hung’s underfill 320 in the teachings of Lin in order to provide protection from thermal and mechanical stresses (Hung, [col.5, lines 33-36]).
Regarding claim 12, Lin further teaches the manufacturing method of the package device as claimed in claim 11, wherein disposing the bridge chip
/115 (col.14, lines 4-5) comprises bonding the bridge chip 10b/115 to the carrier 20 (col.3, lines 65-66) by an adhesive layer 21 (col.3, line 66).
Regarding claim 13, Lin further teaches the manufacturing method of the package device as claimed in claim 11, wherein forming the photosensitive encapsulation layer 116 (col.9, lines 60-61) comprises forming a plurality of first through holes and a plurality of second through holes in the photosensitive encapsulation layer 116, one of the first through holes exposes one of the conductive pillars 110 (col.11, lines 3-5), and one of the second through holes exposes one of the pads 8 (Fig.2D, col.13, lines 36-37).
Regarding claim 14, Lin further teaches the manufacturing method of the package device as claimed in claim 11, wherein the photosensitive encapsulation layer 116 (col.9, lines 60-61) is disposed between the bridge chip 10b/115 (col.14, lines 4-5) and the redistribution layer 102/103/104/105/108/112 (col.9, lines 23-24,47, col.10, line 47).
Regarding claim 17, Lin further teaches the manufacturing method of the package device as claimed in claim 11, further comprising performing a thinning process on the encapsulant 106 (col.15, line 29) to expose back surfaces of the active chips 101 (col.15, line 36). It is disclosed in paragraph 0023 wherein a planarization process (e.g., CMP) is performed to remove excess portion of the encapsulant material layer over the top surfaces of the dies 100, such that the top surfaces of the connectors 104 of the dies 100 are exposed.
Regarding claim 21, the combination of Lin and Hung the package device as claimed in claim 1, wherein each of the active chips 101 (Lin, col.15, line 36) comprises a plurality of conductive bumps 310 (Hung, col.5, line 28) bonded to the redistribution layer 102/103/104/105/108/112 (Lin, col.9, lines 23-24,47, col.10, line 47), and the redistribution layer 102/103/104/105/108/112 is between the active chips 101 and the photosensitive encapsulation layer 116 (col.9, lines 60-61).
Regarding claim 22, Lin further teaches the package device as claimed in claim 1, wherein the photosensitive encapsulation layer 116 (col.9, lines 60-61), the conductive pillars 110 (col.10, lines 45-46), and the bridge chip 10b/115 (col.14, lines 4-5) are disposed between the substrate PM2/PM3/RDL2/RDL3 (col.14, lines 17-18) and the redistribution layer 102/103/104/105/108/112 (col.9, lines 23-24,47, col.10, line 47).
Claims 8 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US11482497B2) in view of Hung et al. (US11302600B2) and in further view of Wu et al. (US20200411399A1).
Regarding claim 8, the combination of Lin and Hung does not teach wherein a Young's modulus of the encapsulant is greater than a Young's modulus of the photosensitive encapsulation layer.
Fig.1F of Wu teaches a semiconductor structure that includes a patterned dielectric layer 150 has a Young's modulus smaller than that of the insulating encapsulation 130. The patterned dielectric layer 150 may be made of polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO) or photosensitive polyimide material (para.0031).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the dielectric layer 150 and the encapsulation 130 of Wu in the teachings of Lin, as modified by Hung, because the patterned dielectric layer 150 is relatively soft to cushion forces exerted on the corners and edges of the circuit carriers 120. (Wu, [para.0031]).
Regarding claim 16, Lin further teaches the manufacturing method of the package device as claimed in claim 11, wherein a Young's modulus of the photosensitive encapsulation layer is less than a Young's modulus of the encapsulant.
Fig.1F of Wu teaches a semiconductor structure that includes a patterned dielectric layer 150 has a Young's modulus smaller than that of the insulating encapsulation 130. The patterned dielectric layer 150 may be made of polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO) or photosensitive polyimide material (para.0031).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the dielectric layer 150 and the encapsulation 130 of Wu in the teachings of Lin, as modified by Hung, because the patterned dielectric layer 150 is relatively soft to cushion forces exerted on the corners and edges of the circuit carriers 120. (Wu, [para.0031]).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US11482497B2) in view of Hung et al. (US11302600B2) and in further view of Rusli et al. (US20190189561A1).
Regarding claim 18, the combination of Lin and Hung does not teach wherein between forming the redistribution layer and disposing the active chips, the manufacturing method further comprises performing an automated optical inspection on the redistribution layer.
Fig.48 of Rusli teaches, in para.0203, wherein conductive circuits of the RDL layers of the top interposer 3010 undergo automatic optical inspection before being placed on the mold layer 3030.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the automated optical inspection of Rusli in the teachings of Lin, as modified by Hung, for the purpose of checking the connections of the conductive circuits of the RDL layers.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT KIPKEMOI RONO whose telephone number is (571)270-5977. The examiner can normally be reached Mon-Fri, 8am-5pm.
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VINCENT KIPKEMOI. RONO
Examiner
Art Unit 2891
/V.K.R./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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