Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Amendment filed on 12/29/2025 has been entered. Claims 1, 8, 9, 10, 12, 19 are amended. Claim 20 is added. Claims 1 – 20 are pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 19 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lai.
Regarding Claim 19 ( Currently Amended ), Lai teaches a semiconductor memory structure, comprising:
a substrate ( Lai, FIG. 8, 100; [0039], substrate 100 );
at least one first groove ( Lai, FIG. 1, 110; [0039], trench 110 ) disposed on an upper surface of the substrate ( Lai, FIG. 8, 100; [0039], substrate 100 );
a first dielectric layer ( Lai, FIG. 8, 210; [0039], first dielectric layer 210 ), disposed along an inner wall of the first groove ( Lai, FIG. 1, 110; [0039], trench 110 );
a second dielectric layer ( Lai, FIG. 8, 220, 230; [0039], second dielectric layer 220, third dielectric layer 230 ), disposed on a surface of the first dielectric layer ( Lai, FIG. 8, 210; [0039], first dielectric layer 210 ), to fill up the first groove ( Lai, FIG. 1, 110; [0039], trench 110 ), wherein a top portion of the first dielectric layer ( Lai, FIG. 8, 210; [0039], first dielectric layer 210 ) is lower than a top portion of the second dielectric layer ( Lai, FIG. 8, 220, 230; [0039], second dielectric layer 220, third dielectric layer 230 ) and an upper surface of the substrate ( Lai, FIG. 8, 100; [0039], substrate 100 ), and a first recess ( Lai, FIG. 1, 211; [0039], first groove 211 between the second dielectric layer 220 and the substrate 100 ) is disposed between the second dielectric layer ( Lai, FIG. 8, 220, 230; [0039], second dielectric layer 220, third dielectric layer 230 ) and the substrate ( Lai, FIG. 8, 100; [0039], substrate 100 );
a gate stack structure ( Lai, FIG. 6, 400; FIG. 7, 410, 420, 430; [0074], The functional film layer may be a stacked structure. The functional film layer may be located at a surface facing away from the substrate of fourth dielectric layer; [0075], functional film layer 400 is further fabricated on the side facing away from the substrate 100 of the polysilicon layer 300; [0078], The functional film layer in one embodiment may at least include the first wiring layer 410, the second wiring layer 420 and the hard mask layer 430 that are sequentially stacked, from the polysilicon layer 300 ), disposed on an upper surface of the substrate; and
a loading stacked structure ( Lai, [0023], Each of the at least one stacked structure includes at least a first wiring layer, a second wiring layer, and a hard mask layer that are sequentially stacked above the substrate; FIG. 7, the at least one stacked structure above the top of 220 and 230 ), disposed on the top portion of the second dielectric layer ( Lai, FIG. 8, 220, 230 );
a metal filling layer ( Lai, FIG. 4, 250; fifth layer 250 at the first groove 211, and the fifth layer 250 is located in a groove formed by an inner wall of the fourth dielectric layer 240 ), disposed between the gate stacked structure ( Lai, FIG. 6, 400; FIG. 7, 410, 420, 430 ) and the loading stacked structure ( Lai, [0023], Each of the at least one stacked structure includes at least a first wiring layer, a second wiring layer, and a hard mask layer that are sequentially stacked above the substrate; FIG. 7, the at least one stacked structure above the top of 220 and 230 ), within the first recess, to fill in a partial space of the first recess ( Lai, FIG. 1, 211; [0039], first groove 211 between the second dielectric layer 220 and the substrate 100 ) ( Lai, FIG. 4, a partial space of the groove 211 is filled by the fourth dielectric layer 240, a partial space of the groove 211 is filled by fifth layer 250 ).
Regarding Claim 20 ( New ), Lai teaches the semiconductor memory structure, as claimed in claim 19, on which this claim is dependent, Lai further teaches: further comprising:
a fourth dielectric layer ( Lai, FIG. 8, 240; [0045], fourth dielectric layer 240 ), covering the substrate, the first dielectric layer ( Lai, FIG. 8, 210 ) and the second dielectric layer ( Lai, FIG. 8, 220, 230 ), and directly contacting the gate stacked structure ( Lai, FIG. 6, 400; FIG. 7, 410, 420, 430 ), the loading stacked structure ( Lai, [0023], Each of the at least one stacked structure includes at least a first wiring layer, a second wiring layer, and a hard mask layer that are sequentially stacked above the substrate; FIG. 7, on the top portion of 220 and 230 ) and the metal filling layer ( Lai, FIG. 4, 250 ).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lai ( Pub. No. US 20210098571 A1 ), hereinafter Lai, in view of Panda ( Pub. US 20220068935 A1 ), hereinafter Panda.
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Regarding Independent Claim 1 ( Currently Amended ), Lai teaches a semiconductor memory structure, comprising:
a substrate ( Lai, FIG. 8, 100; [0039], substrate 100 );
at least one first groove ( Lai, FIG. 1, 110; [0039], trench 110 ) disposed on an upper surface of the substrate ( Lai, FIG. 8, 100; [0039], substrate 100 );
a first dielectric layer ( Lai, FIG. 8, 210; [0039], first dielectric layer 210 ), disposed along an inner wall of the first groove ( Lai, FIG. 1, 110; [0039], trench 110 );
a second dielectric layer ( Lai, FIG. 8, 220, 230; [0039], second dielectric layer 220, third dielectric layer 230 ), disposed on a surface of the first dielectric layer ( Lai, FIG. 8, 210; [0039], first dielectric layer 210 ), to fill up the first groove ( Lai, FIG. 1, 110; [0039], trench 110 ), wherein a top portion of the first dielectric layer ( Lai, FIG. 8, 210; [0039], first dielectric layer 210 ) is lower than a top portion of the second dielectric layer ( Lai, FIG. 8, 220, 230; [0039], second dielectric layer 220, third dielectric layer 230 ) and an upper surface of the substrate ( Lai, FIG. 8, 100; [0039], substrate 100 ), and a first recess ( Lai, FIG. 1, 211; [0039], first groove 211 between the second dielectric layer 220 and the substrate 100 ) is disposed between the second dielectric layer ( Lai, FIG. 8, 220, 230; [0039], second dielectric layer 220, third dielectric layer 230 ) and the substrate ( Lai, FIG. 8, 100; [0039], substrate 100 ); and
a metal filling layer ( Lai, FIG. 4, 250; fifth layer 250 at the first groove 211, and the fifth layer 250 is located in a groove formed by an inner wall of the fourth dielectric layer 240 ), disposed in the first recess ( Lai, FIG. 1, 211; [0039], first groove 211 between the second dielectric layer 220 and the substrate 100 ), to fill in a partial space of the first recess ( Lai, FIG. 1, 211; [0039], first groove 211 between the second dielectric layer 220 and the substrate 100 ) ( Lai, FIG. 4, a partial space of the groove 211 is filled by the fourth dielectric layer 240, a partial space of the groove 211 is filled by fifth layer 250 ).
a gate stacked structure ( Lai, FIG. 6, 400; FIG. 7, 410, 420, 430; [0074], The functional film layer may be a stacked structure. The functional film layer may be located at a surface facing away from the substrate of fourth dielectric layer; [0075], functional film layer 400 is further fabricated on the side facing away from the substrate 100 of the polysilicon layer 300; [0078], The functional film layer in one embodiment may at least include the first wiring layer 410, the second wiring layer 420 and the hard mask layer 430 that are sequentially stacked, from the polysilicon layer 300 ), disposed on the upper surface of the substrate, the gate stacked structure ( Lai, FIG. 6, 400; FIG. 7, 410, 420, 430 ) comprising a polysilicon layer ( Lai, [0078], first wiring layer 410 ) and a conductive layer ( Lai, [0078], second wiring layer 420 ) stacked in sequence, wherein the conductive layer ( Lai, [0078], the second wiring layer 420 may be metal (such as tungsten) ) and the metal filling layer ( Lai, FIG. 4, 250; [0053], The fifth layer 250 and the polysilicon layer 300 are made of a same material ) comprise a metal material.
Lai does not explicitly disclose:
wherein the conductive layer and the metal filling layer comprise a same metal material.
However, Panda teaches:
wherein the conductive layer and the metal filling layer comprise a same metal material ( Panda, FIG. 7; [0035], In a buried word line (bWL) device, a word line is buried below the surface of a semiconductor substrate using a metal as a gate electrode; [0070], e.g. so that the metal layer 114 and, if present, the second metal layer 116 are completely buried within the substrate 102; [0047], In one or more embodiments, the work-function metal layer comprises a metal nitride. In one more embodiments, the work-function metal layer comprises one or more of … tungsten nitride (WN), … or WN/TiN. In one more embodiments, the work-function metal layer is selected from the group consisting of … tungsten nitride (WN) ).
Lai and Panda are both considered to be analogous to the claimed invention because they are forming metal layer / gate electrode / buried word line in memory semiconductor device ( Lai, FIG. 8, [0046]; Panda, FIG. 7, [0035], [0070], [0071] ). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lai ( [0078], the second wiring layer 420 may be metal (such as tungsten) ), to incorporate the teachings of Panda ( the work-function metal layer comprises one or more of … tungsten nitride (WN) ), to implement wherein the conductive layer and the metal filling layer comprise a same metal material. Doing so would reduce bottom voids in buried word lines, and therefore production yield and reliability of memory semiconductor device can be improved.
Regarding Claim 2 ( Original ), Lai and Panda teach the semiconductor memory structure as claimed in claim 1, on which this claim is dependent, Lai further teaches:
a third dielectric layer ( Lai, FIG. 8, 500; [0081], filling layer 500 may obtained by directly filling at a side facing away from the substrate 100 of the fourth dielectric layer 240 in the semiconductor device. A material of the filling layer 500 may include, but is not limited to, an oxide ), disposed on a top portion of the metal filling layer ( Lai, FIG. 4, 250; fifth layer 250 at the first groove 211, and the fifth layer 250 is located in a groove formed by an inner wall of the fourth dielectric layer 240 ).
Lai fails to disclose a third dielectric layer, within the first recess, to fill up the first recess.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to make the third dielectric layer ( Lai, FIG. 8, 500 ) to be within the first recess ( Lai, FIG. 1, 211 ) and fill up the first recess ( Lai, FIG. 1, 211 ), by minimizing or deleting the polysilicon layer 300 ( Lai, FIG. 8, 300; [0053], polysilicon layer 300 ), since this is within the skill level of one in the art.
Regarding Claim 3 ( Original ), Lai and Panda teach the semiconductor memory structure as claimed in claim 1, on which this claim is dependent, Lai further teaches:
wherein the second dielectric layer ( Lai, FIG. 8, 220, 230; [0039], second dielectric layer 220, third dielectric layer 230 ) comprises a first sublayer ( Lai, FIG. 8, 220; [0039], second dielectric layer 220 ) and a second sublayer ( Lai, FIG. 8, 230; [0039], third dielectric layer 230 ), the first sublayer ( Lai, FIG. 8, 220; [0039], second dielectric layer 220 ) is disposed on the surface of the first dielectric layer ( Lai, FIG. 8, 210; [0039], first dielectric layer 210 ), and the second sublayer ( Lai, FIG. 8, 230; [0039], third dielectric layer 230 ) is disposed on a surface of the first sublayer ( Lai, FIG. 8, 220; [0039], second dielectric layer 220 ) and filled up the first groove ( Lai, FIG. 1, 110; [0039], trench 110 ).
Regarding Claim 4 ( Original ), Lai and Panda teach the semiconductor memory structure as claimed in claim 1, on which this claim is dependent, Lai further teaches:
wherein the first dielectric layer ( Lai, FIG. 8, 210; [0039], first dielectric layer 210 ) comprises an oxide dielectric layer ( Lai, [0044], first dielectric layer may be an oxide dielectric layer ) and/or the second dielectric layer ( Lai, FIG. 8, 220, 230; [0039], second dielectric layer 220, third dielectric layer 230 ) comprises a nitride dielectric layer ( Lai, [0044], second dielectric layer may be a nitride dielectric layer ).
Regarding Claim 5 ( Original ), Lai and Panda teach the semiconductor memory structure as claimed in claim 3, on which this claim is dependent, Lai further teaches:
wherein the first sublayer ( Lai, FIG. 8, 220; [0039], second dielectric layer 220 ) comprises a nitride dielectric layer ( Lai, [0044], second dielectric layer may be a nitride dielectric layer ), and the second sublayer ( Lai, FIG. 8, 230; [0039], third dielectric layer 230 ) comprises an oxide dielectric layer ( Lai, [0044], third dielectric layer may be an oxide dielectric layer ).
Regarding Claim 6 ( Original ), Lai and Panda teach the semiconductor memory structure as claimed in claim 1, on which this claim is dependent, Lai further teaches:
a fourth dielectric layer ( Lai, FIG. 8, 240; [0045], fourth dielectric layer 240 ), covering an inner wall of the first recess ( Lai, FIG. 1, 211; [0039], first groove 211 between the second dielectric layer 220 and the substrate 100 ), and the fourth dielectric layer ( Lai, FIG. 8, 240; [0045], fourth dielectric layer 240 ) filled in a partial space of the first recess ( Lai, FIG. 1, 211; [0039], first groove 211 between the second dielectric layer 220 and the substrate 100 ).
Regarding Claim 7 ( Previously Presented ), Lai and Panda teach the semiconductor memory structure as claimed in claim 1, on which this claim is dependent, Lai further teaches:
an insulating layer ( Lai, FIG. 8, 500; [0081], filling layer 500 ), disposed on the top portion of the second dielectric layer ( Lai, FIG. 8, 220, 230; [0039], second dielectric layer 220, third dielectric layer 230 ), the top portion of the metal filling layer ( Lai, FIG. 4, 250; fifth layer 250 at the first groove 211, and the fifth layer 250 is located in a groove formed by an inner wall of the fourth dielectric layer 240 ) and the upper surface of the substrate ( Lai, FIG. 8, 100; [0039], substrate 100 ).
Regarding Claim 8 ( Currently Amended ), Lai and Panda teach the semiconductor memory structure as claimed in claim 1, on which this claim is dependent, Lai further teaches:
a loading stacked structure ( Lai, [0023], Each of the at least one stacked structure includes at least a first wiring layer, a second wiring layer, and a hard mask layer that are sequentially stacked above the substrate ), disposed on the top portion of the second dielectric layer ( Lai, FIG. 8, 220, 230; [0039], second dielectric layer 220, third dielectric layer 230 ).
Regarding Claim 9 ( Currently Amended ), Lai and Panda teach the semiconductor memory structure as claimed in claim 8, on which this claim is dependent, Lai further teaches:
wherein the gate stacked structure ( Lai, FIG. 6, 400; FIG. 7, 410, 420, 430; [0074], The functional film layer may be a stacked structure. The functional film layer may be located at a surface facing away from the substrate of fourth dielectric layer; [0075], functional film layer 400 is further fabricated on the side facing away from the substrate 100 of the polysilicon layer 300; [0078], The functional film layer in one embodiment may at least include the first wiring layer 410, the second wiring layer 420 and the hard mask layer 430 that are sequentially stacked, from the polysilicon layer 300 ) further comprises a first mask layer ( Lai, [0078], hard mask layer 430 ) stacked on the conductive layer ( Lai, [0078], second wiring layer 420 ) and/or, the loading stacked structure ( Lai, [0023], Each of the at least one stacked structure includes at least a first wiring layer, a second wiring layer, and a hard mask layer that are sequentially stacked above the substrate ) comprises a second polysilicon layer ( Lai, [0023], first wiring layer ), a second conductive layer ( Lai, [0023], second wiring layer ) and a second mask layer ( Lai, [0023], hard mask layer) stacked sequentially from bottom to top in the direction being perpendicular to the upper surface of the substrate ( Lai, FIG. 8, 100; [0039], substrate 100 ).
Regarding Claim 10 ( Currently Amended ), Lai and Panda teach the semiconductor memory structure as claimed in claim 9, on which this claim is dependent, Lai further teaches:
wherein the first conductive layer ( Lai, [0078], second wiring layer 420 ) and the second conductive layer ( Lai, [0023], second wiring layer; [0053], The fifth layer 250 and the polysilicon layer 300 are made of a same material ) comprises the same metal material.
Regarding Claim 11 ( Original ), Lai and Panda teach the semiconductor memory structure as claimed in claim 8, on which this claim is dependent, Lai further teaches:
wherein the gate stacked structure ( Lai, FIG. 6, 400; FIG. 7, 410, 420, 430; [0074], The functional film layer may be a stacked structure. The functional film layer may be located at a surface facing away from the substrate of fourth dielectric layer; [0075], functional film layer 400 is further fabricated on the side facing away from the substrate 100 of the polysilicon layer 300; [0078], The functional film layer in one embodiment may at least include the first wiring layer 410, the second wiring layer 420 and the hard mask layer 430 that are sequentially stacked, from the polysilicon layer 300 ) crosses over the metal filling layer ( Lai, FIG. 4, 250; fifth layer 250 at the first groove 211, and the fifth layer 250 is located in a groove formed by an inner wall of the fourth dielectric layer 240 ).
Regarding Independent Claim 12 ( Currently Amended ), Lai teaches a method of fabricating a semiconductor memory structure, comprising following steps:
providing a substrate ( Lai, FIG. 8, 100; [0039], substrate 100 ), with a first groove ( Lai, FIG. 1, 110; [0039], trench 110 ) being formed at an upper surface of the substrate ( Lai, FIG. 8, 100; [0039], substrate 100 );
sequentially forming a first dielectric material layer ( Lai, FIG. 8, 210; [0039], first dielectric layer 210 ), a second dielectric material layer ( Lai, FIG. 8, 220, 230; [0039], second dielectric layer 220, third dielectric layer 230 ) along an inner wall of the first groove ( Lai, FIG. 1, 110; [0039], trench 110 );
partially removing the first dielectric material layer ( Lai, FIG. 8, 210; [0039], first dielectric layer 210; [0040], a first dielectric layer and a second dielectric layer that are flush at the top may be formed in fabricating the shallow trench isolation structure. Then, the topmost surface of the first dielectric layer is etched to form the first groove ) and the second dielectric material layer ( Lai, FIG. 8, 220, 230; [0039], second dielectric layer 220, third dielectric layer 230 ), with an edge corner of a top portion of the first groove ( Lai, FIG. 1, 110; [0039], trench 110 ) being arc-shaped to correspondingly form a first dielectric layer ( Lai, FIG. 8, 210; [0039], first dielectric layer 210 ) and a second dielectric layer ( Lai, FIG. 8, 220, 230; [0039], second dielectric layer 220, third dielectric layer 230 ) respectively, and with a top portion of the first dielectric layer ( Lai, FIG. 8, 210; [0039], first dielectric layer 210 ) being lower than a top portion of the second dielectric layer ( Lai, FIG. 8, 220, 230; [0039], second dielectric layer 220, third dielectric layer 230 ) and the upper surface of the substrate ( Lai, FIG. 8, 100; [0039], substrate 100 ) to form a first recess ( Lai, FIG. 1, 211; [0039], first groove 211 between the second dielectric layer 220 and the substrate 100 ) between the second dielectric layer ( Lai, FIG. 8, 220, 230; [0039], second dielectric layer 220, third dielectric layer 230 ) and the substrate ( Lai, FIG. 8, 100; [0039], substrate 100 ); and
forming a metal filling layer ( Lai, FIG. 4, 250; fifth layer 250 at the first groove 211, and the fifth layer 250 is located in a groove formed by an inner wall of the fourth dielectric layer 240 ) in the first recess ( Lai, FIG. 1, 211; [0039], first groove 211 between the second dielectric layer 220 and the substrate 100 ) to partially fill in the first recess ( Lai, FIG. 1, 211; [0039], first groove 211 between the second dielectric layer 220 and the substrate 100 ).
forming a gate stacked structure ( Lai, FIG. 6, 400; FIG. 7, 410, 420, 430; [0074], The functional film layer may be a stacked structure. The functional film layer may be located at a surface facing away from the substrate of fourth dielectric layer; [0075], functional film layer 400 is further fabricated on the side facing away from the substrate 100 of the polysilicon layer 300; [0078], The functional film layer in one embodiment may at least include the first wiring layer 410, the second wiring layer 420 and the hard mask layer 430 that are sequentially stacked, from the polysilicon layer 300 ) on the upper surface of the substrate, the gate stacked structure ( Lai, FIG. 6, 400; FIG. 7, 410, 420, 430 ) comprising a polysilicon layer ( Lai, [0078], first wiring layer 410 ) and a conductive layer ( Lai, [0078], second wiring layer 420 ) stacked in sequence, wherein the conductive layer ( Lai, [0078], the second wiring layer 420 may be metal (such as tungsten) ) and the metal filling layer ( Lai, FIG. 4, 250; [0053], The fifth layer 250 and the polysilicon layer 300 are made of a same material ) comprise a metal material.
Lai does not explicitly disclose:
wherein the conductive layer and the metal filling layer comprise a same metal material.
However, Panda teaches:
wherein the conductive layer and the metal filling layer comprise a same metal material ( Panda, FIG. 7; [0035], In a buried word line (bWL) device, a word line is buried below the surface of a semiconductor substrate using a metal as a gate electrode; [0070], e.g. so that the metal layer 114 and, if present, the second metal layer 116 are completely buried within the substrate 102; [0047], In one or more embodiments, the work-function metal layer comprises a metal nitride. In one more embodiments, the work-function metal layer comprises one or more of … tungsten nitride (WN), … or WN/TiN. In one more embodiments, the work-function metal layer is selected from the group consisting of … tungsten nitride (WN) ).
Lai and Panda are both considered to be analogous to the claimed invention because they are forming metal layer / gate electrode / buried word line in memory semiconductor device ( Lai, FIG. 8, [0046]; Panda, FIG. 7, [0035], [0070], [0071] ). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lai ( Lai, [0078], the second wiring layer 420 may be metal (such as tungsten) ), to incorporate the teachings of Panda ( the work-function metal layer comprises one or more of … tungsten nitride (WN) ), to implement wherein the conductive layer and the metal filling layer comprise a same metal material. Doing so would reduce bottom voids in buried word lines, and therefore production yield and reliability of memory semiconductor device can be improved.
Regarding Claim 13 ( Original ), Lai and Panda teach the method of fabricating the semiconductor memory structure as claimed in claim 12, on which this claim is dependent, Lai further teaches: comprising following steps:
wherein after forming the metal filling layer ( Lai, FIG. 4, 250; fifth layer 250 at the first groove 211, and the fifth layer 250 is located in a groove formed by an inner wall of the fourth dielectric layer 240 ) in the first recess ( Lai, FIG. 1, 211; [0039], first groove 211 between the second dielectric layer 220 and the substrate 100 ) further comprising following steps:
forming a third dielectric layer ( Lai, FIG. 8, 500; [0081], filling layer 500 may obtained by directly filling at a side facing away from the substrate 100 of the fourth dielectric layer 240 in the semiconductor device. A material of the filling layer 500 may include, but is not limited to, an oxide ) on a top portion of the metal filling layer ( Lai, FIG. 4, 250; fifth layer 250 at the first groove 211, and the fifth layer 250 is located in a groove formed by an inner wall of the fourth dielectric layer 240 ) .
Lai fails to disclose the third dielectric layer filled up the first recess.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to make the third dielectric layer ( Lai, FIG. 8, 500 ) to fill up the first recess ( Lai, FIG. 1, 211 ), by minimizing or deleting the polysilicon layer 300 ( Lai, FIG. 8, 300; [0053], polysilicon layer 300 ), since this is within the skill level of one in the art.
Regarding Claim 14 ( Original ), Lai and Panda teach the method of fabricating the semiconductor memory structure as claimed in claim 12, on which this claim is dependent, Lai further teaches:
wherein partially removing the first dielectric material layer ( Lai, FIG. 8, 210; [0039], first dielectric layer 210; [0040], a first dielectric layer and a second dielectric layer that are flush at the top may be formed in fabricating the shallow trench isolation structure. Then, the topmost surface of the first dielectric layer is etched to form the first groove ) and the second dielectric material layer ( Lai, FIG. 8, 220, 230; [0039], second dielectric layer 220, third dielectric layer 230 ) comprises following steps:
using at least one of a dry etching process and a wet etching process, to partially removing the first dielectric material layer ( Lai, FIG. 8, 210; [0039], first dielectric layer 210; [0040], a first dielectric layer and a second dielectric layer that are flush at the top may be formed in fabricating the shallow trench isolation structure. Then, the topmost surface of the first dielectric layer is etched to form the first groove ) and the second dielectric material layer ( Lai, FIG. 8, 220, 230; [0039], second dielectric layer 220, third dielectric layer 230 ), with an etching rate of an etching selecting gas or an etching liquid related to the first dielectric material layer ( Lai, FIG. 8, 210; [0039], first dielectric layer 210 ) being greater ( Lai, [0040], a first dielectric layer and a second dielectric layer that are flush at the top may be formed in fabricating the shallow trench isolation structure. Then, the topmost surface of the first dielectric layer is etched to form the first groove ) than that of the second dielectric material layer ( Lai, FIG. 8, 220, 230; [0039], second dielectric layer 220, third dielectric layer 230 ) ( Lai, [0039], A topmost surface of the first dielectric layer 210 is lower than a topmost surface of the second dielectric layer 220 and a top surface of the substrate 100, to form a first groove 211 between the second dielectric layer 220 and the substrate 100. An edge corner between the top surface of the substrate 100 and the inner wall of each of the at least one trench 110 is in a shape of a fillet curve 120 ).
Regarding Claim 15 ( Original ), Lai and Panda teach the method of fabricating the semiconductor memory structure as claimed in claim 12, on which this claim is dependent, Lai further teaches:
wherein the second dielectric layer ( Lai, FIG. 8, 220, 230; [0039], second dielectric layer 220, third dielectric layer 230 ) comprises a first sublayer ( Lai, FIG. 8, 220; [0039], second dielectric layer 220 ) and a second sublayer ( Lai, FIG. 8, 230; [0039], third dielectric layer 230 ), while forming the second dielectric layer ( Lai, FIG. 8, 220, 230; [0039], second dielectric layer 220, third dielectric layer 230 ) comprises following steps:
forming the first sublayer ( Lai, FIG. 8, 220; [0039], second dielectric layer 220 ) on the surface of a first dielectric layer ( Lai, FIG. 8, 210; [0039], first dielectric layer 210 ); and
forming the second sublayer ( Lai, FIG. 8, 230; [0039], third dielectric layer 230 ) on a surface of the first sublayer ( Lai, FIG. 8, 220; [0039], second dielectric layer 220 ), and the second sublayer ( Lai, FIG. 8, 230; [0039], third dielectric layer 230 ) filled up the first groove ( Lai, FIG. 1, 110; [0039], trench 110 ).
Regarding Claim 16 ( Original ), Lai and Panda teach the method of fabricating the semiconductor memory structure as claimed in claim 12, on which this claim is dependent, Lai further teaches:
before forming the metal filling layer ( Lai, FIG. 4, 250; fifth layer 250 at the first groove 211, and the fifth layer 250 is located in a groove formed by an inner wall of the fourth dielectric layer 240 ) in the first recess ( Lai, FIG. 1, 211; [0039], first groove 211 between the second dielectric layer 220 and the substrate 100 ) further comprising following steps:
forming a fourth dielectric layer ( Lai, FIG. 8, 240; [0045], fourth dielectric layer 240 ) on an inner wall of the first recess ( Lai, FIG. 1, 211; [0039], first groove 211 between the second dielectric layer 220 and the substrate 100 ).
Regarding Claim 17 ( Original ), Lai and Panda teach the method of fabricating the semiconductor memory structure as claimed in claim 12, on which this claim is dependent, Lai further teaches:
wherein forming the metal filling layer ( Lai, FIG. 4, 250; fifth layer 250 at the first groove 211, and the fifth layer 250 is located in a groove formed by an inner wall of the fourth dielectric layer 240 ) in the first recess ( Lai, FIG. 1, 211; [0039], first groove 211 between the second dielectric layer 220 and the substrate 100 ) comprises:
forming a metal layer in the first recess ( Lai, FIG. 1, 211; [0039], first groove 211 between the second dielectric layer 220 and the substrate 100 ), on the top portion of the second dielectric and on the upper surface of the substrate ( Lai, FIG. 8, 100; [0039], substrate 100 ), the metal layer at least filled up the first recess ( Lai, FIG. 1, 211; [0039], first groove 211 between the second dielectric layer 220 and the substrate 100 ); and
performing an etching back process ( Lai, FIG. 4, 250; [0051], The shallow trench isolation structure further includes a fifth layer 250 at the first groove 211, and the fifth layer 250 is located in a groove formed by an inner wall of the fourth dielectric layer 240 ) on the metal layer, to remain the metal layer filled in the first recess ( Lai, FIG. 1, 211; [0039], first groove 211 between the second dielectric layer 220 and the substrate 100 ) to form the metal filling layer ( Lai, FIG. 4, 250; fifth layer 250 at the first groove 211, and the fifth layer 250 is located in a groove formed by an inner wall of the fourth dielectric layer 240 ).
Regarding Claim 18 ( Original ), Lai and Panda teach the method of fabricating the semiconductor memory structure as claimed in claim 13, on which this claim is dependent, Lai further teaches:
wherein forming the third dielectric layer ( Lai, FIG. 8, 500; [0081], filling layer 500 may obtained by directly filling at a side facing away from the substrate 100 of the fourth dielectric layer 240 in the semiconductor device. A material of the filling layer 500 may include, but is not limited to, an oxide ) on the top portion of the metal filling layer ( Lai, FIG. 4, 250; fifth layer 250 at the first groove 211, and the fifth layer 250 is located in a groove formed by an inner wall of the fourth dielectric layer 240 ) comprises:
forming a dielectric material layer ( Lai, FIG. 8, 500; [0081], A material of the filling layer 500 may include, but is not limited to, an oxide ) on the top portion of the metal filling layer ( Lai, FIG. 4, 250; fifth layer 250 at the first groove 211, and the fifth layer 250 is located in a groove formed by an inner wall of the fourth dielectric layer 240 ), the top portion of the second dielectric layer ( Lai, FIG. 8, 220, 230; [0039], second dielectric layer 220, third dielectric layer 230 ) and the upper surface of the substrate ( Lai, FIG. 8, 100; [0039], substrate 100 ), the dielectric material layer ( Lai, FIG. 8, 500; [0081], A material of the filling layer 500 may include, but is not limited to, an oxide ) at least filled up the first recess ( Lai, FIG. 1, 211; [0039], first groove 211 between the second dielectric layer 220 and the substrate 100 ); and
performing an etching back process ( Lai, [0080], In one embodiment, the hard mask layer 430 may be a planarized layer, and the surfaces of the hard mask layers facing away from the substrate 100 may be coplanar. The present disclosure is not limited thereto ) on the dielectric material layer ( Lai, FIG. 8, 500; [0081], A material of the filling layer 500 may include, but is not limited to, an oxide ).
Lai fails to disclose to remain the dielectric material layer filled in the first recess to form the third dielectric layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to make the third dielectric layer ( Lai, FIG. 8, 500 ) to be on the top portion of the metal filling layer ( Lai, FIG. 4, 250 ), by minimizing or deleting the polysilicon layer 300 ( Lai, FIG. 8, 300; [0053], polysilicon layer 300 ); and perform an etching back process based on the purpose of planarized layer or coplanar, to reduce the thickness of the third dielectric layer ( Lai, FIG. 8, 500 ), and remain the third dielectric layer ( Lai, FIG. 8, 500 ) filled in the first recess ( Lai, FIG. 1, 211 ); since this is within the skill level of one in the art.
Response to Arguments
Applicant’s argument for claims 1, 12: page 9, line 7, cited “ Claim 1 has been amended to …, and to recite features "a gate stacked structure, disposed on the upper surface of the substrate, the gate stacked structure comprising a polysilicon layer and a conductive layer stacked in sequence, wherein the conductive layer and the metal filling layer comprise a same metal material". ”; page 11, line 2, cited “ In summary, since the aforementioned cited references do not explicitly or inherently disclose the said features in current claim 1 of the instant patent application, the Examiner is requested to allow Claim 1. ”.
Examiner’s response: please refer to claims 1, 12 in Claim Rejections - 35 USC § 103 of this office action, for instance, claim 1, cited “
a gate stacked structure ( Lai, FIG. 6, 400; FIG. 7, 410, 420, 430; [0074], The functional film layer may be a stacked structure. The functional film layer may be located at a surface facing away from the substrate of fourth dielectric layer; [0075], functional film layer 400 is further fabricated on the side facing away from the substrate 100 of the polysilicon layer 300; [0078], The functional film layer in one embodiment may at least include the first wiring layer 410, the second wiring layer 420 and the hard mask layer 430 that are sequentially stacked, from the polysilicon layer 300 ), disposed on the upper surface of the substrate, the gate stacked structure ( Lai, FIG. 6, 400; FIG. 7, 410, 420, 430 ) comprising a polysilicon layer ( Lai, [0078], first wiring layer 410 ) and a conductive layer ( Lai, [0078], second wiring layer 420 ) stacked in sequence, wherein the conductive layer ( Lai, [0078], the second wiring layer 420 may be metal (such as tungsten) ) and the metal filling layer ( Lai, FIG. 4, 250; [0053], The fifth layer 250 and the polysilicon layer 300 are made of a same material ) comprise a
Lai does not explicitly disclose:
wherein the conductive layer and the metal filling layer comprise a same metal material.
However, Panda teaches:
wherein the conductive layer and the metal filling layer comprise a same metal material ( Panda, FIG. 7; [0035], In a buried word line (bWL) device, a word line is buried below the surface of a semiconductor substrate using a metal as a gate electrode; [0070], e.g. so that the metal layer 114 and, if present, the second metal layer 116 are completely buried within the substrate 102; [0047], In one or more embodiments, the work-function metal layer comprises a metal nitride. In one more embodiments, the work-function metal layer comprises one or more of … tungsten nitride (WN), … or WN/TiN. In one more embodiments, the work-function metal layer is selected from the group consisting of … tungsten nitride (WN) ).
Lai and Panda are both considered to be analogous to the claimed invention because they are forming metal layer / gate electrode / buried word line in memory semiconductor device ( Lai, FIG. 8, [0046]; Panda, FIG. 7, [0035], [0070], [0071] ). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lai ( Lai, [0078], the second wiring layer 420 may be metal (such as tungsten) ), to incorporate the teachings of Panda ( the work-function metal layer comprises one or more of … tungsten nitride (WN) ), to implement wherein the conductive layer and the metal filling layer comprise a same metal material. Doing so would reduce bottom voids in buried word lines, and therefore production yield and reliability of memory semiconductor device can be improved. ”.
Applicant’s argument for claim 19: page 14, line 8 from bottom, cited “ In other words, the cited Lai does not disclose the features "a gate stack structure, disposed on an upper surface of the substrate; and a loading stacked structure, disposed on the top portion of the second dielectric layer, wherein the metal filling layer is disposed between the gate stacked structure and the loading stacked structure" currently amended in claim 19 ”.
Examiner’s response: please refer to claim 19 in Claim Rejections - 35 USC § 103 of this office action, cited “
a gate stack structure ( Lai, FIG. 6, 400; FIG. 7, 410, 420, 430; [0074], The functional film layer may be a stacked structure. The functional film layer may be located at a surface facing away from the substrate of fourth dielectric layer; [0075], functional film layer 400 is further fabricated on the side facing away from the substrate 100 of the polysilicon layer 300; [0078], The functional film layer in one embodiment may at least include the first wiring layer 410, the second wiring layer 420 and the hard mask layer 430 that are sequentially stacked, from the polysilicon layer 300 ), disposed on an upper surface of the substrate; and
a loading stacked structure ( Lai, [0023], Each of the at least one stacked structure includes at least a first wiring layer, a second wiring layer, and a hard mask layer that are sequentially stacked above the substrate; FIG. 7, the at least one stacked structure above the top of 220 and 230 ), disposed on the top portion of the second dielectric layer ( Lai, FIG. 8, 220, 230 ) ;
a metal filling layer ( Lai, FIG. 4, 250; fifth layer 250 at the first groove 211, and the fifth layer 250 is located in a groove formed by an inner wall of the fourth dielectric layer 240 ), disposed between the gate stacked structure ( Lai, FIG. 6, 400; FIG. 7, 410, 420, 430 ) and the loading stacked structure ( Lai, [0023], Each of the at least one stacked structure includes at least a first wiring layer, a second wiring layer, and a hard mask layer that are sequentially stacked above the substrate; FIG. 7, the at least one stacked structure above the top of 220 and 230 ) ”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm.
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/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817