DETAILED ACTION
Response to Arguments
Applicant’s arguments with respect to claims 1-10 and 20-29 have been considered but are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 10, 20-26, and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Lilak et al. (US 20200395386 A1), hereinafter “Lilak,” in view of HuangFu (US 20160329239 A1), hereinafter “Huang Fu.”
Re: Independent Claim 1 Lilak discloses a multi-layer stacked semiconductor device comprising (See Fig. 1H):
a first integrated circuit device (Fig. 1H shows a first integrated circuit device having gate 106);
a bonding insulator formed upon the first integrated circuit device, wherein the bonding insulator comprises an insulating material layer and an etch stop layer (Fig. 1H shows insulator layer 128 and etch stop layer 121 formed upon a first integrated circuit device having gate 106; ¶0080: Insulator layer 302, may for example, be one or more dielectric materials known to be suitable for wafer bonding applications and deposited by plasma enhanced chemical vapor deposition (PECVD) or chemical vapor deposition (CVD)…The etch stop layer 121 may include a dielectric layer such as silicon nitride, silicon carbide or a carbon doped silicon nitride.);
…
a second integrated circuit device formed over the first integrated circuit device in a stacked configuration (Fig. 1H shows a second integrated circuit device having gate 136 which is formed over the first IC device having gate 106); and
a bonding insulator layer formed between the second integrated circuit device and the insulating material layer (Fig. 5A shows insulator layer 402; ¶0081: FIG. 4 illustrates a cross sectional view of a wafer 400 including an insulator layer 402 formed on a semiconductor substrate 126; ¶0082: FIG. 5A illustrates a cross sectional view of the wafer 400 bonded onto the first insulator layer 300);
wherein the insulating material layer and the bonding insulator layer are bonded adjacent to one another (Fig. 5A shows layer 302 and 402 bonded adjacent to each other; ¶0082: FIG. 5A illustrates a cross sectional view of the wafer 400 bonded onto the first insulator layer 300).
However, Lilak does not specifically disclose one or more portions formed below a top surface of the etch stop layer, the one or more portions including sacrificial insulating material filling irregularities in the top surface of the etch stop layer;
In a similar field of endeavor, HuangFu discloses one or more portions formed below a top surface of the etch stop layer, the one or more portions including sacrificial insulating material filling irregularities in the top surface of the etch stop layer (Fig. 5D shows an etch stop layer 130; Fig. 5E shows an oxide layer 122, i.e., insulating material, which fills cavities below a top surface of the etch stop layer.; ¶0078: a second oxide layer 122 may be further grown on the patterned etch-stop layer 130, and flattening processing and chemical surface processing may be performed on the further grown second oxide layer 122, so that the first silicon substrate 110 has a smooth surface.);
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date to have modified the device of Lilak by including a sacrificial insulating layer on top of the etch stop layer, such as the oxide layer disclose by HuangFu, for the purpose of filling in irregularities in order to ensure a smooth surface during bonding (See HuangFu, ¶0078).
Re: Claim 2, the combination of Lilak and HuangFu discloses the semiconductor device of claim 1.
Lilak further discloses wherein the insulating material layer comprises a material that is different with respect to a material of the bonding insulator layer (Fig. 5A shows an insulating layer 128 which includes insulating material layer (302) and a bonding insulator layer (402); ¶0071: Insulator layer 128, may for example, be one or more (i.e., different materials) dielectric materials).
Re: Claim 3, the combination of Lilak and HuangFu discloses the semiconductor device of claim 1.
Lilak further discloses wherein the insulating material layer comprises a material that is the same with respect to a material of the bonding insulator layer (Fig. 5A shows an insulating layer 128 which includes insulating material layer (302) and a bonding insulator layer (402); ¶0071: Insulator layer 128, may for example, be one (i.e., the same material) or more dielectric materials).
Re: Claim 4, the combination of Lilak and HuangFu discloses the semiconductor device of claim 1.
Lilak further discloses wherein the insulating material layer comprises a silicon oxide material (See Fig. 5A; ¶0071: dielectric materials include silicon dioxide, silicon nitride, silicon oxynitride, carbon doped nitride and carbon doped oxide.).
Re: Claim 5, the combination of Lilak and HuangFu discloses the semiconductor device of claim 1.
Lilak further discloses wherein the first integrated circuit device comprises a first layer field-effect transistor (FET) and wherein the second integrated circuit device comprises a second layer FET (Fig. 1H shows FET’s 136 and 106; ¶0068: Depending on whether transistor 100B includes an N-channel MOSFET or a P-channel MOSFET, gate electrode 136B may include a P-type work function metal or an N-type work function metal to provide a PMOS or an NMOS transistor 100B.).
Re: Claim 6, the combination of Lilak and HuangFu discloses the semiconductor device of claim 5.
Lilak further discloses further comprising a local interconnect electrical connection connecting the first layer FET to the second layer FET (¶0078: FIG. 1K illustrates a cross-sectional illustration of a device structure 160 including a transistor 160B, where the metallization structure 144 is coupled (i.e., local interconnect electrical connection) with the epitaxial structure 134 and the first terminal 114 of the device structure 100A.).
Re: Claim 7, the combination of Lilak and HuangFu discloses the semiconductor device of claim 6.
Lilak further discloses wherein the local interconnect electrical connection connects a terminal of the first layer FET to a terminal of the second layer FET (¶0078: FIG. 1K illustrates a cross-sectional illustration of a device structure 160 including a transistor 160B, where the metallization structure 144 is coupled with the epitaxial structure 134 and the first terminal 114 of the device structure 100A.).
Re: Claim 10, the combination of Lilak and HuangFu discloses the semiconductor device of claim 1.
Lilak further discloses wherein the etch stop layer has a thickness of about 10 nm to about 20 nm (¶0080: The thickness of the etch stop layer 121 may range from 10 nm-50 nm).
Re: Independent Claim 20, Lilak discloses a semiconductor chip comprising a multi-layer stacked semiconductor device, the multi-layer stacked semiconductor device (¶0130: The integrated circuit die may include one or more device systems such as a device structure including a transistor 100B and 160B with an epitaxial structure 130 and a metallization structure 140 that couples with a terminal contact 118 of a transistor 100A for example.) comprising:
a first integrated circuit device (Fig. 1H shows a first integrated circuit device having gate 106);
a bonding insulator formed upon the first integrated circuit device, wherein the bonding insulator comprises an insulating material layer and an etch stop layer (Fig. 5A shows insulator layer 402; See ¶0081 and ¶0082);
…
a second integrated circuit device formed over the first integrated circuit device in a stacked configuration (Fig. 1H shows a second integrated circuit device having gate 136 which is formed over the first IC device having gate 106); and
a bonding insulator layer formed between the second integrated circuit device and the insulating material layer (Fig. 5A shows insulator layer 402; See ¶0081; ¶0082: FIG. 5A illustrates a cross sectional view of the wafer 400 bonded onto the first insulator layer 300);
wherein the insulating material layer and the bonding insulator layer are bonded adjacent to one another (Fig. 5A shows layer 302 and 402 bonded adjacent to each other; ¶0082: FIG. 5A illustrates a cross sectional view of the wafer 400 bonded onto the first insulator layer 300).
However, Lilak does not specifically disclose one or more portions formed below a top surface of the etch stop layer, the one or more portions including sacrificial insulating material filling irregularities in the top surface of the etch stop layer;
In a similar field of endeavor, HuangFu discloses one or more portions formed below a top surface of the etch stop layer, the one or more portions including sacrificial insulating material filling irregularities in the top surface of the etch stop layer (Fig. 5D shows an etch stop layer 130; Fig. 5E shows an oxide layer 122, i.e., insulating material, which fills cavities below a top surface of the etch stop layer.; ¶0078: a second oxide layer 122 may be further grown on the patterned etch-stop layer 130, and flattening processing and chemical surface processing may be performed on the further grown second oxide layer 122, so that the first silicon substrate 110 has a smooth surface.);
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date to have modified the device of Lilak by including a sacrificial insulating layer on top of the etch stop layer, such as the oxide layer disclose by HuangFu, for the purpose of filling in irregularities in order to ensure a smooth surface during bonding (See HuangFu, ¶0078).
Re: Claim 21, the combination of Lilak and HuangFu discloses the semiconductor device of claim 20.
Lilak further discloses wherein the insulating material layer comprises a material that is different with respect to a material of the bonding insulator layer (Fig. 5A shows an insulating layer 128 which includes insulating material layer (302) and a bonding insulator layer (402); ¶0071: Insulator layer 128, may for example, be one or more (i.e., different materials) dielectric materials).
Re: Claim 22, the combination of Lilak and HuangFu discloses the semiconductor device of claim 20.
Lilak further discloses wherein the insulating material layer comprises a material that is the same with respect to a material of the bonding insulator layer (Fig. 5A shows an insulating layer 128 which includes insulating material layer (302) and a bonding insulator layer (402); ¶0071: Insulator layer 128, may for example, be one (i.e., the same material) or more dielectric materials).
Re: Claim 23, the combination of Lilak and HuangFu discloses the semiconductor device of claim 20.
Lilak further discloses wherein the insulating material layer comprises a silicon oxide material (See Fig. 5A; ¶0071: dielectric materials include silicon dioxide, silicon nitride, silicon oxynitride, carbon doped nitride and carbon doped oxide.).
Re: Claim 24, the combination of Lilak and HuangFu discloses the semiconductor device of claim 20.
Lilak further discloses wherein the first integrated circuit device comprises a first layer field-effect transistor (FET) and wherein the second integrated circuit device comprises a second layer FET (Fig. 1H shows FET’s 136 and 106; See ¶0068: N-channel MOSFET or a P-channel MOSFET).
Re: Claim 25, the combination of Lilak and HuangFu discloses the semiconductor device of claim 24.
Lilak also discloses further comprising a local interconnect electrical connection connecting the first layer FET to the second layer FET (¶0078: FIG. 1K illustrates a cross-sectional illustration of a device structure 160 including a transistor 160B, where the metallization structure 144 is coupled (i.e., local interconnect electrical connection) with the epitaxial structure 134 and the first terminal 114 of the device structure 100A.).
Re: Claim 26, the combination of Lilak and HuangFu discloses the semiconductor device of claim 25.
Lilak further discloses wherein the local interconnect electrical connection connects a terminal of the first layer FET to a terminal of the second layer FET (¶0078: FIG. 1K illustrates a cross-sectional illustration of a device structure 160 including a transistor 160B, where the metallization structure 144 is coupled with the epitaxial structure 134 and the first terminal 114 of the device structure 100A.).
Re: Independent Claim 29, Lilak discloses a multi-layer stacked semiconductor device (¶0130: The integrated circuit die may include one or more device systems such as a device structure including a transistor 100B and 160B with an epitaxial structure 130 and a metallization structure 140 that couples with a terminal contact 118 of a transistor 100A for example.) comprising:
a first integrated circuit device (Fig. 1H shows a first integrated circuit device having gate 106);
a bonding insulator formed upon the first integrated circuit device, wherein the bonding insulator comprises an insulating material layer and an etch stop layer (Fig. 5A shows insulator layer 402; See ¶0081 and ¶0082);
…
a second integrated circuit device formed over the first integrated circuit device in a stacked configuration (Fig. 1H shows a second integrated circuit device having gate 136 which is formed over the first IC device having gate 106); and
a bonding insulator layer formed between the second integrated circuit device and the insulating material layer (Fig. 5A shows insulator layer 402; See ¶0081; ¶0082: FIG. 5A illustrates a cross sectional view of the wafer 400 bonded onto the first insulator layer 300); and
a bonding line between the insulating material layer and the bonding insulator layer (Fig. 5A shows a bonding line between 402 and 302).
However, Lilak does not specifically disclose one or more portions formed below a top surface of the etch stop layer, the one or more portions including sacrificial insulating material filling irregularities in the top surface of the etch stop layer;
In a similar field of endeavor, HuangFu discloses one or more portions formed below a top surface of the etch stop layer, the one or more portions including sacrificial insulating material filling irregularities in the top surface of the etch stop layer (Fig. 5D shows an etch stop layer 130; Fig. 5E shows an oxide layer 122, i.e., insulating material, which fills cavities below a top surface of the etch stop layer.; ¶0078: a second oxide layer 122 may be further grown on the patterned etch-stop layer 130, and flattening processing and chemical surface processing may be performed on the further grown second oxide layer 122, so that the first silicon substrate 110 has a smooth surface.);
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date to have modified the device of Lilak by including a sacrificial insulating layer on top of the etch stop layer, such as the oxide layer disclose by HuangFu, for the purpose of filling in irregularities in order to ensure a smooth surface during bonding (See HuangFu, ¶0078).
Claims 8 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Lilak et al. (US 20200395386 A1) in view of HuangFu (US 20160329239 A1), and further in view of Or-Bach et al. (US 20230170244 A1), hereinafter “Or-Bach.”
Re: Claim 8, the combination of Lilak and HuangFu discloses the semiconductor device of claim 5.
However, the combination does not disclose wherein the first layer FET and the second layer FET are selected from planar FETs and finFETs.
In a similar field of endeavor, Or-Bach discloses wherein the first layer FET and the second layer FET are selected from planar FETs and finFETs (See ¶0200 and ¶0203; ¶0446: FIG. 58A-K … Finfet).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the process of manufacturing bonded semiconductors as disclosed by Lilak to include the capability of creating planar FET’s and finFETs, as disclosed by Or-Bach, in order to fabricate devices offering a large variety of end products (Or-Bach, ¶0562).
Re: Claim 27, the combination of Lilak and HuangFu discloses the semiconductor device of claim 24.
However, the combination does not disclose wherein the first layer FET and the second layer FET are selected from planar FETs and finFETs.
In a similar field of endeavor, Or-Bach discloses wherein the first layer FET and the second layer FET are selected from planar FETs and finFETs (See ¶0200 and ¶0203; ¶0446: FIG. 58A-K … Finfet).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the process of manufacturing bonded semiconductors as disclosed by Lilak to include the capability of creating planar FET’s and finFETs, as disclosed by Or-Bach, in order to fabricate devices offering a large variety of end products (Or-Bach, ¶0562).
Claims 9 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Lilak et al. (US 20200395386 A1) in view of HuangFu (US 20160329239 A1), and further in view of Tang et al. (US 20170194351 A1), hereinafter “Tang.”
Re: Claim 9, the combination of Lilak and HuangFu discloses the semiconductor device of claim 1.
However, the combination does not specifically disclose wherein the insulating material layer has a thickness of about 15 nm to about 35 nm.
In a similar field of endeavor, Tang discloses wherein the insulating material layer has a thickness of about 15 nm to about 35 nm (Fig. 2 shows layer 206; ¶0032: the thickness of the amorphous silicon material 206 may be from about 10 nm to about 50 nm.).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the process of manufacturing bonded semiconductors as disclosed by Lilak to include an insulating material layer with a sufficient thickness as disclosed by Tang, in order to guarantee adherence between the bonded layers (Tang, ¶0032).
Re: Claim 28, the combination of Lilak and HuangFu discloses the semiconductor device of claim 20.
However, the combination does not specifically disclose wherein the insulating material layer has a thickness of about 15 nm to about 35 nm.
In a similar field of endeavor, Tang discloses wherein the insulating material layer has a thickness of about 15 nm to about 35 nm (Fig. 2 shows layer 206; ¶0032: the thickness of the amorphous silicon material 206 may be from about 10 nm to about 50 nm.).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the process of manufacturing bonded semiconductors as disclosed by Lilak to include an insulating material layer with a sufficient thickness as disclosed by Tang, in order to guarantee adherence between the bonded layers (Tang, ¶0032).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM ADROVEL whose telephone number is (571)272-3048. The examiner can normally be reached 7:30 AM - 5:00 PM.
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/WILLIAM ADROVEL/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898