DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Previous action: 1, 3 through 12, 21 through 27 allowed, claims 2 and 13 through 20 cancelled, claims 28 and 29 objected
Present action: 1, 3, 4, 11, 12, 21, 22, and 23 rejected, 5 through 10 and 24 through 29 objected, claims 2 and 13 through 20 cancelled
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 1, 3, 4, and 12 is/are rejected under 35 U.S.C. 103 as being obvious over Liu (US 2022/0367510) in view of Okina (US 2020/0258817)
The applied references have a common Yangtze Memory Technologies Co., LTD. with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Regarding claim 1.
Liu teaches:
A method for forming a three-dimensional (3D) memory device (fig 21), comprising: forming a first semiconductor structure, comprising: forming a first substrate (fig 5:330; [para 0058]), including a sacrificial substrate (fig 5:545; [para 0058]), a first stop layer (fig 5:546; [para 0059]), an initial semiconductor layer (fig 5:547; [para 0059]), a second stop layer (fig 5:550; [para 0062]), and a barrier layer (fig 5:552; [para 0062]) stacked in a vertical direction (fig 5:z; [para 0065]), forming a dielectric stack structure (fig 6:654; [para 0065]) including a plurality of dielectric layer pairs (fig 6:656,658; [para 0066])stacked on the first substrate (fig 5:330; [para 0058]), each dielectric layer pair (fig 6:656,658; [para 0066]) including a sacrificial layer (fig 6:658; [para 0066]) and a dielectric layer (fig 6:656; [para 0066]) different from the sacrificial layer (fig 6:658; [para 0066]), forming a plurality of channel structures (fig 7:761; [para 0089]) penetrating the dielectric stack structure (fig 6:654; [para 0065]), each channel structure (fig 7:761; [para 0089]) including a functional layer (fig 7:337; [para 0088]) and a semiconductor channel (fig 7:338; [para 0049]), and forming a gate line slit structure (fig 12:gls; [para 0111]) including a filling structure (fig 12:1278; [para 0111]) penetrating the dielectric stack structure (fig 6:654; [para 0065]) and extending into the first substrate (fig 5:330; [para 0058]);
removing a portion of the first substrate (fig 12,13:330; [para 0117]) and a portion of the gate line slit structure (fig 13,14:gls; [para 0123]) extended into the first substrate (fig 12,13:330; [para 0117]);
and forming a supplemental semiconductor layer (fig 15:1580; [para 0134]) on a remaining portion of the first substrate (fig 5:552; [para 0062]).
Liu does not teach a second substrate.
Okina teaches:
forming a second semiconductor structure (fig 15:700; [para 0111]) including a periphery circuit (fig 15:710; [para 0111]) on a second substrate (fig 15:709; [para 0111]); bonding the second semiconductor structure (fig 16:700; [para 0115]) to the first semiconductor structure (fig 16:1000; [para 0115]);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a second substrate in order to provide peripheral circuitry for device control.
Regarding claim 3.
Liu in view of Okina teaches the method of claim 1,
Liu teaches:
wherein forming the first semiconductor structure further comprises: forming a slit (fig 7,8:864; [para 0094]) penetrating the dielectric stack structure (fig 6:654; [para 0065]) and extending into the first substrate (fig 5:330; [para 0058]);
removing the sacrificial layers (fig 6:658; [para 0066]) in the dielectric stack structure (fig 6:654; [para 0065]) through the slit (fig 7,8:864; [para 0094]) to form a plurality of horizontal trenches (fig 2,8; [para 0095]);
forming a high-k dielectric layer (fig 8:872; [para 0099]) to cover exposed surfaces of the plurality of horizontal trenches (fig 8:864; [para 0094]) and on sidewalls and on a bottom of the slit (fig 7,8:864; [para 0094]);
and forming a gate structure (fig 8:870; [para 0096]) in each horizontal trench.
Regarding claim 4.
Liu in view of Okina teaches the method of claim 3,
Liu teaches:
forming the gate line slit structure comprises: forming at least one gate line spacer layer (fig 9:974; [para 0104]) on the high-k dielectric layer (fig 8:872; [para 0099]);
and forming the filling structure (fig 12:1278; [para 0111]) to fill the slit.
Regarding claim 12.
Liu in view of Okina teaches the method of claim 1,
Okina teaches:
bonding the second semiconductor structure (fig 15:700; [para 0111]) to the first semiconductor structure (fig 14:1000; [para 0110]) comprises:
hybrid bonding the second semiconductor structure (fig 15:700; [para 0111]) to the first semiconductor structure (fig 14:1000; [para 0110]) in a face-to-face manner (fig 16; [para 0115]).
Claim 11 is/are rejected under 35 U.S.C. 103 as being obvious over Liu (US 2022/0367510) in view of Okina (US 2020/0258817) as applied to claim 11 and further in view of Wu (US 2022/0310162) in view of Chen (US 2020/0027509)
The applied references have a common Yangtze Memory Technologies Co., LTD. with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
Regarding claim 11.
Liu in view of Okina teaches the method of claim 1, above.
Liu in view of Okina does not teach a wiring layer
Wu teaches:
further comprising forming a pad layer (fig 14:1282; [para 0145]) on the supplemental semiconductor layer (fig 14:1281; [para 0145]), comprising: forming a pad dielectric layer (fig 14:1384; [para 0151]) on the supplemental semiconductor layer (fig 14:1281; [para 0145]); forming a plurality of pad structures (fig 15:1595,1596; [para 0158]) embedded in the pad dielectric layer (fig 14:1384; [para 0151]); forming a wiring layer (fig 15:1594; [para 0158]) on the pad dielectric layer (fig 14:1384; [para 0151]) to connect with the plurality of pad structures (fig 15:1595,1596; [para 0158]);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a wiring layer in order to enable redistribution of voltage to the underlying memory structures.
Liu in view of Okina does not teach a protection layer
Chen teaches:
forming a protection layer (fig 4f; [para 0071]) to cover the wiring layer (fig 4f:424; [para 0070]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a protection layer overlying the wiring layer in order to provide additional layer of redistribution and to provide contact pads to enable connection between the memory structures and external structures.
Claims 21, 22, and 23 is/are rejected under 35 U.S.C. 103 as being obvious over Liu (US 2022/0367510) in view of Okina (US 2020/0258817)
The applied references have a common Yangtze Memory Technologies Co., LTD. with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
Regarding claim 21.
Liu teaches:
A method for forming a three-dimensional (3D) memory device (fig 21), comprising: forming a first semiconductor structure, comprising: forming a first substrate (fig 5:330; [para 0058]) including a sacrificial substrate (fig 5:545; [para 0058]), a first stop layer (fig 5:546; [para 0059]), an initial semiconductor layer (fig 5:547; [para 0059]), a second stop layer (fig 5:550; [para 0062]), and a barrier layer (fig 5:552; [para 0062]) stacked in a vertical direction (fig 5:z; [para 0065]), forming a dielectric stack structure (fig 6:654; [para 0065]) including a plurality of dielectric layer pairs (fig 6:656,658; [para 0066]) stacked on the first substrate (fig 5:330; [para 0058]), each dielectric layer pair (fig 6:656,658; [para 0066]) including a sacrificial layer (fig 6:658; [para 0066]) and a dielectric layer (fig 6:656; [para 0066]) different from the sacrificial layer (fig 6:658; [para 0066]), forming a plurality of channel structures (fig 7:761; [para 0089]) penetrating the dielectric stack structure (fig 6:654; [para 0065]), each channel structure (fig 7:761; [para 0089]) including a functional layer (fig 7:337; [para 0088]) and a semiconductor channel (fig 7:338; [para 0049]), and forming a gate line slit structure (fig 12:gls; [para 0111]) including a filling structure (fig 12:1278; [para 0111])penetrating the dielectric stack structure (fig 6:654; [para 0065]) and extending into the first substrate (fig 5:330; [para 0058]);
Liu does not teach a second substrate.
Okina teaches:
forming a second semiconductor structure (fig 15:700; [para 0111]) including a periphery circuit (fig 15:750; [para 0112]) on a second substrate (fig 15:709; [para 0112]); and bonding the second semiconductor structure (fig 16:700; [para 0115]) to the first semiconductor structure (fig 16:1000; [para 0111]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a second substrate in order to provide peripheral circuitry for device control.
Regarding claim 22.
Liu in view of Okina teaches the method of claim 21,
Liu teaches:
forming the first semiconductor structure further comprises: forming a slit (fig 7,8:864; [para 0094])penetrating the dielectric stack structure (fig 6:654; [para 0065]) and extending into the first substrate (fig 5:330; [para 0058]);
removing the sacrificial layers (fig 6:658; [para 0066]) in the dielectric stack structure (fig 6:654; [para 0065]) through the slit (fig 7,8:864; [para 0094]) to form a plurality of horizontal trenches (fig 2,8; [para 0095]);
forming a high-k dielectric layer (fig 8:872; [para 0099]) to cover exposed surfaces of the plurality of horizontal trenches and on sidewalls and on a bottom of the slit (fig 7,8:864; [para 0094]);
and forming a gate structure (fig 8:870; [para 0096]) in each horizontal trench.
Regarding claim 23.
Liu in view of Okina teaches the method of claim 22,
Liu teaches:
forming the gate line slit structure comprises: forming at least one gate line spacer layer (fig 9:974; [para 0104]) on the high-k dielectric layer (fig 8:872; [para 0099]);
and forming the filling structure (fig 12:1278; [para 0111]) to fill the slit.
Allowable Subject Matter
Claims 5 through 10 and 24 through 29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 5, the prior art does not teach in combination with other elements of the claim, a method for forming a three-dimensional (3D) memory device: forming a first substrate including a sacrificial substrate, a first stop layer, an initial semiconductor layer, a second stop layer, and a barrier layer stacked in a vertical direction; removing a portion of the first substrate and a portion of the gate line slit structure extended into the first substrate; and forming a supplemental semiconductor layer on a remaining portion of the first substrate, forming a slit penetrating the dielectric stack structure and extending into the first substrate; forming at least one gate line spacer layer on a high-k dielectric layer; and forming the filling structure to fill the slit, before forming a high-k dielectric layer, performing an oxidization process to oxidize a portion of the barrier layer exposed by the slit.
Regarding claim 6, the prior art does not teach, in combination with other elements of the claim a method for forming a three-dimensional (3D) memory device, comprising: forming a first substrate including a sacrificial substrate, a first stop layer, an initial semiconductor layer, a second stop layer, and a barrier layer stacked in a vertical direction, forming a supplemental semiconductor layer on a remaining portion of the first substrate, forming a slit penetrating the dielectric stack structure and extending into the first substrate; removing the sacrificial layers in the dielectric stack structure through the slit to form a plurality of horizontal trenches; and forming a gate structure in each horizontal trench.forming at least one gate line spacer layer on the high-k dielectric layer; and forming the filling structure to fill the slit.removing the sacrificial substrate and stopping at the first stop layer; removing the first stop layer and the initial semiconductor layer and stopping at the second stop layer to expose portions of the channel structures and portions of the high-k dielectric layer of the gate line slit structure; removing a portion of the functional layer of each channel structure to expose the semiconductor channel; and doping a portion of the semiconductor channel of each channel structure.
Regarding claim 24, the prior art does not teach in combination with other elements of the claim, a method for forming a three-dimensional (3D) memory device, comprising: forming a first semiconductor structure, comprising: forming a first substrate including a sacrificial substrate, a first stop layer, an initial semiconductor layer, a second stop layer, and a barrier layer stacked in a vertical direction; forming a high-k dielectric layer to cover exposed surfaces of the plurality of horizontal trenches and on sidewalls and on a bottom of the slit; and forming a gate structure in each horizontal trench,forming at least one gate line spacer layer on the high-k dielectric layer; and forming the filling structure to fill the slit,
before forming the high-k dielectric layer, performing an oxidization process to oxidize a portion of the barrier layer exposed by the slit; after bonding the second semiconductor structure and the first semiconductor structure, removing a portion of the first substrate and a portion of the gate line slit structure extended into the first substrate; and forming a supplemental semiconductor layer on a remaining portion of the first substrate.
Conclusion
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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