DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nishida (U.S 10,283,493 B1).
As to claim 1, Nishida discloses in Figs. 17 & 24 a three-dimensional (3D) memory device (Figs. 17, 24), comprising:
a first semiconductor structure (Fig. 24: 1000; also shown in Fig. 17) including a core region (Fig. 24: area including 100, 200; also shown in Fig. 17) (Fig. 17& 24, col. 12, lines 12-20, and 45-49), a spacer region (Fig. 17: area including 768) (Fig. 17, col. 8, lines 35-50), and a periphery region (Figs. 17, 24: area including 700), comprising:
a memory stack (Figs. 17, 24: 100) on a semiconductor layer (Figs. 17, 24: 10) in the core region (area including 100, 200) (Figs. 17, 24, col. 8, line 45 – col. 9, line 55; col. 12, lines 45-49), a first periphery circuit (Fig. 24: 710) on the semiconductor layer (10) in the periphery region (Figs. 17, 24, col. 9, line 55 - col. 10, line 2), and a spacer structure (Fig.17: 768) in the spacer region to separate the memory stack (Figs. 17, 24: 100) and the first periphery circuit (Fig. 24: 710) (see Figs. 17, 24 , col. 8, lines 35-50);
and a second semiconductor structure (Fig. 24: 2000) including a second periphery circuit (Fig. 24: 2710) on a substrate (Fig. 24: 2009) (Fig. 24, col. 31, lines 51-59, col. 32, lines 45-55);
wherein the second semiconductor structure (Fig. 24: 2000) is connected to the first semiconductor structure (Fig. 24: 1000) (see Fig 24, col. 32, lines 26-45).
As to claim 2, as applied to claim 1 above, Nishida discloses in Figs. 17 & 24 all claimed limitations including the limitation: wherein the spacer structure (Fig.17: 768) comprises a dielectric stack structure (including layers 768, 165, 265, 270, 280, 282, 284 & 132, Fig. 17) in the spacer region, the dielectric stack structure (including layers 768, 165, 265, 270, 280, 282, 284 & 132, Fig. 17) including a plurality of dielectric layer pairs each including a stack sacrificial layer (132/142) and a stack dielectric layer (including layers 768, 165, 265, 270, 280, 282, 284, Fig. 17) different from the stack sacrificial layer (132/142) (Fig. 17, col. 10, lines 41-50, col. 11, 50-60).
As to claim 3, as applied to claims 1 and 2 above, Nishida discloses in Figs. 17 & 24 all claimed limitations including the limitation: wherein the spacer structure (Fig.17: 768) comprises a turning structure (56) comprises a first portion of the plurality of dielectric layer pairs (56) extending in a horizontal plane and a second portion of the plurality of dielectric layer pairs (170, 170) extending in a non-horizontal plane (Figs. 8, 9C-9D).
As to claim 4, as applied to claim 1 above, Nishida discloses in Figs. 17 & 24 all claimed limitations including the limitation: wherein the first semiconductor structure (Fig. 24: 1000; also shown in Fig. 17) further comprises: a plurality of channel structures (60) penetrating the memory stack (Figs. 17, 24: 100) in the core region (area including 100, 200), each channel structure (60) including a functional layer (54) and a semiconductor channel (“memory stack structure” 55 include “a semiconductor channel”) (Figs. 11, 17 & 20, col. 21, lines 38-51).
As to claim 5, as applied to claim 1 and 4 above, Nishida discloses in Figs. 17 & 24 all claimed limitations including the limitation: wherein the first semiconductor structure (Fig. 24: 1000; also shown in Fig. 17) further comprises: a staircase structure in the memory stack (Figs. 17, 24: 100); and a plurality of dummy channel structures (20) penetrating the staircase structure in the core region (area including 100, 200) (Figs. 17, 24).
As to claim 6, as applied to claim 1, 4 and 5 above, Nishida discloses in Figs. 17 & 24 all claimed limitations including the limitation: wherein the first semiconductor structure (Fig. 24: 1000; also shown in Fig. 17) further comprises: at least one slit structure (79, Fig. 12A) penetrating the memory stack (Figs. 17, 24: 100) and extending in a parallel direction to separate the plurality of channel structures (60) (Figs. 12A, 17, 24).
As to claim 7, as applied to claim 1, 4, 5 and 6 above, Nishida discloses in Figs. 17 & 24 all claimed limitations including the limitation: wherein the memory stack comprises: a plurality of interleaved stack dielectric layers (132, 232) and gate structures (146, 246) stacked in a vertical direction (Fig. 17).
As to claim 8, as applied to claim 1, 4, 5, 6 and 7 above, Nishida discloses in Figs. 17 & 24 all claimed limitations including the limitation: wherein the first semiconductor structure (Fig. 24: 1000; also shown in Fig. 17) further comprises: a plurality of word line contacts (146, 246), a plurality of channel structure contacts (88) in the core region (area including 100, 200); a plurality of periphery contacts (782) in the periphery region (Fig. 24: 710); and a plurality of first interconnect contacts (20) connected with corresponding word line contacts (146, 246), channel structure contacts (88), and periphery contacts (782), respectively.
As to claim 9, as applied to claim 1 above, Nishida discloses in Figs. 17 & 24 all claimed limitations including the limitation: wherein the first periphery circuit (Fig. 24: 710) comprises: a high voltage circuit including a plurality of high voltage transistors on the semiconductor layer (Figs. 17, 24: 10) in the periphery region (Figs. 17, 24, col. 36, lines 32-50).
As to claim 10, as applied to claims 1 and 9 above, Nishida discloses in Figs. 17 & 24 all claimed limitations including the limitation: wherein the first periphery circuit (Fig. 24: 710) further comprises: a low voltage circuit including a plurality of low voltage transistors on the semiconductor layer (Figs. 17, 24: 10) in the periphery region (Figs. 17, 24, col. 36, lines 32-50).
As to claim 11, as applied to claims 1 and 9 above, Nishida discloses in Figs. 17 & 24 all claimed limitations including the limitation: wherein the second periphery circuit (see a second periphery circuit 710 on the right side, Fig. 24) comprises: a low low voltage circuit including a plurality of low low voltage transistors on the substrate (10); and a plurality of second interconnect contacts (comprising 782, 784, 786, 786) connected with corresponding low low voltage transistors, respectively (Figs. 17, 24, col. 36, lines 32-50).
As to claim 12, as applied to claims 1, 9 and 11 above, Nishida discloses in Figs. 17 & 24 all claimed limitations including the limitation: wherein the second periphery circuit (see a second periphery circuit 710 on the right side, Fig. 24) further comprises: a low voltage circuit including a plurality of low voltage transistors on the substrate (10) (Figs. 17, 24, col. 36, lines 32-50).
As to claim 13, as applied to claim 1 above, Nishida discloses in Figs. 17 & 24 all claimed limitations including the limitation: wherein: the second semiconductor structure (Fig. 24: 2000) and the first semiconductor structure (Fig. 24: 1000; also shown in Fig. 17) are bonded together in a face-to-face manner, such that the second interconnect contacts (comprising 782, 784, 786, 786) and corresponding second interconnect contacts (comprising 782, 784, 786, 786) are connected respectively at a bonding interface (Figs. 17, 24).
As to claim 14, as applied to claims 1, 4, and 5 above, Nishida discloses in Figs. 17 & 24 all claimed limitations including the limitation: wherein: the functional layer (54) of each channel structure comprises a blocking layer (52), a storage layer (54), and a tunneling layer (56); and the semiconductor channel (“memory stack structure” 55 include “a semiconductor channel”) comprises a doped region contacting the semiconductor layer (Figs. 17, 24: 10) (Fig. 12A, col. 19, lines 27-55).
As to claim 15, as applied to claims 1, 4, and 5 above, Nishida discloses in Figs. 17 & 24 all claimed limitations including the device further comprising a pad layer (comprising 764, 782/784/786) on the semiconductor layer (10), the pad layer (comprising 764, 782/784/786) comprising: a pad dielectric layer (764) on the semiconductor layer (10); a plurality of pad structures (782, 784, 786) embedded in the pad dielectric layer (764) (Fig. 17); a wiring layer (788) on the pad dielectric layer (764) to connect with the plurality of pad structures (782, 784, 786); and a passivation layer (766) to cover the wiring layer (788) (Fig. 17).
As to claim 16, as applied to claim 1 above, Nishida discloses in Figs. 17 & 24 all claimed limitations including the limitation: wherein the semiconductor layer comprises: an initial semiconductor layer (9) in the periphery region; and a supplemental semiconductor layer (6) in the core region (area including 100, 200) and the spacer region; wherein the initial semiconductor layer (9) is isolated from the supplemental semiconductor layer (6) by a spacer layer (Fig. 17).
As to claim 17, Nishida discloses in Figs. 17 & 24 a memory system, comprising: a memory device (Figs. 17, 24) configured to store data, and comprising: a first semiconductor structure (Fig. 24: 1000; also shown in Fig. 17) including a core region (area including 100, 200) (Fig. 17& 24, col. 12, lines 12-20, and 45-49), a spacer region (Fig. 17: area including 768) (Fig. 17, col. 8, lines 35-50), and a periphery region (Figs. 17, 24: area including 700), comprising: a memory stack (Figs. 17, 24: 100) including an array of memory cells on a semiconductor layer (Figs. 17, 24: 10) in the core region (area including 100, 200) (Figs. 17, 24, col. 8, line 45 – col. 9, line 55; col. 12, lines 45-49), a first periphery circuit (Fig. 24: 710) on the semiconductor layer (Figs. 17, 24: 10) in the periphery region (Figs. 17, 24, col. 9, line 55 - col. 10, line 2), and a spacer structure (Fig.17: 768) in the spacer region to separate the memory stack (Figs. 17, 24: 100) and the first periphery circuit (Fig. 24: 710) (see Figs. 17, 24 , col. 8, lines 35-50), and a second semiconductor structure (Fig. 24: 2000) including a second periphery circuit (Fig. 24: 2710) on a substrate (Fig. 24: 2009) (Fig. 24, col. 31, lines 51-59, col. 32, lines 45-55), wherein the second semiconductor structure (Fig. 24: 2000) is bonded with the first semiconductor structure (Fig. 24: 1000) at a bonding interface (see Fig 24, col. 32, lines 26-45); and a memory controller (700) coupled to the memory device (Figs. 17, 24) and configured to control the array of memory cells through the first peripheral circuit (Fig. 24: 710) and the second periphery circuit (Fig. 24: 2710) (Figs. 17, 24, col. 25, lines 25-45).
As to claim 18, as applied to claim 17 above, Nishida discloses in Figs. 17 & 24 all claimed limitations including the limitation: wherein the spacer structure (Fig.17: 768) comprises a dielectric stack structure (including layers 768, 165, 265, 270, 280, 282, 284 & 132, Fig. 17) in the spacer region, the dielectric stack structure (including layers 768, 165, 265, 270, 280, 282, 284 & 132, Fig. 17) including a plurality of dielectric layer pairs each including a stack sacrificial layer (132/142) and a stack dielectric layer (including layers 768, 165, 265, 270, 280, 282, 284, Fig. 17) different from the stack sacrificial layer (132/142) (Fig. 17, col. 10, lines 41-50, col. 11, 50-60).
As to claim 19, as applied to claims 17 and 18 above, Nishida discloses in Figs. 17 & 24 all claimed limitations including the limitation: wherein the spacer structure (Fig.17: 768) comprises a turning structure (56) comprises a first portion of the plurality of dielectric layer pairs (56) extending in a horizontal plane and a second portion of the plurality of dielectric layer pairs (170, 170) extending in a non-horizontal plane (Figs. 8, 9C-9D).
As to claim 20, as applied to claim 17 above, Nishida discloses in Figs. 17 & 24 all claimed limitations including the limitation: wherein the first periphery circuit (Fig. 24: 710) comprises: a high voltage circuit including a plurality of high voltage transistors on the semiconductor layer (Figs. 17, 24: 10) in the periphery region (Figs. 17, 24, col. 36, lines 32-50); the second periphery circuit (see a second periphery circuit 710 on the right side, Fig. 24) comprises: a low low voltage circuit including a plurality of low low voltage transistors on the substrate (10); and the first periphery circuit (Fig. 24: 710) or the second periphery circuit (see a second periphery circuit 710 on the right side, Fig. 24) further comprises a low voltage circuit including a plurality of low voltage transistors (Figs. 17, 24, col. 36, lines 32-50).
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Son et al. (U.S 2023/0328956 A1) and Choi et al. (U.S 2022/0068859 A1).
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached M-F, 10am-10pm (flex) (PST).
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/Thanh Y. Tran/Primary Examiner, Art Unit 2817
February 5, 2026