DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/14/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claims 1-14, 17-19 and 21-23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-14, 17-19 and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Wu (CN111463263) in view of Chen et al. (20220336593)
Regarding Claim 1, in Figs 11, 13 and 20, Wu discloses a laterally-diffused metal-oxide semiconductor (LDMOS) device, comprising: a semiconductor substrate 302 of a first conductivity type (p); a doped drift region 3030of a second conductivity type (n) formed on at least a portion of the substrate, the second conductivity type being opposite in polarity to the first conductivity type; a body region 309 of the first conductivity type (p) formed in the doped drift region proximate an upper surface of the doped drift region; source 313 and drain regions 314 of the second conductivity type (n) formed proximate an upper surface of the body region and doped drift region, respectively, and spaced apart laterally from one another; a gate structure comprising a control gate 307 and a field plate 308, the control gate being formed over at least a portion of the body region 309, the field plate being 308 formed over at least a portion of the doped drift region 303, the gate structure being disposed between the source and drain regions and electrically isolated from the body and doped drift regions by a first insulating layer 305 formed between the gate structure and the body and doped drift regions; and an oxide structure 304/306 formed on a portion of the field plate and a portion of the doped drift region, the oxide structure overlapping a corner of the field plate. With respect to the newly added limitation of “the oxide structure extending on an upper surface of the field plate and overlapping a corner of the field plate”, Wu discloses this as element 2001 (SAB silicide/silicide block/barrier) in Figs. 20. Wu fails to disclose the newly added limitation of wherein the oxide structure is vertically non-overlapping with the drain region. However, Chen et al. disclose a high power semiconductor device where in Figs. 1 and 2, elements 124/122 and 106, the required non-overlapping configuration is disclosed.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the non-overlapping configuration on Wu as taught by Chen et al. in order to prevent the possibility of overlap parasitic capacitance.
Regarding Claim 2, in Wu, a silicide layer 315a formed on an upper surface of the control gate, a portion of an upper surface of the field plate uncovered by the oxide structure, and an upper surface of the source and drain regions. Regarding newly added limitation “wherein the oxide structure extends on a sidewall of the field plate”, this is disclosed as element 2001 in Fig 20.
Regarding Claim 3, in Wu, the control gate 307 is fully silicided.
Regarding Claim 4, in Wu, an isolation structure 311b/311c formed on the doped drift region between the control gate 307 and the field plate 308.
Regarding Claim 5, in Wu, the isolation structure 311b/311c is formed on at least one sidewall of each of the control gate 307 and the field plate 308.
Regarding Claim 6, in Wu, a plurality of insulating spacers 311b/311c formed on at least sidewalls of the control gate and field plate.
Regarding Claim 7, in Wu, the control gate 307 and field plate 308 are formed substantially planar relative to one another.
Regarding Claim 8, in Wu, a thick oxide structure 304/306 formed on the upper surface of the doped drift region, at least a portion of the field plate being formed on an upper surface of the thick oxide structure, a least a portion of the oxide structure being formed on the thick oxide structure, the thick oxide structure extending laterally across the doped drift region to the drain region.
Regarding Claim 9, in Wu, a local oxidation of silicon (LOCOS) structure 304/306 formed in the doped drift region proximate the upper surface of the doped drift region, at least a portion of the field plate being formed on an upper surface of the LOCOS structure, a least a portion of the oxide structure being formed on the LOCOS structure, the LOCOS structure extending laterally in the doped drift region to the drain region.
Regarding Claim 10, in Wu, a shallow trench isolation (STI) structure 1101 (see Fig. 11) formed in the doped drift region proximate the upper surface of the doped drift region, at least a portion of the field plate being formed on an upper surface of the STI structure such that the field plate is substantially planar with the control gate, a least a portion of the oxide structure being formed on the STI structure, the STI structure extending laterally in the doped drift region to the drain region.
Regarding Claim 11, in Figs. 11 and 13, Wu discloses a method of fabricating a laterally-diffused metal-oxide semiconductor (LDMOS) device, the method comprising: forming a doped drift region 303 of a first conductivity type (n) on at least a portion of a semiconductor substrate of a second conductivity type (p), the second conductivity type being opposite in polarity to the first conductivity type; forming a body region 309 of the second conductivity type (p) in the doped drift region proximate an upper surface of the doped drift region; forming source 313 and drain regions 314 of the first conductivity type (p) proximate an upper surface of the body region and doped drift region, respectively, and spaced apart laterally from one another; forming a gate structure 307 comprising a control gate and a field plate 308, the control gate being formed over at least a portion of the body region, the field plate being formed over at least a portion of the doped drift region, the gate structure being disposed between the source and drain regions and electrically isolated from the body and doped drift regions by a first insulating layer 305 formed between the gate structure and the body and doped drift regions; and forming an oxide structure 304/306 on a portion of the field plate and a portion of the doped drift region, the oxide structure overlapping a corner of the field plate. Wu fails to disclose the newly added limitation of wherein the oxide structure is vertically non-overlapping with the drain region. However, Chen et al. disclose a high power semiconductor device where in Figs. 1 and 2, elements 124/122 and 106, the required non-overlapping configuration is disclosed.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the non-overlapping configuration on Wu as taught by Chen et al. in order to prevent the possibility of overlap parasitic capacitance.
Regarding Claim 12, in Wu, forming a silicide layer 315a on an upper surface of the control gate, a portion of an upper surface of the field plate uncovered by the oxide structure, and an upper surface of the source and drain regions.
Regarding Claim 13, in Wu, method comprising fully siliciding (315a) the control gate 307.
Regarding Claim 14, in Wu, forming an isolation structure 311b/311c on the doped drift region between the control gate and the field plate.
Regarding Claim 17, in Wu, forming a thick oxide structure 304/306 on the upper surface of the doped drift region, at least a portion of the field plate being formed on an upper surface of the thick oxide structure, a least a portion of the oxide structure being formed on the thick oxide structure, the thick oxide structure extending laterally across the doped drift region to the drain region.
Regarding Claim 18, in Wu, comprising forming a local oxidation of silicon (LOCOS) structure 304/306 in the doped drift region proximate the upper surface of the doped drift region, at least a portion of the field plate being formed on an upper surface of the LOCOS structure, a least a portion of the oxide structure being formed on the LOCOS structure, the LOCOS structure extending laterally in the doped drift region to the drain region.
Regarding Claim 19, in Wu, forming a shallow trench isolation (STI) structure 1101 (see Fig. 11) in the doped drift region proximate the upper surface of the doped drift region, at least a portion of the field plate being formed on an upper surface of the STI structure such that the field plate is substantially planar with the control gate, a least a portion of the oxide structure being formed on the STI structure, the STI structure extending laterally in the doped drift region to the drain region.
Regarding Claim 21, in Wu, in Fig. 20, a portion (rightmost edge) of the oxide structure 2001 is directly on the doped drift region 303.
Also, non-applied pertinent art Kim 20140231911 discloses this limitation in Figs. 5L and 5M as element 561
Regarding Claim 22, in Wu, in Fig. 20, an upper surface of the drain region is free of the oxide structure thereon.
Regarding Claim 23, in Wu, in Fig. 20, a silicide layer 315a/315b formed on a second portion of the upper surface of the field plate that is uncovered by the oxide structure 2001.
Conclusion
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/FAZLI ERDEM/Primary Examiner, Art Unit 2812 1/16/2026