DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 11 and 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhuang et al. (US 2020/0402968).
Regarding claim 11, Zhuang et al. discloses, as shown in Figures 4, a semiconductor structure comprising:
a first circuit row (ROW3), the first circuit row comprising a first circuit cell (CELLd) having a first cell height greater than a first row height (RH2) of the first circuit row; and
a second circuit row (ROW2) adjacent the first circuit row, the second circuit row comprising a second circuit cell (CELLc) having a second cell height greater than a second row height (RH1) of the second circuit row;
wherein a first portion of the first circuit cell (CELLd) extends into the second circuit row (ROW2), a second portion of the second circuit cell (CELLc) extends into the first circuit row (ROW3), and the first portion of the first circuit cell is offset from the second portion of the second circuit cell.
Regarding claim 14, Zhuang et al. discloses the first circuit row further comprises a third circuit cell (CELLb) having a third cell height (RH2) equal to the first row height (RH2) of the first circuit row (ROW3).
Claim(s) 16 and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kazue (JP2000-22084A).
Regarding claim 16, Kazue discloses, as shown in Figure 7, a semiconductor structure comprising:
a first circuit row (between upper 41/42), the first circuit row having a first set of two or more circuit cells having different cell heights, wherein horizontal centers of the first set of two or more circuit cells (43-49) are aligned with a first horizontal center line (imaginary middle line between upper 41 and 42) of the first circuit row; and
a second circuit row (between lower 41/42) adjacent the first circuit row, the second circuit row having a second set of two or more circuit cells (50-59) having different cell heights, wherein horizontal centers of the second set of two or more circuit cells are aligned with a second horizontal center line (imaginary middle line between lower 41 and 42) of the second circuit row.
Regarding claim 18, Kazue discloses the first set of two or more circuit cells comprises a first circuit cell (43) having a first cell height greater than a first row height (height from the upper 42 to 41) of the first circuit row, wherein the second set of two or more circuit cells comprises a second circuit cell (53,54,55,56,57,58, or 59) having a second cell height greater than a second row height (height from the lower 42 to lower 41) of the second circuit row, and wherein the first circuit cell in the first circuit row is horizontally offset from the second circuit cell in the second circuit row.
Allowable Subject Matter
Claims 1-10 are allowed.
Claims 12-13, 15, 17 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Applicant' s claims 1-10, 12-13, 15, 17 and 19-20 are allowable over the references of record because none of these references disclose or can be combined to yield the claimed semiconductor structure comprising the first circuit cell having a first cell height greater than a first row height of the first circuit row, the second circuit cell having a second cell height different than the first cell height, the third circuit cell having a third cell height less than a second row height of the second circuit row, and the first circuit cell in the first circuit row is at least partially aligned with the third circuit cell in the second circuit row, in combination with the remaining claimed limitations of claim 1; none of these references disclose or can be combined to yield the claimed semiconductor structure comprising a horizontal center of the first circuit cell is aligned with a first horizontal center line of the first circuit row and a horizontal center of the second circuit cell is aligned with a second horizontal center line of the second circuit row, as recited in claim 12; none of these references disclose or can be combined to yield the claimed semiconductor structure comprising the first circuit row further comprises a third circuit cell having a third cell height less than the first row height of the first circuit row, as recited in claim 13; none of these references disclose or can be combined to yield the claimed semiconductor structure comprising the first row height of the first circuit row is equal to the second row height of the second circuit row, as recited in claim 15; none of these references disclose or can be combined to yield the claimed semiconductor structure comprising the first set of two or more circuit cells comprises a first circuit cell having a first cell height greater than a first row height of the first circuit row, wherein the second set of two or more circuit cells comprises a second circuit cell having a second cell height less than a second row height of the second circuit row, and wherein the first circuit cell in the first circuit row is at least partially horizontally aligned with the second circuit cell in the second circuit row, as recited in claim 17; none of these references disclose or can be combined to yield the claimed semiconductor structure comprising the first set of two or more circuit cells comprises a first circuit cell having a first cell height greater than a first row height of the first circuit row and a second circuit cell having a second cell height less than the first row height of the first circuit row, as recited in claim 19; and none of these references disclose or can be combined to yield the claimed semiconductor structure comprising the first set of two or more circuit cells comprises a first circuit cell having a first cell height greater than a first row height of the first circuit row and a second circuit cell having a second cell height equal to the first row height of the first circuit row, as recited in claim 20.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUNG K VU whose telephone number is (571)272-1666. The examiner can normally be reached Monday - Friday: 7am - 5pm.
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/HUNG K VU/ Primary Examiner, Art Unit 2897