DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Response to Amendment
Applicant’s arguments filed 12/18/2025 have been entered and considered. The amendments to claims 21, 31, 33, and 38, the cancellation of claims 23 and 32, and the added claims 41 and 42 are acknowledged.
Response to Arguments
Applicant’s arguments with respect to claims 1, 31 and 38 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under pre-AIA 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims under pre-AIA 35 U.S.C. 103(a), the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were made absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and invention dates of each claim that was not commonly owned at the time a later invention was made in order for the examiner to consider the applicability of pre-AIA 35 U.S.C. 103(c) and potential pre-AIA 35 U.S.C. 102(e), (f) or (g) prior art under pre-AIA 35 U.S.C. 103(a).
Claims 21-22, 30, 38-39, and 41 are rejected under pre-AIA 35 U.S.C. 103 as being unpatentable over by Huemoeller US 6905914 B1 (hereinafter referred to as Huemoeller), in view of Yu et al. US 20130241057 A1 (hereinafter referred to as Yu).
Regarding claim 21, Huemoeller teaches
A semiconductor device (“assembly 1200” col line FIG. 13) comprising:
an interposer (though not called interposer by name, the structure comprising “vias 624, 824, 924, traces 832, and lands 1044 formed in dielectric strips 108, 708, 908, and 1008”, col 12 lines 43-44 FIG. 13, has the same features known in the art for an interposer) comprising:
a first interposer side (“Upper surface 108U of dielectric strip 108”, col 12 line 33, top side of “dielectric strip 108” of interposer);
a second interposer side (bottom side of “dielectric strip 1008”) opposite the first interposer side;
a first dielectric layer (“dielectric strip 108”) at the first interposer side;
a first conductive via (“via 624”) that extends through at least the first dielectric layer;
a second conductive via (“via 924”) at the second interposer side; and
a redistribution structure (“vias 824” and “traces 832”) in contact with the first dielectric layer and electrically connected to the first conductive via and the second conductive via (“vias 824” and “traces 832” at least partially contact surfaces of “dielectric strip 108” and electrically connect “visa 624” and “vias 924” as seen in FIG. 13);
a semiconductor die (“electronic component 106-1” col 12 line 21 FIG. 13) comprising:
a first die side that faces away from the first interposer side (top side of “electronic component 106-1”);
a second die side that faces toward the first interposer side (“front surfaces 106F of electronic components 106-1”, col 12 lines 34, bottom side of “electronic component 106-1”) and comprises a die connection terminal (“bond pad 112” col 12 line 50) that is coupled to the first conductive via; and
a lateral die side that extends between the first die side and the second die side (“electronic component 106-1” has a left and right lateral side);
an encapsulating material over at least the second die side (though not called encapsulant by name, “adhesive strip 120” performs the function of an encapsulating material since it encapsulates the “front surface 106F” and “Upper surface 108U” and surrounds portions “vias 624”), wherein:
at least one other side of the semiconductor die is exposed from the encapsulating material (lateral sides and top side of “electronic component 106-1” are exposed from “adhesive strip 120”);
the encapsulating material comprises an uppermost surface facing away from the interposer (“adhesive strip 120” has a surface in contact with “front surface 106F” facing away from “Upper surface 108U” of “dielectric strip 108”), a lowermost surface facing the interposer (“adhesive strip 120” has a surface in contact with “Upper surface 108U” facing away from “front surface 106F”), and a lateral surface that extends between the uppermost surface and the lowermost surface (“adhesive strip 120” has left and right lateral surfaces); and
the lateral surface of the encapsulating material is parallel to the lateral die side (left and right lateral surfaces of “adhesive strip 120” and “electronic component 106-1” appear substantially coplanar in FIG. 13 after singulation); and
a conductive bump (“interconnection balls 1150” col 12 lines 47-48) coupled to the second conductive via.
However, Huemoeller fails to teach the second conductive via that extends outward from the second interposer side such that a portion of the second conductive via is below the second interposer side, wherein the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump.
Nevertheless, Yu teaches
the second conductive via (“through via 29” para. 0044 FIG. 5) that extends outward from the second interposer side (bottom of “substrate 17”, para. 0039) such that a portion of the second conductive via is below the second interposer side (“protrusion 35” of “through via 29” extends beyond the bottom surface of “substrate 17”, para. 0044 FIG. 44),
wherein the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump (“solder 33 melts and reforms to surround the through via protrusions 35” para. 0040).
Huemoeller and Yu teach multichip packages. Yu teaches “through vias 29” that protrude and connect to “substrate 19” or “system board 19” through “solder 33” (para. 0040). The way “through vias 29” protrude allow for direct connection between “substrate 17” and “system board 19” without the need of additional interposers or redistribution layers (para. 0021 and 0028). This reduces the package thickness and the amount of manufacturing steps (para. 0003 and 0021). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the “via 924” in Huemoeller can be formed to protrude like “through vias 29” from the interposer surface so that “interconnection balls 150” can be directly attached to “via 924”. This saves manufacturing costs and time and reduces package size.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device in Huemoeller with the extending via as taught in Yu. When the via extends below the second surface of the interposer, bump connections can be directly made to the via. This eliminates the need for redistribution structures or other interposers, increasing manufacturing efficiency and reducing package size.
Regarding claim 22, Huemoeller, modified by Yu, teach the semiconductor device of claim 21, but fail to expressly teach comprising an under bump metal layer between the second conductive via and the conductive bump, and wherein at least a first portion of the under bump metal layer extends outward from the second interposer side.
Nevertheless, an alternate embodiment in Yu teaches a metallic “surface finish 49” that coats “protrusions 35” (para. 0044 FIG. 7). The “surface finish 49” prevents the copper of “protrusion 35” from being totally consumed by an intermetallic compound formed with the “solder 33” during the reflow process (para. 0044), serving as a barrier layer. This embodiment is used to form an assembly as the one in FIG. 5, so it is understood that “surface finish 49” is interposed between “protrusion 35” and “solder 33”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that “surface finish 49” prevents the copper is “through via 29” from diffusing and forming an intermetallic compound with “solder 33”, better retaining the original structure.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the semiconductor device taught between Huemoeller and Yu with the alternate embodiment in Yu. The under bump metal protects the material of the second via from forming intermetallic compounds.
Regarding claim 30, Huemoeller, modified by Yu, teaches the semiconductor device of claim 21, wherein: the interposer comprises a lateral interposer side that extends between the first interposer side and the second interposer side (the interposer in FIG. 13 has left and right lateral sides extending from “upper surface 108U” and the bottom side); and the lateral interposer side is parallel to the lateral die side and to the lateral surface of the encapsulating material (lateral sides of “electronic component 106-1”, “adhesive strip 120”, and the interposer are at least substantially coplanar).
Regarding claim 41, Huemoeller, modified by Yu, teaches the semiconductor device of claim 21 but fail to expressly teach comprising: an under bump metal layer comprising a portion that covers the portion of the second conductive via that is below the second interposer side; and wherein the portion of the under bump metal layer covering the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump.
Nevertheless, an alternate embodiment in Yu teaches a metallic “surface finish 49” that coats “protrusions 35” (para. 0044 FIG. 7). The “surface finish 49” prevents the copper of “protrusion 35” from being totally consumed by an intermetallic compound formed with the “solder 33” during the reflow process (para. 0044), serving as a barrier layer. This embodiment is used to form an assembly as the one in FIG. 5, so it is understood that “surface finish 49” is within “solder 33”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that “surface finish 49” prevents the copper is “through via 29” from diffusing and forming an intermetallic compound with “solder 33”, better retaining the original structure.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the semiconductor device taught between Huemoeller and Yu with the alternate embodiment in Yu. The under bump metal protects the material of the second via from forming intermetallic compounds.
Regarding claim 38, Huemoeller teaches a method of manufacturing a semiconductor device (method of forming “assembly 1200” col 12 line 10 FIG. 13), the method comprising:
providing an interposer (though not called interposer by name, the structure comprising “vias 624, 824, 924, traces 832, and lands 1044 formed in dielectric strips 108, 708, 908, and 1008”, col 12 lines 43-44 FIG. 13, has the same features known in the art for an interposer) comprising:
a first interposer side (“Upper surface 108U of dielectric strip 108”, col 12 line 33, top side of “dielectric strip 108” of interposer);
a second interposer side (bottom side of “dielectric strip 1008”) opposite the first interposer side;
a first dielectric layer (“dielectric strip 108”) at the first interposer side;
a first conductive via (“via 624”) that extends through at least the first dielectric layer;
a second conductive via (“via 924”) at the second interposer side; and
a redistribution structure (“vias 824” and “traces 832”) in contact with the first dielectric layer and electrically connected to the first conductive via and the second conductive via (“vias 824” and “traces 832” at least partially contact surfaces of “dielectric strip 108” and electrically connect “visa 624” and “vias 924” as seen in FIG. 13);
providing a semiconductor die (“electronic component 106-1” col 12 line 21 FIG. 13) comprising:
a first die side that faces away from the first interposer side (top side of “electronic component 106-1”);
a second die side that faces toward the first interposer side (“front surfaces 106F of electronic components 106-1”, col 12 lines 34, bottom side of “electronic component 106-1”) and comprises a die connection terminal (“bond pad 112” col 12 line 50) that is coupled to the first conductive via; and
a lateral die side that extends between the first die side and the second die side (“electronic component 106-1” has a left and right lateral side);
providing an encapsulating material over at least the second die side (though not called encapsulant by name, “adhesive strip 120” performs the function of an encapsulating material since it encapsulates the “front surface 106F” and “Upper surface 108U” and surrounds portions “vias 624”), wherein:
at least one other side of the semiconductor die is exposed from the encapsulating material (lateral sides and top side of “electronic component 106-1” are exposed from “adhesive strip 120”);
the encapsulating material comprises an uppermost surface facing away from the interposer (“adhesive strip 120” has a surface in contact with “front surface 106F” facing away from “Upper surface 108U” of “dielectric strip 108”), a lowermost surface facing the interposer (“adhesive strip 120” has a surface in contact with “Upper surface 108U” facing away from “front surface 106F”), and a lateral surface that extends between the uppermost surface and the lowermost surface (“adhesive strip 120” has left and right lateral surfaces); and
the lateral surface of the encapsulating material is parallel to the lateral die side (left and right lateral surfaces of “adhesive strip 120” and “electronic component 106-1” appear substantially coplanar in FIG. 13 after singulation); and
providing a conductive bump (“interconnection balls 1150” col 12 lines 47-48) coupled to the second conductive via.
However, Huemoeller fails to teach the second conductive via that extends outward from the second interposer side such that a portion of the second conductive via is below the second interposer side, wherein the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump.
Nevertheless, Yu teaches
the second conductive via (“through via 29” para. 0044 FIG. 5) that extends outward from the second interposer side (bottom of “substrate 17”, para. 0039) such that a portion of the second conductive via is below the second interposer side (“protrusion 35” of “through via 29” extends beyond the bottom surface of “substrate 17”, para. 0044 FIG. 44),
wherein the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump (“solder 33 melts and reforms to surround the through via protrusions 35” para. 0040).
Huemoeller and Yu teach multichip packages. Yu teaches “through vias 29” that protrude and connect to “substrate 19” or “system board 19” through “solder 33” (para. 0040). The way “through vias 29” protrude allow for direct connection between “substrate 17” and “system board 19” without the need of additional interposers or redistribution layers (para. 0021 and 0028). This reduces the package thickness and the amount of manufacturing steps (para. 0003 and 0021). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the “via 924” in Huemoeller can be formed to protrude like “through vias 29” from the interposer surface so that “interconnection balls 150” can be directly attached to “via 924”. This saves manufacturing costs and time and reduces package size.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device in Huemoeller with the extending via as taught in Yu. When the via extends below the second surface of the interposer, bump connections can be directly made to the via. This eliminates the need for redistribution structures or other interposers, increasing manufacturing efficiency and reducing package size.
Regarding claim 39, Huemoeller, modified by Yu, teaches the method of claim 38 but fails to expressly teach providing an under bump metal layer between the second conductive via and the conductive bump, and wherein at least a first portion of the under bump metal layer extends outward from the second interposer side.
Nevertheless, an alternate embodiment in Yu teaches a metallic “surface finish 49” that coats “protrusions 35” (para. 0044 FIG. 7). The “surface finish 49” prevents the copper of “protrusion 35” from being totally consumed by an intermetallic compound formed with the “solder 33” during the reflow process (para. 0044), serving as a barrier layer. This embodiment is used to form an assembly as the one in FIG. 5, so it is understood that “surface finish 49” is interposed between “protrusion 35” and “solder 33”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that “surface finish 49” prevents the copper is “through via 29” from diffusing and forming an intermetallic compound with “solder 33”, better retaining the original structure.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the semiconductor device taught between Huemoeller and Yu with the alternate embodiment in Yu. The under bump metal protects the material of the second via from forming intermetallic compounds.
Claim 24-25 is rejected under pre-AIA 35 U.S.C. 103 as being unpatentable over Huemoeller, in view of Yu, in view of Lin et al. US 20140048951 A1 (hereinafter referred to as Lin’51).
Regarding claim 24, Huemoeller, modified by Yu, teaches the semiconductor device of claim 21 but fails to teach comprising an adhesive layer directly on the first die side, wherein at least a portion of the adhesive layer is vertically higher from the interposer than the encapsulating material.
Nevertheless, Lin’51 teaches
an adhesive layer (“thermally conductive adhesive 801” para. 0054 FIG. 2) directly on the first die side (top side of “semiconductor chip 51”, para. 0054), wherein at least a portion of the adhesive layer is vertically higher from the interposer (“interposer 31” para. 0050) than the encapsulating material (“Encapsulant 71” para. 0054).
Huemoeller, modified by Yu and Lin’51 teach devices comprising a chip on an interposer. The device in Lin’51 features a “heat dissipation plate 81” in thermal contact with “semiconductor chip 51” through the “thermally conductive adhesive 801” (para. 0054). In this manner, heat can be dissipated away from the device. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that a “thermally conductive adhesive 801” can conduct heat from “semiconductor chip 51” towards a “heat dissipation plate 81”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught between Huemoeller and Yu with the adhesive layer taught in Lin’51. An adhesive with good thermal conduction can be used in conjunction with a heat dissipation plate to provide a path of heat dissipation for the device.
Regarding claim 25, Huemoeller, modified by Yu and Lin’51, teaches the he semiconductor device of claim 24, wherein the adhesive layer is vertically higher from the interposer than the encapsulating material (“thermally conductive adhesive 801” is vertically higher than “encapsulant 71” as seen in FIG. 2 of Lin).
Claims 31-34 are rejected under pre-AIA 35 U.S.C. 103 as being unpatentable over by Huemoeller US 6905914 B1 (hereinafter referred to as Huemoeller), in view of Yu et al. US 20130241057 A1 (hereinafter referred to as Yu), in view of Lin et al. US 20140048951 A1 (hereinafter referred to as Lin’51).
Regarding claim 31, Huemoeller teaches
A semiconductor device (“assembly 1200” col line FIG. 13) comprising:
an interposer (though not called interposer by name, the structure comprising “vias 624, 824, 924, traces 832, and lands 1044 formed in dielectric strips 108, 708, 908, and 1008”, col 12 lines 43-44 FIG. 13, has the same features known in the art for an interposer) comprising:
a first interposer side (“Upper surface 108U of dielectric strip 108”, col 12 line 33, top side of “dielectric strip 108” of interposer);
a second interposer side (bottom side of “dielectric strip 1008”) opposite the first interposer side;
a first dielectric layer (“dielectric strip 108”) at the first interposer side;
a first conductive via (“via 624”) that extends through at least the first dielectric layer;
a second conductive via (“via 924”) at the second interposer side; and
a redistribution structure (“vias 824” and “traces 832”) in contact with the first dielectric layer and electrically connected to the first conductive via and the second conductive via (“vias 824” and “traces 832” at least partially contact surfaces of “dielectric strip 108” and electrically connect “visa 624” and “vias 924” as seen in FIG. 13);
a semiconductor die (“electronic component 106-1” col 12 line 21 FIG. 13) comprising:
a first die side that faces away from the first interposer side (top side of “electronic component 106-1”);
a second die side that faces toward the first interposer side (“front surfaces 106F of electronic components 106-1”, col 12 lines 34, bottom side of “electronic component 106-1”) and comprises a die connection terminal (“bond pad 112” col 12 line 50) that is coupled to the first conductive via;
an encapsulating material over at least the second die side (though not called encapsulant by name, “adhesive strip 120” performs the function of an encapsulating material since it encapsulates the “front surface 106F” and “Upper surface 108U” and surrounds portions “vias 624”), wherein:
at least one other side of the semiconductor die is exposed from the encapsulating material (lateral sides and top side of “electronic component 106-1” are exposed from “adhesive strip 120”); and
the encapsulating material comprises an uppermost surface facing away from the interposer (“adhesive strip 120” has a surface in contact with “front surface 106F” facing away from “Upper surface 108U” of “dielectric strip 108”), a lowermost surface facing the interposer (“adhesive strip 120” has a surface in contact with “Upper surface 108U” facing away from “front surface 106F”), and a lateral surface that extends between the uppermost surface and the lowermost surface (“adhesive strip 120” has left and right lateral surfaces); and
However, Huemoeller fails to teach the second conductive via comprising a second side portion that extends outward from the second interposer side such that a portion of the second conductive via is below the second interposer side, wherein the second side portion of the second conductive via is disposed within the conductive bump, an adhesive layer on the first die side.
Nevertheless, Yu teaches
the second conductive via (“through via 29” para. 0044 FIG. 5) comprising a second side portion that extends outward from the second interposer side (“protrusion 35” of “through via 29” extends beyond the bottom surface of “substrate 17”, para. 0044 FIG. 44),
wherein the second side portion of the second conductive via is disposed within the conductive bump (“solder 33 melts and reforms to surround the through via protrusions 35” para. 0040).
Huemoeller and Yu teach multichip packages. Yu teaches “through vias 29” that protrude and connect to “substrate 19” or “system board 19” through “solder 33” (para. 0040). The way “through vias 29” protrude allow for direct connection between “substrate 17” and “system board 19” without the need of additional interposers or redistribution layers (para. 0021 and 0028). This reduces the package thickness and the amount of manufacturing steps (para. 0003 and 0021). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the “via 924” in Huemoeller can be formed to protrude like “through vias 29” from the interposer surface so that “interconnection balls 150” can be directly attached to “via 924”. This saves manufacturing costs and time and reduces package size.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device in Huemoeller with the extending via as taught in Yu. When the via extends below the second surface of the interposer, bump connections can be directly made to the via. This eliminates the need for redistribution structures or other interposers, increasing manufacturing efficiency and reducing package size.
However, Huemoeller fails to teach an adhesive layer on the first die side.
Nevertheless, Lin’51 A1teaches
an adhesive layer (“thermally conductive adhesive 801” para. 0054 FIG. 2) on the first die side (top side of “semiconductor chip 51”, para. 0054).
Huemoeller, modified by Yu, and Lin’51 teach devices comprising a chip on an interposer. The device in Lin’51 features a “heat dissipation plate 81” in thermal contact with “semiconductor chip 51” through the “thermally conductive adhesive 801” (para. 0054). In this manner, heat can be dissipated away from the device. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that a “thermally conductive adhesive 801” can conduct heat from “semiconductor chip 51” towards a “heat dissipation plate 81”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught between Huemoeller and Yu with the adhesive layer taught in Lin’51. An adhesive with good thermal conduction can be used in conjunction with a heat dissipation plate to provide a path of heat dissipation for the device.
Regarding claim 32, Huemoeller, modified by Yu and Lin’51, teaches the semiconductor device of claim 31, comprising a conductive bump (“interconnection balls 1150” col 12 lines 47-48) coupled to the second conductive via.
Regarding claim 33, Huemoeller, modified by Yu and Lin’51, teaches the semiconductor device of claim 32 but fails to teach comprising an underbump metal layer between the second conductive via and the conductive bump, and wherein at least a first portion of the underbump metal layer extends outward from the second interposer side.
Huemoeller, modified by Yu, teach the semiconductor device of claim 21, but fail to expressly teach comprising an under bump metal layer between the second conductive via and the conductive bump, and wherein at least a first portion of the under bump metal layer extends outward from the second interposer side.
Nevertheless, an alternate embodiment in Yu teaches a metallic “surface finish 49” that coats “protrusions 35” (para. 0044 FIG. 7). The “surface finish 49” prevents the copper of “protrusion 35” from being totally consumed by an intermetallic compound formed with the “solder 33” during the reflow process (para. 0044), serving as a barrier layer. This embodiment is used to form an assembly as the one in FIG. 5, so it is understood that “surface finish 49” is interposed between “protrusion 35” and “solder 33”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that “surface finish 49” prevents the copper is “through via 29” from diffusing and forming an intermetallic compound with “solder 33”, better retaining the original structure.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the semiconductor device taught between Huemoeller and Yu with the alternate embodiment in Yu. The under bump metal protects the material of the second via from forming intermetallic compounds.
Regarding claim 34, Huemoeller, modified by Yu and Lin’51, teach the semiconductor device of claim 33, wherein the conductive bump covers at least the first portion of the under bump metal layer that extends outward from the second interposer side (since “surface finish 49” coats the “protrusion 35” and is used to assemble a package as that of FIG. 5, it is understood that at least some of the “solder 33” covers a portion of “surface finish 49”, para. 0044).
Claims 21, 26-29, 38, and 40 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Warren et al. US 20120286408 A1 (hereinafter referred to as Warren) in view of Mizunashi US 20020139571 A1 (hereinafter referred to as Mizunashi), in view of Yu et al. US 20130241057 A1 (hereinafter referred to as Yu).
Regarding claim 21, Warren teaches
A semiconductor device (“WLP package with an interposer” para. 0049 FIG. 8B) comprising:
an interposer (“interposer 830” para. 0049) comprising:
a first interposer side (top side of “interposer 830” in FIG. 8B);
a second interposer side (bottom side of “interposer 830”) opposite the first interposer side;
a semiconductor die (“active die 812” para. 0049) comprising:
a first die side that faces away from the first interposer side (top of “active die 812” in FIG. 8B);
a first conductive via (“via 832” para. 0049);
a second die side (bottom of “active die 812”) that faces toward the first interposer side and comprises a die connection terminal (“metal pillars 822”) that is coupled to the first conductive via (“metal pillars 822” are coupled to “vias 832” through “bumps 824”, para. 0049); and
a lateral die side that extends between the first die side and the second die side (left and right lateral sides of “active die 812”);
an encapsulating material (“underfill 810”, which encapsulates the second die side and first side of interposer, para. 0049) over at least the second die side, wherein:
at least one other side of the semiconductor die is exposed from the encapsulating material (lateral sides of “active die 812” are exposed from “underfill 810);
the encapsulating material comprises an uppermost surface facing away from the interposer (“underfill 810” has a top side in contact with bottom of “active die 812” facing away from top side of “interposer 830”), a lowermost surface facing the interposer (“underfill 810” has a top side in contact with top side of “interposer 830” facing away from bottom of “active die 812”), and a lateral surface that extends between the uppermost surface and the lowermost surface (“underfill 810” has left and right lateral sides); and a lateral surface of the encapsulating material is parallel to the lateral die side (lateral sides of “underfill 810” are shown as coplanar in FIG. 8B after the dicing operation of the package shown in FIG. 8A); and
a conductive bump (“plating metal 836”, which may be solder material, para. 0049, 0071) coupled to the second conductive via.
However, Warren fails to teach a first dielectric layer at the first interposer side; a first conductive via that extends through at least the first dielectric layer; a second conductive via at the second interposer side; and a redistribution structure in contact with the first dielectric layer and electrically connected to the first conductive via and the second conductive via, teach the second conductive via that extends outward from the second interposer side such that a portion of the second conductive via is below the second interposer side, wherein the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump.
Nevertheless, Mizunashi teaches
a first dielectric layer (“insulating layer 21” para. 0043 FIG. 3) at the first interposer side (top side of “packaging substrate 1”, para. 0041);
a first conductive via (conductor in “via hole 23”, para. 0043) that extends through at least the first dielectric layer (“via hole 23” extends through “insulating layer 21”);
a second conductive via (conductor “via hole 33”) at the second interposer side (bottom side of “packaging substrate 1”); and
a redistribution structure (the structure comprising “core wiring layers 12 and 13”, which includes ground planes, signal line patterns, and power supply patterns, para. 0043-0044) in contact with the first dielectric layer (“core wiring layer 12” contacts “insulating layer 21”) and electrically connected to the first conductive via and the second conductive via (conductor in “via holes 23” is coupled to core wiring layer 12” and conductor in “via holes 33” are coupled to “core wiring layer 13”, para. 0046-0047).
Warren and Mizunashi teach devices comprising chips on interposer structures. The “interposer 830” only shows vias that have a similar pitch to the “metal pillars 822”. The “packaging substrate 1” in Mizunashi shows “flip chip terminals 5” of “device chip 3” having a certain pitch being redistributed by “core wiring layers 12 and 13” of “packaging substrate 1” to “solder balls 6” having a greater pitch. Mizunashi teaches in para. 0023 that device chips of different sizes can be bonded on “packaging substrate 1”. The device package can then be bonded onto another package or device with “solder balls 6”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the “package substrate 1” can redistribute signals from a “device chip 3” having “chip terminals 5” at a small pitch to another device having the pitch of the “solder balls 6”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught in Warren with the interposer as taught in Mizunashi. The multilayer interposer can accommodate chips of different sizes. Furthermore, having a redistribution layer and vias on each side of the interposer can route signals between chips having different external terminal pitches.
However, Warren, modified by Mizunashi, fails to teach the second conductive via that extends outward from the second interposer side such that a portion of the second conductive via is below the second interposer side, wherein the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump.
Nevertheless, Yu teaches
the second conductive via (“through via 29” para. 0044 FIG. 5) that extends outward from the second interposer side (bottom of “substrate 17”, para. 0039) such that a portion of the second conductive via is below the second interposer side (“protrusion 35” of “through via 29” extends beyond the bottom surface of “substrate 17”, para. 0044 FIG. 44),
wherein the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump (“solder 33 melts and reforms to surround the through via protrusions 35” para. 0040).
Warren, modified by Mizunashi, and Yu teach multichip packages. Yu teaches “through vias 29” that protrude and connect to “substrate 19” or “system board 19” through “solder 33” (para. 0040). The way “through vias 29” protrude allow for direct connection between “substrate 17” and “system board 19” without the need of additional interposers or redistribution layers and pads (para. 0003, 0021 and 0028). This reduces the package thickness and the amount of manufacturing steps (para. 0003 and 0021). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the conductors in “vias 33” in Mizunashi can be formed to protrude like “through vias 29” from the interposer surface so that “flip chip terminals 5” can be directly attached to the conductor in “via 33” instead of needing “electrodes 7”. This saves manufacturing costs and time and reduces package size.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device between Warren and Mizunashi with the extending via as taught in Yu. When the via extends below the second surface of the interposer, bump connections can be directly made to the via. This eliminates the need for extra redistribution structures such as pads or other interposers, increasing manufacturing efficiency and reducing package size.
Regarding claim 26, Warren, modified by Mizunashi and Yu, teaches the semiconductor device of claim 21, comprising solder (“bumps 824” which comprise solder, para. 0049, 0057) between the die connection terminal (“metal pillars 822”) and the first conductive via (“via 832”).
Regarding claim 27, Warren, modified by Mizunashi and Yu, teaches the semiconductor device of claim 21, wherein the die connection terminal comprises a conductive pillar (“metal pillar 822”) comprising:
a first pillar end toward the semiconductor die (upper end of “metal pillar 822” at “active die 812” side);
a second pillar end toward the interposer (lower end of “metal pillar 822” in contact with “bump 824”); and
a lateral pillar side that extends between the first pillar end and the second pillar end (“metal pillars 822” have lateral sides in contact with “underfill 810”).
Regarding claim 28, Warren, modified by Mizunashi and Yu, teaches the semiconductor device of claim 27, wherein the lateral pillar side is covered by the encapsulating material (“metal pillars 822” have lateral sides in contact with “underfill 810”).
Regarding claim 29, Warren, modified by Mizunashi and Yu, teaches the semiconductor device of claim 27, wherein the lateral surface of the encapsulating material is vertically longer than the conductive pillar (lateral surface of “underfill 810” extends from bottom of “active die 812” to top side of “interposer 830” while lateral side of “metal pillar 822” extends from bottom side of “active die 812” to the top of “bump 824”, as seen in FIG. 8B).
Regarding claim 38, Warren teaches
A method of manufacturing a semiconductor device (method of manufacturing “WLP package with an interposer” para. 0049 FIG. 8B), the method comprising:
Providing an interposer (“interposer 830” para. 0049) comprising:
a first interposer side (top side of “interposer 830” in FIG. 8B);
a second interposer side (bottom side of “interposer 830”) opposite the first interposer side;
providing a semiconductor die (“active die 812” para. 0049) comprising:
a first die side that faces away from the first interposer side (top of “active die 812” in FIG. 8B);
a first conductive via (“via 832” para. 0049);
a second die side (bottom of “active die 812”) that faces toward the first interposer side and comprises a die connection terminal (“metal pillars 822”) that is coupled to the first conductive via (“metal pillars 822” are coupled to “vias 832” through “bumps 824”, para. 0049); and
a lateral die side that extends between the first die side and the second die side (left and right lateral sides of “active die 812”);
providing an encapsulating material (“underfill 810”, which encapsulates the second die side and first side of interposer, para. 0049) over at least the second die side, wherein:
at least one other side of the semiconductor die is exposed from the encapsulating material (lateral sides of “active die 812” are exposed from “underfill 810);
the encapsulating material comprises an uppermost surface facing away from the interposer (“underfill 810” has a top side in contact with bottom of “active die 812” facing away from top side of “interposer 830”), a lowermost surface facing the interposer (“underfill 810” has a top side in contact with top side of “interposer 830” facing away from bottom of “active die 812”), and a lateral surface that extends between the uppermost surface and the lowermost surface (“underfill 810” has left and right lateral sides); and a lateral surface of the encapsulating material is parallel to the lateral die side (lateral sides of “underfill 810” are shown as coplanar in FIG. 8B after the dicing operation of the package shown in FIG. 8A); and
providing a conductive bump (“plating metal 836”, which may be solder material, para. 0049, 0071) coupled to the second conductive via.
However, Warren fails to teach a first dielectric layer at the first interposer side; a first conductive via that extends through at least the first dielectric layer; a second conductive via at the second interposer side; and a redistribution structure in contact with the first dielectric layer and electrically connected to the first conductive via and the second conductive via, the second conductive via that extends outward from the second interposer side such that a portion of the second conductive via is below the second interposer side, wherein the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump.
Nevertheless, Mizunashi teaches
a first dielectric layer (“insulating layer 21” para. 0043 FIG. 3) at the first interposer side (top side of “packaging substrate 1”, para. 0041);
a first conductive via (conductor in “via hole 23”, para. 0043) that extends through at least the first dielectric layer (“via hole 23” extends through “insulating layer 21”);
a second conductive via (conductor “via hole 33”) at the second interposer side (bottom side of “packaging substrate 1”); and
a redistribution structure (the structure comprising “core wiring layers 12 and 13”, which includes ground planes, signal line patterns, and power supply patterns, para. 0043-0044) in contact with the first dielectric layer (“core wiring layer 12” contacts “insulating layer 21”) and electrically connected to the first conductive via and the second conductive via (conductor in “via holes 23” is coupled to core wiring layer 12” and conductor in “via holes 33” are coupled to “core wiring layer 13”, para. 0046-0047).
Warren and Mizunashi teach devices comprising chips on interposer structures. The “interposer 830” only shows vias that have a similar pitch to the “metal pillars 822”. The “packaging substrate 1” in Mizunashi shows “chip terminals 5” of “device chip 3” having a certain pitch being redistributed by “core wiring layers 12 and 13” of “packaging substrate 1” to “solder balls 6” having a greater pitch. Mizunashi teaches in para. 0023 that device chips of different sizes can be bonded on “packaging substrate 1”. The device package can then be bonded onto another package or device with “solder balls 6”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the “package substrate 1” can redistribute signals from a “device chip 3” having “chip terminals 5” at a small pitch to another device having the pitch of the “solder balls 6”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing a semiconductor device taught in Warren with the interposer as taught in Mizunashi. The multilayer interposer can accommodate chips of different sizes. Furthermore, having a redistribution layer and vias on each side of the interposer can route signals between chips having different external terminal pitches.
However, Warren, modified by Mizunashi, fails to teach the second conductive via that extends outward from the second interposer side such that a portion of the second conductive via is below the second interposer side, wherein the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump.
Nevertheless, Yu teaches
the second conductive via (“through via 29” para. 0044 FIG. 5) that extends outward from the second interposer side (bottom of “substrate 17”, para. 0039) such that a portion of the second conductive via is below the second interposer side (“protrusion 35” of “through via 29” extends beyond the bottom surface of “substrate 17”, para. 0044 FIG. 44),
wherein the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump (“solder 33 melts and reforms to surround the through via protrusions 35” para. 0040).
Warren, modified by Mizunashi, and Yu teach multichip packages. Yu teaches “through vias 29” that protrude and connect to “substrate 19” or “system board 19” through “solder 33” (para. 0040). The way “through vias 29” protrude allow for direct connection between “substrate 17” and “system board 19” without the need of additional interposers or redistribution layers and pads (para. 0003, 0021 and 0028). This reduces the package thickness and the amount of manufacturing steps (para. 0003 and 0021). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the conductors in “vias 33” in Mizunashi can be formed to protrude like “through vias 29” from the interposer surface so that “flip chip terminals 5” can be directly attached to the conductor in “via 33” instead of needing “electrodes 7”. This saves manufacturing costs and time and reduces package size.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device between Warren and Mizunashi with the extending via as taught in Yu. When the via extends below the second surface of the interposer, bump connections can be directly made to the via. This eliminates the need for extra redistribution structures such as pads or other interposers, increasing manufacturing efficiency and reducing package size.
Regarding claim 40, Warren, modified by Mizunashi and Yu, teaches the method of claim 38, wherein providing the encapsulating material over at least the second die side comprises covering a lateral side of the die connection terminal with the encapsulating material (“metal pillars 822” have lateral sides in contact with “underfill 810”).
Claims 31, 35-37, and 42 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Warren, in view of Mizunashi, in view of Yu, and in view of Lin’51.
Regarding claim 31, Warren teaches
A semiconductor device (“WLP package with an interposer” para. 0049 FIG. 8B) comprising:
an interposer (“interposer 830” para. 0049) comprising:
a first interposer side (top side of “interposer 830” in FIG. 8B);
a second interposer side (bottom side of “interposer 830”) opposite the first interposer side;
a semiconductor die (“active die 812” para. 0049) comprising:
a first die side that faces away from the first interposer side (top of “active die 812” in FIG. 8B);
a first conductive via (“via 832” para. 0049);
a second die side (bottom of “active die 812”) that faces toward the first interposer side and comprises a die connection terminal (“metal pillars 822”) that is coupled to the first conductive via (“metal pillars 822” are coupled to “vias 832” through “bumps 824”, para. 0049); and
an encapsulating material (“underfill 810”, which encapsulates the second die side and first side of interposer, para. 0049) over at least the second die side, wherein:
at least one other side of the semiconductor die is exposed from the encapsulating material (lateral sides of “active die 812” are exposed from “underfill 810);
the encapsulating material comprises an uppermost surface facing away from the interposer (“underfill 810” has a top side in contact with bottom of “active die 812” facing away from top side of “interposer 830”), a lowermost surface facing the interposer (“underfill 810” has a top side in contact with top side of “interposer 830” facing away from bottom of “active die 812”), and a lateral surface that extends between the uppermost surface and the lowermost surface (“underfill 810” has left and right lateral sides); and a lateral surface of the encapsulating material is parallel to the lateral die side (lateral sides of “underfill 810” are shown as coplanar in FIG. 8B after the dicing operation of the package shown in FIG. 8A); and
a conductive bump (“plating metal 836”, which may be solder material, para. 0049, 0071) coupled to the second conductive via.
However, Warren fails to teach a first dielectric layer at the first interposer side; a first conductive via that extends through at least the first dielectric layer; a second conductive via comprising a second side portion that extends outward from the second interposer side; and a redistribution structure in contact with the first dielectric layer and electrically connected to the first conductive via and the second conductive via, an adhesive layer on the first die side, the second conductive via comprising a second side portion that extends outward from the second interposer side such that a portion of the second conductive via is below the second interposer side, wherein the second side portion of the second conductive via is disposed within the conductive bump.
Nevertheless, Mizunashi teaches
a first dielectric layer (“insulating layer 21” para. 0043 FIG. 3) at the first interposer side (top side of “packaging substrate 1”, para. 0041);
a first conductive via (conductor in “via hole 23”, para. 0043) that extends through at least the first dielectric layer (“via hole 23” extends through “insulating layer 21”);
a second conductive via (conductor “via hole 33”) at the second interposer side (bottom side of “packaging substrate 1”); and
a redistribution structure (the structure comprising “core wiring layers 12 and 13”, which includes ground planes, signal line patterns, and power supply patterns, para. 0043-0044) in contact with the first dielectric layer (“core wiring layer 12” contacts “insulating layer 21”) and electrically connected to the first conductive via and the second conductive via (conductor in “via holes 23” is coupled to core wiring layer 12” and conductor in “via holes 33” are coupled to “core wiring layer 13”, para. 0046-0047).
Warren and Mizunashi teach devices comprising chips on interposer structures. The “interposer 830” only shows vias that have a similar pitch to the “metal pillars 822”. The “packaging substrate 1” in Mizunashi shows “chip terminals 5” of “device chip 3” having a certain pitch being redistributed by “core wiring layers 12 and 13” of “packaging substrate 1” to “solder balls 6” having a greater pitch. Mizunashi teaches in para. 0023 that device chips of different sizes can be bonded on “packaging substrate 1”. The device package can then be bonded onto another package or device with “solder balls 6”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the “package substrate 1” can redistribute signals from a “device chip 3” having “chip terminals 5” at a small pitch to another device having the pitch of the “solder balls 6”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught in Warren with the interposer as taught in Mizunashi. The multilayer interposer can accommodate chips of different sizes. Furthermore, having a redistribution layer and vias on each side of the interposer can route signals between chips having different external terminal pitches.
However, Warren, modified by Mizunashi, fails to teach comprising an adhesive layer on the first die side, the second conductive via comprises a second side portion that extends outward from the second interposer side, wherein the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump.
Nevertheless, Lin’51 teaches
an adhesive layer (“thermally conductive adhesive 801” para. 0054 FIG. 2) directly on the first die side (top side of “semiconductor chip 51”, para. 0054), wherein at least a portion of the adhesive layer is vertically higher from the interposer (“interposer 31” para. 0050) than the encapsulating material (“Encapsulant 71” para. 0054).
Warren, modified by Mizunashi, and Lin’51 teach devices comprising a chip on an interposer. The device in Lin’51 features a “heat dissipation plate 81” in thermal contact with “semiconductor chip 51” through the “thermally conductive adhesive 801” (para. 0054). In this manner, heat can be dissipated away from the device. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that a “thermally conductive adhesive 801” can conduct heat from “semiconductor chip 51” towards a “heat dissipation plate 81”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught between Warren and Mizunashi with the adhesive layer taught in Lin’51. An adhesive with good thermal conduction can be used in conjunction with a heat dissipation plate to provide a path of heat dissipation for the device.
However, Warren, modified by Mizunashi and Lin’51, fails to teach the second conductive via comprises a second side portion that extends outward from the second interposer side, wherein the second side portion of the second conductive via is disposed within the conductive bump.
Nevertheless, Yu teaches
the second conductive via (“through via 29” para. 0044 FIG. 5) comprises a second side portion that extends outward from the second interposer side (“protrusion 35” of “through via 29” extends beyond the bottom surface of “substrate 17”, para. 0044 FIG. 44),
wherein the portion of the second conductive via is disposed within the conductive bump (“solder 33 melts and reforms to surround the through via protrusions 35” para. 0040).
Warren, modified by Mizunashi, and Yu teach multichip packages. Yu teaches “through vias 29” that protrude and connect to “substrate 19” or “system board 19” through “solder 33” (para. 0040). The way “through vias 29” protrude allow for direct connection between “substrate 17” and “system board 19” without the need of additional interposers or redistribution layers and pads (para. 0003, 0021 and 0028). This reduces the package thickness and the amount of manufacturing steps (para. 0003 and 0021). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the conductors in “vias 33” in Mizunashi can be formed to protrude like “through vias 29” from the interposer surface so that “flip chip terminals 5” can be directly attached to the conductor in “via 33” instead of needing “electrodes 7”. This saves manufacturing costs and time and reduces package size.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device between Warren, Mizunashi, and Lin’51 with the extending via as taught in Yu. When the via extends below the second surface of the interposer, bump connections can be directly made to the via. This eliminates the need for extra redistribution structures such as pads or other interposers, increasing manufacturing efficiency and reducing package size.
Regarding claim 35, Warren, modified by Minuzashi, Lin’51, and Yu, teaches the semiconductor device of claim 31, wherein the die connection terminal comprises a conductive pillar (“metal pillar 822”) comprising:
a first pillar end toward the semiconductor die (upper end of “metal pillar 822” at “active die 812” side);
a second pillar end toward the interposer (lower end of “metal pillar 822” in contact with “bump 824”); and
a lateral pillar side that extends between the first pillar end and the second pillar end (“metal pillars 822” have lateral sides in contact with “underfill 810”).
Regarding claim 36, Warren, modified by Minuzashi, Lin’51, and Yu, teaches the semiconductor device of claim 35, wherein the lateral pillar side is covered by the encapsulating material (“metal pillars 822” have lateral sides in contact with “underfill 810”).
Regarding claim 37, Warren, modified by Minuzashi, Lin’51, and Yu, teaches the semiconductor device of claim 36, wherein the lateral surface of the encapsulating material is vertically longer than the conductive pillar (lateral surface of “underfill 810” extends from bottom of “active die 812” to top side of “interposer 830” while lateral side of “metal pillar 822” extends from bottom side of “active die 812” to the top of “bump 824”, as seen in FIG. 8B).
Regarding claim 42, Warren, modified by Minuzashi, Lin’51, and Yu semiconductor device of claim 31 but fail to expressly teach comprising: an under bump metal layer comprising a portion that covers the second side portion of the second conductive via; and wherein the portion of the under bump metal layer covering the second side portion of the second conductive via is disposed within the conductive bump.
Nevertheless, an alternate embodiment in Yu teaches a metallic “surface finish 49” that coats “protrusions 35” (para. 0044 FIG. 7). The “surface finish 49” prevents the copper of “protrusion 35” from being totally consumed by an intermetallic compound formed with the “solder 33” during the reflow process (para. 0044), serving as a barrier layer. This embodiment is used to form an assembly as the one in FIG. 5, so it is understood that “surface finish 49” is within “solder 33”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that “surface finish 49” prevents the copper is “through via 29” from diffusing and forming an intermetallic compound with “solder 33”, better retaining the original structure.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the semiconductor device taught between Huemoeller and Yu with the alternate embodiment in Yu. The under bump metal protects the material of the second via from forming intermetallic compounds.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21-30 and 41 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 21, 24, and 26-30 of U.S. Patent No. 11527496, in view of Warren et al. US 20120286408 A1 (hereinafter referred to as Warren), in view of Yu et al. US 20130241057 A1 (hereinafter referred to as Yu).
Regarding claim 21, the limitation in the instant application “the lateral surface of the encapsulating material is parallel to the lateral die side” and the limitation in in U.S. Patent No. 11527496 “no portion of the encapsulating material is substantially vertically higher than the first die side” are not identical, as shown in the table below. Claim 21 of the instant application contains the limitation “extends between the uppermost surface and the lowermost surface” that is not patentably distinct from “extends entirely between the uppermost surface and the lowermost surface” in U.S. Patent No. 11527496. The limitation in U.S. Patent No. 11527496 is considered a species of the limitation of the instant application. It has been held that a generic invention is “anticipated” by a “species” within the scope of the generic invention. See In re Goodman, 29 USPQ2d 2010 (Fed. Cir. 1993).
Instant application
U.S. Patent No. 11527496
an interposer comprising
interposer
a first interposer side
first interposer side
a second interposer side opposite the first interposer side;
second interposer side opposite the first interposer side
a first dielectric layer at the first interposer side;
first dielectric layer at the first interposer side
a first conductive via that extends through at least the first dielectric layer;
first conductive via that extends through at least the first dielectric layer
a second conductive via at the second interposer side; and
second conductive via at the second interposer side
a redistribution structure in contact with the first dielectric layer and electrically connected to the first conductive via and the second conductive via;
redistribution structure in contact with the first dielectric layer and electrically connected to the first conductive via and the second conductive via
a semiconductor die comprising
a semiconductor die comprising
a first die side that faces away from the first interposer side;
a first die side that faces away from the first interposer side
a second die side that faces toward the first interposer side and comprises a die connection terminal that is coupled to the first conductive via; and
a second die side that faces toward the first interposer side and comprises a die connection terminal that is coupled to the first conductive via
a lateral die side that extends between the first die side and the second die side;
a lateral die side that extends between the first die side and the second die side
an encapsulating material over at least the second die side, wherein:
an encapsulating material that covers at least the second die side
at least one other side of the semiconductor die is exposed from the encapsulating material;
and leaves exposed at least one other side of the semiconductor die
the encapsulating material comprises an uppermost surface facing away from the interposer, a lowermost surface facing the interposer, and a lateral surface that extends between the uppermost surface and the lowermost surface; and
the encapsulating material comprises an uppermost surface facing away from the interposer, a lowermost surface facing the interposer, and a lateral surface that extends entirely between the uppermost surface and the lowermost surface
the lateral surface of the encapsulating material is parallel to the lateral die side; and
no portion of the encapsulating material is substantially vertically higher than the first die side
a conductive bump coupled to the second conductive via.
a conductive bump coupled to the second conductive via
the second conductive via that extends outward from the second interposer side such that a portion of the second conductive via is below the second interposer side,
wherein the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump
Claim 21 of U.S. Patent No. 11527496 fails to teach the lateral surface of the encapsulating material is parallel to the lateral die side, the second conductive via that extends outward from the second interposer side such that a portion of the second conductive via is below the second interposer side, wherein the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump.
Nevertheless, Warren teaches “active die 812” bonded to “interposer 830” and an “underfill 810” with side surfaces coplanar to “active die 812” and “interposer 830” side surfaces (para. 0049). The side surfaces are coplanar because each package comprising a “active die 812” and an “interposer 830” was singulated from two bonded wafers, as seen in FIG. 8A. In this manner, both wafers can be aligned and bonded once and only one singulation step is required instead of having to singulate each “active die 812” or “interposer 830” first and then bond them together, as shown in alternate embodiments in Warren. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the side surfaces of “underfill 810” and “active die 812” will be coplanar when both components are bonded at wafer level and then the boded wafer are diced.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify claim 21 of U.S. Patent No. 11527496 with the arrangement taught in Warren. The parallel encapsulant side surface and first die side are a result of dicing the semiconductor chip and the interposer after a wafer level package has been bonded. This is favorable due to only requiring a single alignment step and a single singulation step to form the semiconductor device.
However, U.S. Patent No. 11527496, in view of Warren, fails to teach the second conductive via that extends outward from the second interposer side such that a portion of the second conductive via is below the second interposer side, wherein the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump.
Nevertheless, Yu teaches
the second conductive via (“through via 29” para. 0044 FIG. 5) that extends outward from the second interposer side (bottom of “substrate 17”, para. 0039) such that a portion of the second conductive via is below the second interposer side (“protrusion 35” of “through via 29” extends beyond the bottom surface of “substrate 17”, para. 0044 FIG. 44),
wherein the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump (“solder 33 melts and reforms to surround the through via protrusions 35” para. 0040).
U.S. Patent No. 11527496, in view of Warren, and Yu teach multichip packages. Yu teaches “through vias 29” that protrude and connect to “substrate 19” or “system board 19” through “solder 33” (para. 0040). The way “through vias 29” protrude allow for direct connection between “substrate 17” and “system board 19” without the need of additional interposers or redistribution layers (para. 0021 and 0028). This reduces the package thickness and the amount of manufacturing steps (para. 0003 and 0021). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the second conductive via in U.S. Patent No. 11527496 can be formed to protrude like “through vias 29” from the interposer surface so that the conductive bump can be directly attached to the second conductive via. This saves manufacturing costs and time and reduces package size.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught between U.S. Patent No. 11527496 and Warren with the extending via as taught in Yu. When the via extends below the second surface of the interposer, bump connections can be directly made to the via. This eliminates the need for redistribution structures or other interposers, increasing manufacturing efficiency and reducing package size.
The following table shows the correspondence between claims 22-30 of the instant application and claims 22, 24, and 26-30 of the cited patent. The claimed subject appears identical.
Instant application
Patent
Claim 22
Claim 22
The semiconductor device of claim 21, comprising an under bump metal layer between the second conductive via and the conductive bump, and wherein at least a first portion of the under bump metal layer extends outward from the second interposer side.
The semiconductor device of claim 21, comprising an under bump metal layer between the second conductive via and the conductive bump, and wherein at least a first portion of the under bump metal layer extends outward from the second interposer side.
Claim 23
Claim 24
The semiconductor device of claim 21, comprising a second dielectric material directly contacting at least one surface of the encapsulating material.
The semiconductor device of claim 21, comprising a second dielectric material directly contacting at least one surface of the encapsulating material.
Claim 24
Claim 26
The semiconductor device of claim 21, comprising an adhesive layer directly on the first die side, wherein at least a portion of the adhesive layer is vertically higher from the interposer than the encapsulating material.
The semiconductor device of claim 21, comprising an adhesive layer directly on the first die side, wherein at least a portion of the adhesive layer is vertically higher from the interposer than the encapsulating material.
Claim 25
Claim 27
The semiconductor device of claim 24, wherein the adhesive layer is vertically higher from the interposer than the encapsulating material.
The semiconductor device of claim 26, wherein the entire adhesive layer is vertically higher from the interposer than the encapsulating material
Claim 26
Claim 28
The semiconductor device of claim 21, comprising solder between the die connection terminal and the first conductive via.
The semiconductor device of claim 21, comprising solder between the die connection terminal and the first conductive via.
Claims 27-29
Claim 29
The semiconductor device of claim 21, wherein the die connection terminal comprises a conductive pillar comprising: a first pillar end toward the semiconductor die; a second pillar end toward the interposer; and a lateral pillar side that extends between the first pillar end and the second pillar end.
The semiconductor device of claim 21, wherein: the die connection terminal comprises a copper pillar comprising: a first pillar end toward the semiconductor die, a second pillar end toward the interposer, and a lateral pillar side that extends between the first pillar end and the second pillar end; the lateral pillar side is covered by the encapsulating material; and the lateral surface of the encapsulating material is vertically longer than the copper pillar.
The semiconductor device of claim 27, wherein the lateral pillar side is covered by the encapsulating material.
The semiconductor device of claim 27, wherein the lateral surface of the encapsulating material is vertically longer than the conductive pillar.
Claim 30
Claim 30
The semiconductor device of claim 21, wherein: the interposer comprises a lateral interposer side that extends between the first interposer side and the second interposer side; and the lateral interposer side is parallel to the lateral die side and to the lateral surface of the encapsulating material.
The semiconductor device of claim 21, wherein: the interposer comprises a lateral interposer side that extends between the first interposer side and the second interposer side; and the lateral interposer side is parallel to the lateral die side and to the lateral surface of the encapsulating material.
Regarding claim 41, U.S. Patent No. 11527496, modified by Warren and Yu, teaches the semiconductor device of claim 21 but fail to expressly teach comprising: an under bump metal layer comprising a portion that covers the portion of the second conductive via that is below the second interposer side; and wherein the portion of the under bump metal layer covering the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump.
Nevertheless, an alternate embodiment in Yu teaches a metallic “surface finish 49” that coats “protrusions 35” (para. 0044 FIG. 7). The “surface finish 49” prevents the copper of “protrusion 35” from being totally consumed by an intermetallic compound formed with the “solder 33” during the reflow process (para. 0044), serving as a barrier layer. This embodiment is used to form an assembly as the one in FIG. 5, so it is understood that “surface finish 49” is within “solder 33”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that “surface finish 49” prevents the copper is “through via 29” from diffusing and forming an intermetallic compound with “solder 33”, better retaining the original structure.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the semiconductor device taught between U.S. Patent No. 11527496, Warren and Yu with the alternate embodiment in Yu. The under bump metal protects the material of the second via from forming intermetallic compounds.
Claims 31-37 and 42 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 31 and 35-37 of U.S. Patent No. 11527496 in view of Lin et al US 20140048951 A1 (hereinafter referred to as Lin’51), in view of Yu et al. US 20130241057 A1 (hereinafter referred to as Yu).
Regarding claim 31, the limitations of the current application are substantially similar to those of claim 31 of U.S. Patent No. 1152749 with the exception of “an adhesive layer on the first die side” and “the second conductive via that extends outward from the second interposer side such that a portion of the second conductive via is below the second interposer side, wherein the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump”, as can be seen in the following table.
Instant application claim 31
U.S. Patent No. 11527496 claim 31
A semiconductor device comprising
A semiconductor device comprising
an interposer comprising
an interposer comprising
a first interposer side
a first interposer side
a second interposer side opposite the first interposer side
a second interposer side opposite the first interposer side
a first dielectric layer at the first interposer side
a first dielectric layer at the first interposer side
a first conductive via that extends through at least the first dielectric layer
a first conductive via that extends through at least the first dielectric layer
a second conductive via at the second interposer side
a second conductive via at the second interposer side
a redistribution structure in contact with the first dielectric layer and electrically connected to the first conductive via and the second conductive via
a redistribution structure in contact with the first dielectric layer and electrically connected to the first conductive via and the second conductive via
a semiconductor die comprising
a semiconductor die comprising
a first die side that faces away from the first interposer side
a first die side that faces away from the first interposer side
a second die side that faces toward the first interposer side and comprises a die connection terminal that is coupled to the first conductive via
a second die side that faces toward the first interposer side and comprises a die connection terminal that is coupled to the first conductive via
an encapsulating material over at least the second die side
an encapsulating material that covers at least the second die side and leaves exposed at least one other side of the semiconductor die
wherein:at least one other side of the semiconductor die is exposed from the encapsulating material
the encapsulating material comprises an uppermost surface facing away from the interposer
the encapsulating material comprises an uppermost surface facing away from the interposer
a lowermost surface facing the interposer
a lowermost surface facing the interposer
a lateral surface that extends between the uppermost surface and the lowermost surface;
a lateral surface that extends entirely between the uppermost surface and the lowermost surface;
an adhesive layer on the first die side
the second conductive via that extends outward from the second interposer side such that a portion of the second conductive via is below the second interposer side,
wherein the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump.
Nevertheless, Lin’51 teaches a “thermally conductive adhesive 801” on top side of “semiconductor chip 51” (para. 0054 FIG. 2). The device in Lin features a “heat dissipation plate 81” in thermal contact with “semiconductor chip 51” through the “thermally conductive adhesive 801” (para. 0054). In this manner, heat can be dissipated away from the device. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that a “thermally conductive adhesive 801” can conduct heat from “semiconductor chip 51” towards a “heat dissipation plate 81”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught in claim 31 of U.S. Patent No. 11527496 with the adhesive layer taught in Lin’51. An adhesive with good thermal conduction can be used in conjunction with a heat dissipation plate to provide a path of heat dissipation for the device.
However, U.S. Patent No. 11527496, in view of Lin’51, fails to teach the second conductive via that extends outward from the second interposer side such that a portion of the second conductive via is below the second interposer side, wherein the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump.
Nevertheless, Yu teaches
the second conductive via (“through via 29” para. 0044 FIG. 5) that extends outward from the second interposer side (bottom of “substrate 17”, para. 0039) such that a portion of the second conductive via is below the second interposer side (“protrusion 35” of “through via 29” extends beyond the bottom surface of “substrate 17”, para. 0044 FIG. 44),
wherein the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump (“solder 33 melts and reforms to surround the through via protrusions 35” para. 0040).
U.S. Patent No. 11527496, in view of Lin’51, and Yu teach multichip packages. Yu teaches “through vias 29” that protrude and connect to “substrate 19” or “system board 19” through “solder 33” (para. 0040). The way “through vias 29” protrude allow for direct connection between “substrate 17” and “system board 19” without the need of additional interposers or redistribution layers (para. 0021 and 0028). This reduces the package thickness and the amount of manufacturing steps (para. 0003 and 0021). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the second conductive via in U.S. Patent No. 11527496 can be formed to protrude like “through vias 29” from the interposer surface so that the conductive bump can be directly attached to the second conductive via. This saves manufacturing costs and time and reduces package size.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught between U.S. Patent No. 11527496 and Lin’51 with the extending via as taught in Yu. When the via extends below the second surface of the interposer, bump connections can be directly made to the via. This eliminates the need for redistribution structures or other interposers, increasing manufacturing efficiency and reducing package size.
The following table shows the correspondence between claims 32-37 of the instant application and claims 31 and 35-37 of U.S. Patent No. 11527496, which appear identical.
Application Claim 32
U.S. Patent No. 11527496 Claim 31
The semiconductor device of claim 31, comprising a conductive bump coupled to the second conductive via.
a conductive bump coupled to the second conductive via
Claim 33
Claim 35
The semiconductor device of claim 32, comprising an under bump metal layer between the second conductive via and the conductive bump, and wherein at least a first portion of the under bump metal layer extends outward from the second interposer side.
comprising an under bump metal layer between the second conductive via and the conductive bump, and wherein at least a first portion of the under bump metal layer extends outward from the second interposer side
Claim 34
Claim 36
The semiconductor device of claim 33, wherein the conductive bump covers at least the first portion of the under bump metal layer that extends outward from the second interposer side.
wherein the conductive bump completely covers said at least a first portion of the under bump metal layer that extends outward from the second interposer side.
Claim 35
Claim 37
The semiconductor device of claim 31, wherein the die connection terminal comprises a conductive pillar comprising: a first pillar end toward the semiconductor die; a second pillar end toward the interposer; and a lateral pillar side that extends between the first pillar end and the second pillar end.
wherein: the die connection terminal comprises a copper pillar comprising: a first pillar end toward the semiconductor die, a second pillar end toward the interposer, and a lateral pillar side that extends between the first pillar end and the second pillar end; the lateral pillar side is covered by the encapsulating material; and the lateral surface of the encapsulating material is vertically longer than the copper pillar.
Claim 36
The semiconductor device of claim 35, wherein the lateral pillar side is covered by the encapsulating material.
Claim 37
The semiconductor device of claim 36, wherein the lateral surface of the encapsulating material is vertically longer than the conductive pillar.
Regarding claim 42, U.S. Patent No. 11527496, in view of Lin’51, and Yu teach the semiconductor device of claim 31 but fail to expressly teach comprising: an under bump metal layer comprising a portion that covers the second side portion of the second conductive via; and wherein the portion of the under bump metal layer covering the second side portion of the second conductive via is disposed within the conductive bump.
Nevertheless, an alternate embodiment in Yu teaches a metallic “surface finish 49” that coats “protrusions 35” (para. 0044 FIG. 7). The “surface finish 49” prevents the copper of “protrusion 35” from being totally consumed by an intermetallic compound formed with the “solder 33” during the reflow process (para. 0044), serving as a barrier layer. This embodiment is used to form an assembly as the one in FIG. 5, so it is understood that “surface finish 49” is within “solder 33”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that “surface finish 49” prevents the copper is “through via 29” from diffusing and forming an intermetallic compound with “solder 33”, better retaining the original structure.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the semiconductor device taught between U.S. Patent No. 11527496, Lin’51, and Yu with the alternate embodiment in Yu. The under bump metal protects the material of the second via from forming intermetallic compounds.
Claims 38-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 38 of U.S. Patent No. 11527496 in view of Warren, in view of Yu.
Regarding claim 38, the limitations appear identical to those in claim 38 of U.S. Patent No. 11527496 except for “the second conductive via that extends outward from the second interposer side such that a portion of the second conductive via is below the second interposer side, wherein the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump” as shown below. The claim of the instant application contains the limitation “extends between the uppermost surface and the lowermost surface” that is not patentably distinct from “extends entirely between the uppermost surface and the lowermost surface” in U.S. Patent No. 11527496. The limitation in U.S. Patent No. 11527496 is considered a species of the limitation of the instant application. It has been held that a generic invention is “anticipated” by a “species” within the scope of the generic invention. See In re Goodman, 29 USPQ2d 2010 (Fed. Cir. 1993).
Instant application claim 38
U.S. Patent No. 11527496 claim 38
A method of manufacturing a semiconductor device, the method comprising:
A method of manufacturing a semiconductor device, the method comprising:
providing an interposer comprising
providing an interposer comprising
a first interposer side
a first interposer side
a second interposer side opposite the first interposer side
a second interposer side opposite the first interposer side
a first dielectric layer at the first interposer side
a first dielectric layer at the first interposer side
a first conductive via that extends through at least the first dielectric layer
a first conductive via that extends through at least the first dielectric layer
a second conductive via at the second interposer side
a second conductive via at the second interposer side
and a redistribution structure in contact with the first dielectric layer and electrically connected to the first conductive via and the second conductive via
and a redistribution structure in contact with the first dielectric layer and electrically connected to the first conductive via and the second conductive via
providing a semiconductor die comprising
providing a semiconductor die comprising
a first die side that faces away from the first interposer side
a first die side that faces away from the first interposer side
a second die side that faces toward the first interposer side and comprises a die connection terminal that is coupled to the first conductive via
a second die side that faces toward the first interposer side and comprises a die connection terminal that is coupled to the first conductive via
a lateral die side that extends between the first die side and the second die side
a lateral die side that extends between the first die side and the second die side
providing an encapsulating material over at least the second die side
providing an encapsulating material that covers at least the second die side and leaves exposed at least one other side of the semiconductor die
at least one other side of the semiconductor die is exposed from the encapsulating material
the encapsulating material comprises an uppermost surface facing away from the interposer
the encapsulating material comprises an uppermost surface facing away from the interposer
a lowermost surface facing the interposer
a lowermost surface facing the interposer
a lateral surface that extends between the uppermost surface and the lowermost surface
a lateral surface that extends entirely between the uppermost surface and the lowermost surface
the lateral surface of the encapsulating material is parallel to the lateral die side
the lateral surface of the encapsulating material is parallel to the lateral die side
providing a conductive bump coupled to the second conductive via
providing a conductive bump coupled to the second conductive via
the second conductive via that extends outward from the second interposer side such that a portion of the second conductive via is below the second interposer side,
wherein the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump.
U.S. Patent No. 11527496 fails to teach the second conductive via that extends outward from the second interposer side such that a portion of the second conductive via is below the second interposer side, wherein the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump.
Nevertheless, Yu teaches
the second conductive via (“through via 29” para. 0044 FIG. 5) that extends outward from the second interposer side (bottom of “substrate 17”, para. 0039) such that a portion of the second conductive via is below the second interposer side (“protrusion 35” of “through via 29” extends beyond the bottom surface of “substrate 17”, para. 0044 FIG. 44),
wherein the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump (“solder 33 melts and reforms to surround the through via protrusions 35” para. 0040).
U.S. Patent No. 11527496, in view of Lin’51, and Yu teach multichip packages. Yu teaches “through vias 29” that protrude and connect to “substrate 19” or “system board 19” through “solder 33” (para. 0040). The way “through vias 29” protrude allow for direct connection between “substrate 17” and “system board 19” without the need of additional interposers or redistribution layers (para. 0021 and 0028). This reduces the package thickness and the amount of manufacturing steps (para. 0003 and 0021). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the second conductive via in U.S. Patent No. 11527496 can be formed to protrude like “through vias 29” from the interposer surface so that the conductive bump can be directly attached to the second conductive via. This saves manufacturing costs and time and reduces package size.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught between U.S. Patent No. 11527496 and Lin’51 with the extending via as taught in Yu. When the via extends below the second surface of the interposer, bump connections can be directly made to the via. This eliminates the need for redistribution structures or other interposers, increasing manufacturing efficiency and reducing package size.
Regarding claim 39, U.S. Patent No. 11527496 fails to teach providing an under bump metal layer between the second conductive via and the conductive bump, and wherein at least a first portion of the under bump metal layer extends outward from the second interposer side.
Nevertheless, an alternate embodiment in Yu teaches a metallic “surface finish 49” that coats “protrusions 35” (para. 0044 FIG. 7). The “surface finish 49” prevents the copper of “protrusion 35” from being totally consumed by an intermetallic compound formed with the “solder 33” during the reflow process (para. 0044), serving as a barrier layer. This embodiment is used to form an assembly as the one in FIG. 5, so it is understood that “surface finish 49” is interposed between “protrusion 35” and “solder 33”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that “surface finish 49” prevents the copper is “through via 29” from diffusing and forming an intermetallic compound with “solder 33”, better retaining the original structure.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the semiconductor device taught between Huemoeller and Yu with the alternate embodiment in Yu. The under bump metal protects the material of the second via from forming intermetallic compounds.
Regarding claim 40, U.S. Patent No. 11527496, modified by Yu, fails to teach wherein providing the encapsulating material over at least the second die side comprises covering a lateral side of the die connection terminal with the encapsulating material.
Nevertheless, Warren teaches “active die 812” and “interposer 830” bonded using “metal pillars 822” (para. 0049). Pillars are a known structure for bonding semiconductor devices. “Underfill 810” fills the space between “active die 812” and “interposer 830” and covering sidewalls of “metal pillars 822” (para. 0049 FIG. 8B). “Underfill 810” is made of mold compound that hardens after filling the gap (para. 0057) and the examiner understands that such materials are used to improve the sturdiness of packages. The “metal pillars 822” can be better protected from deformation with “underfill 810” around them and “active die 812” and “interposer 830” can also be protected from bending. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that “underfill 810” improves the reliability of the bonded “interposer 830” and “active die 812” from physical damage when “metal pillars 822” as die connection terminals are used.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the encapsulant will cover a lateral side of the die connection terminal that extends beyond the surface of the semiconductor die, such as a metal pillar taught in Warren. The encapsulant surrounding lateral sides of the die connection terminals will improve the resilience of the die connection terminals, as well as the device, against deformation.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
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/ERIC MANUEL MULERO FLORES/ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898