DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/11/2026 has been entered.
Response to Amendment
Applicant’s arguments filed 5/11/2026 have been entered and considered. The amendments to claims 22, 33, and 34, the cancellation of claims 23 and 32, and the added claims 41 and 42 are acknowledged.
Response to Arguments
Applicant’s arguments with respect to claims 21, 31 and 38 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under pre-AIA 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims under pre-AIA 35 U.S.C. 103(a), the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were made absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and invention dates of each claim that was not commonly owned at the time a later invention was made in order for the examiner to consider the applicability of pre-AIA 35 U.S.C. 103(c) and potential pre-AIA 35 U.S.C. 102(e), (f) or (g) prior art under pre-AIA 35 U.S.C. 103(a).
Claims 21-22, 30, 38-39, and 41 are rejected under pre-AIA 35 U.S.C. 103 as being unpatentable over by Huemoeller US 6905914 B1 (hereinafter referred to as Huemoeller), in view of Deng et al. US 20130241057 A1 (hereinafter referred to as Deng).
Regarding claim 21, Huemoeller teaches
A semiconductor device (“assembly 1200” col line FIG. 13) comprising:
an interposer (though not called interposer by name, the structure comprising “vias 624, 824, 924, traces 832, and lands 1044 formed in dielectric strips 108, 708, 908, and 1008”, col 12 lines 43-44 FIG. 13, has the same features known in the art for an interposer) comprising:
a first interposer side (“Upper surface 108U of dielectric strip 108”, col 12 line 33, top side of “dielectric strip 108” of interposer);
a second interposer side (bottom side of “dielectric strip 1008”) opposite the first interposer side;
a first dielectric layer (“dielectric strip 108”) at the first interposer side;
a first conductive via (“via 624”) that extends through at least the first dielectric layer;
a second conductive via (“via 924”) at the second interposer side; and
a redistribution structure (“vias 824” and “traces 832”) in contact with the first dielectric layer and electrically connected to the first conductive via and the second conductive via (“vias 824” and “traces 832” at least partially contact surfaces of “dielectric strip 108” and electrically connect “visa 624” and “vias 924” as seen in FIG. 13);
a semiconductor die (“electronic component 106-1” col 12 line 21 FIG. 13) comprising:
a first die side that faces away from the first interposer side (top side of “electronic component 106-1”);
a second die side that faces toward the first interposer side (“front surfaces 106F of electronic components 106-1”, col 12 lines 34, bottom side of “electronic component 106-1”) and comprises a die connection terminal (“bond pad 112” col 12 line 50) that is coupled to the first conductive via; and
a lateral die side that extends between the first die side and the second die side (“electronic component 106-1” has a left and right lateral side);
an encapsulating material over at least the second die side (though not called encapsulant by name, “adhesive strip 120” performs the function of an encapsulating material since it encapsulates the “front surface 106F” and “Upper surface 108U” and surrounds portions “vias 624”), wherein:
at least one other side of the semiconductor die is exposed from the encapsulating material (lateral sides and top side of “electronic component 106-1” are exposed from “adhesive strip 120”);
the encapsulating material comprises an uppermost surface facing away from the interposer (“adhesive strip 120” has a surface in contact with “front surface 106F” facing away from “Upper surface 108U” of “dielectric strip 108”), a lowermost surface facing the interposer (“adhesive strip 120” has a surface in contact with “Upper surface 108U” facing away from “front surface 106F”), and a lateral surface that extends between the uppermost surface and the lowermost surface (“adhesive strip 120” has left and right lateral surfaces); and
the lateral surface of the encapsulating material is parallel to the lateral die side (left and right lateral surfaces of “adhesive strip 120” and “electronic component 106-1” appear substantially coplanar in FIG. 13 after singulation); and
a conductive bump (“interconnection balls 1150” col 12 lines 47-48) coupled to the second conductive via.
However, Huemoeller fails to teach the second conductive via that extends outward from the second interposer side such that a portion of the second conductive via is below the second interposer side, wherein the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump.
Nevertheless, Deng teaches
the second conductive via (“embedded trace 190” para. 0021 FIG. 10-11) that extends outward from the second interposer side such that a portion of the second conductive via is below the second interposer side (“embedded trace attachment structures 194” of “embedded trace 190” is integral with and extending from a first surface 196 of the embedded trace planar portion 192”, para. 0021. Flipping FIG. 10-11 180 degrees, “embedded trace attachment structures 194” is below the bottom side of “microelectronic substrate 188”, para. 0021)
wherein the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump (“embedded trace attachment structures 194 extend into their respective solder interconnects 212” para. 0023 FIG. 11).
Huemoeller and Deng teach stacked packages. The “microelectronic substrate 188” in Deng uses “embedded trace 190” for external connection. Deng suggests that such attachment structure is simpler to form and its height can be better controlled than when forming an attachment structure after the formation of the embedded trace (para. 0022 and 0026). Deng further teaches that the protruding “embedded trace attachment structures 194” produces a more reliable connection due to their higher surface area compared to traces without the attachment structure (para. 0025). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that having a “via 924” in Huemoeller can be formed to protrude like “embedded trace 190” so there is greater surface area in contact with “interconnection balls 1150”. Although greater surface area may be achieved by forming a protruding structure under “via 924”, it would require further processing steps an its height is not a simple to control than forming a longer “via 924”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device in Huemoeller with the extending via as taught in Deng. A via that extends below the second surface of the interposer can be formed without significant processing steps and can achieve a more reliable contact with the solder conductive bump.
Regarding claim 22, Huemoeller, modified by Deng, teach the semiconductor device of claim 21, comprising
an under bump metal layer between the second conductive via and the conductive bump (“surface finish 132”, which comprises a barrier layer, a ductile layer, and a solder wetting layer, para. 0016 FIG. 10),
wherein the under bump metal layer extends outward from the second interposer side (“surface finish 132” is formed on the outer surface of “embedded trace attachment structures 194”, para. 0016 and 0028); and
wherein a top side of the under bump metal layer is no higher than the second interposer side (“surface finish 132” is localized on “embedded trace attachment structures 194”, as seen in the formation steps in FIG. 4-8, para. 0016).
Regarding claim 30, Huemoeller, modified by Deng, teaches the semiconductor device of claim 21, wherein:
the interposer comprises a lateral interposer side that extends between the first interposer side and the second interposer side (the interposer in FIG. 13 has left and right lateral sides extending from “upper surface 108U” and the bottom side); and
the lateral interposer side is parallel to the lateral die side and to the lateral surface of the encapsulating material (lateral sides of “electronic component 106-1”, “adhesive strip 120”, and the interposer are at least substantially coplanar).
Regarding claim 41, Huemoeller, modified by Deng, teaches the semiconductor device of claim 21 comprising:
an under bump metal layer (“surface finish 132”, which comprises a barrier layer, a ductile layer, and a solder wetting layer, para. 0016 FIG. 10) comprising a portion that covers the portion of the second conductive via that is below the second interposer side (“surface finish 132” is localized on “embedded trace attachment structures 194”, as seen in the formation steps in FIG. 4-8, para. 0016); and
wherein the portion of the under bump metal layer covering the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump (“solder interconnects 212” is disposed over “surface finish 132” and “embedded trace attachment structures 194”, as shown in FIG. 11).
Regarding claim 38, Huemoeller teaches a method of manufacturing a semiconductor device (method of forming “assembly 1200” col 12 line 10 FIG. 13), the method comprising:
providing an interposer (though not called interposer by name, the structure comprising “vias 624, 824, 924, traces 832, and lands 1044 formed in dielectric strips 108, 708, 908, and 1008”, col 12 lines 43-44 FIG. 13, has the same features known in the art for an interposer) comprising:
a first interposer side (“Upper surface 108U of dielectric strip 108”, col 12 line 33, top side of “dielectric strip 108” of interposer);
a second interposer side (bottom side of “dielectric strip 1008”) opposite the first interposer side;
a first dielectric layer (“dielectric strip 108”) at the first interposer side;
a first conductive via (“via 624”) that extends through at least the first dielectric layer;
a second conductive via (“via 924”) at the second interposer side; and
a redistribution structure (“vias 824” and “traces 832”) in contact with the first dielectric layer and electrically connected to the first conductive via and the second conductive via (“vias 824” and “traces 832” at least partially contact surfaces of “dielectric strip 108” and electrically connect “visa 624” and “vias 924” as seen in FIG. 13);
providing a semiconductor die (“electronic component 106-1” col 12 line 21 FIG. 13) comprising:
a first die side that faces away from the first interposer side (top side of “electronic component 106-1”);
a second die side that faces toward the first interposer side (“front surfaces 106F of electronic components 106-1”, col 12 lines 34, bottom side of “electronic component 106-1”) and comprises a die connection terminal (“bond pad 112” col 12 line 50) that is coupled to the first conductive via; and
a lateral die side that extends between the first die side and the second die side (“electronic component 106-1” has a left and right lateral side);
providing an encapsulating material over at least the second die side (though not called encapsulant by name, “adhesive strip 120” performs the function of an encapsulating material since it encapsulates the “front surface 106F” and “Upper surface 108U” and surrounds portions “vias 624”), wherein:
at least one other side of the semiconductor die is exposed from the encapsulating material (lateral sides and top side of “electronic component 106-1” are exposed from “adhesive strip 120”);
the encapsulating material comprises an uppermost surface facing away from the interposer (“adhesive strip 120” has a surface in contact with “front surface 106F” facing away from “Upper surface 108U” of “dielectric strip 108”), a lowermost surface facing the interposer (“adhesive strip 120” has a surface in contact with “Upper surface 108U” facing away from “front surface 106F”), and a lateral surface that extends between the uppermost surface and the lowermost surface (“adhesive strip 120” has left and right lateral surfaces); and
the lateral surface of the encapsulating material is parallel to the lateral die side (left and right lateral surfaces of “adhesive strip 120” and “electronic component 106-1” appear substantially coplanar in FIG. 13 after singulation); and
providing a conductive bump (“interconnection balls 1150” col 12 lines 47-48) coupled to the second conductive via.
However, Huemoeller fails to teach the second conductive via that extends outward from the second interposer side such that a portion of the second conductive via is below the second interposer side, wherein the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump.
Nevertheless, Deng teaches
the second conductive via (“embedded trace 190” para. 0021 FIG. 10-11) that extends outward from the second interposer side such that a portion of the second conductive via is below the second interposer side (“embedded trace attachment structure 194” of “embedded trace 190” is integral with and extending from a first surface 196 of the embedded trace planar portion 192”, para. 0021. Flipping FIG. 10-11 180 degrees, “embedded trace attachment structure 194” is below the bottom side of “microelectronic substrate 188”, para. 0021)
wherein the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump (“embedded trace attachment structures 194 extend into their respective solder interconnects 212” para. 0023 FIG. 11).
Huemoeller and Deng teach stacked packages. The “microelectronic substrate 188” in Deng uses “embedded trace 190” for external connection. Deng suggests that such attachment structure is simpler to form and its height can be better controlled than when forming an attachment structure after the formation of the embedded trace (para. 0022 and 0026). Deng further teaches that the protruding “embedded trace attachment structure 194” produces a more reliable connection due to their higher surface area compared to traces without the attachment structure (para. 0025). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that having a “via 924” in Huemoeller can be formed to protrude like “embedded trace 190” so there is greater surface area in contact with “interconnection balls 1150”. Although greater surface area may be achieved by forming a protruding structure under “via 924”, it would require further processing steps an its height is not a simple to control than forming a longer “via 924”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method in Huemoeller with the extending via as taught in Deng. A via that extends below the second surface of the interposer can be formed without significant processing steps and can achieve a more reliable contact with the solder conductive bump.
Regarding claim 39, Huemoeller, modified by Deng, teaches the method of claim 38, providing an under bump metal layer between the second conductive via and the conductive bump (“surface finish 132”, which comprises a barrier layer, a ductile layer, and a solder wetting layer, para. 0016 FIG. 10-11), and wherein at least a first portion of the under bump metal layer extends outward from the second interposer side (“surface finish 132” is formed on the outer surface of “embedded trace attachment structures 194”, para. 0016 and 0028).
Claim 24-25 is rejected under pre-AIA 35 U.S.C. 103 as being unpatentable over Huemoeller, in view of Deng, in view of Lin et al. US 20140048951 A1 (hereinafter referred to as Lin’51).
Regarding claim 24, Huemoeller, modified by Deng, teaches the semiconductor device of claim 21 but fails to teach comprising an adhesive layer directly on the first die side, wherein at least a portion of the adhesive layer is vertically higher from the interposer than the encapsulating material.
Nevertheless, Lin’51 teaches
an adhesive layer (“thermally conductive adhesive 801” para. 0054 FIG. 2) directly on the first die side (top side of “semiconductor chip 51”, para. 0054), wherein at least a portion of the adhesive layer is vertically higher from the interposer (“interposer 31” para. 0050) than the encapsulating material (“Encapsulant 71” para. 0054).
Huemoeller, modified by Deng and Lin’51 teach devices comprising a chip on an interposer. The device in Lin’51 features a “heat dissipation plate 81” in thermal contact with “semiconductor chip 51” through the “thermally conductive adhesive 801” (para. 0054). In this manner, heat can be dissipated away from the device. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that a “thermally conductive adhesive 801” can conduct heat from “semiconductor chip 51” towards a “heat dissipation plate 81”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught between Huemoeller and Deng with the adhesive layer taught in Lin’51. An adhesive with good thermal conduction can be used in conjunction with a heat dissipation plate to provide a path of heat dissipation for the device.
Regarding claim 25, Huemoeller, modified by Deng and Lin’51, teaches the he semiconductor device of claim 24, wherein the adhesive layer is vertically higher from the interposer than the encapsulating material (“thermally conductive adhesive 801” is vertically higher than “encapsulant 71” as seen in FIG. 2 of Lin).
Claims 31-34 are rejected under pre-AIA 35 U.S.C. 103 as being unpatentable over by Huemoeller US 6905914 B1 (hereinafter referred to as Huemoeller), in view of Deng et al. US 20130241057 A1 (hereinafter referred to as Deng), in view of Lin et al. US 20140048951 A1 (hereinafter referred to as Lin’51).
Regarding claim 31, Huemoeller teaches
A semiconductor device (“assembly 1200” col line FIG. 13) comprising:
an interposer (though not called interposer by name, the structure comprising “vias 624, 824, 924, traces 832, and lands 1044 formed in dielectric strips 108, 708, 908, and 1008”, col 12 lines 43-44 FIG. 13, has the same features known in the art for an interposer) comprising:
a first interposer side (“Upper surface 108U of dielectric strip 108”, col 12 line 33, top side of “dielectric strip 108” of interposer);
a second interposer side (bottom side of “dielectric strip 1008”) opposite the first interposer side;
a first dielectric layer (“dielectric strip 108”) at the first interposer side;
a first conductive via (“via 624”) that extends through at least the first dielectric layer;
a second conductive via (“via 924”) at the second interposer side; and
a redistribution structure (“vias 824” and “traces 832”) in contact with the first dielectric layer and electrically connected to the first conductive via and the second conductive via (“vias 824” and “traces 832” at least partially contact surfaces of “dielectric strip 108” and electrically connect “visa 624” and “vias 924” as seen in FIG. 13);
a semiconductor die (“electronic component 106-1” col 12 line 21 FIG. 13) comprising:
a first die side that faces away from the first interposer side (top side of “electronic component 106-1”);
a second die side that faces toward the first interposer side (“front surfaces 106F of electronic components 106-1”, col 12 lines 34, bottom side of “electronic component 106-1”) and comprises a die connection terminal (“bond pad 112” col 12 line 50) that is coupled to the first conductive via;
an encapsulating material over at least the second die side (though not called encapsulant by name, “adhesive strip 120” performs the function of an encapsulating material since it encapsulates the “front surface 106F” and “Upper surface 108U” and surrounds portions “vias 624”), wherein:
at least one other side of the semiconductor die is exposed from the encapsulating material (lateral sides and top side of “electronic component 106-1” are exposed from “adhesive strip 120”); and
the encapsulating material comprises an uppermost surface facing away from the interposer (“adhesive strip 120” has a surface in contact with “front surface 106F” facing away from “Upper surface 108U” of “dielectric strip 108”), a lowermost surface facing the interposer (“adhesive strip 120” has a surface in contact with “Upper surface 108U” facing away from “front surface 106F”), and a lateral surface that extends between the uppermost surface and the lowermost surface (“adhesive strip 120” has left and right lateral surfaces); and
However, Huemoeller fails to teach the second conductive via comprising a second side portion that extends outward from the second interposer side such that a portion of the second conductive via is below the second interposer side, wherein the second side portion of the second conductive via is disposed within the conductive bump, an adhesive layer on the first die side.
Nevertheless, Deng teaches
the second conductive via (“embedded trace 190” para. 0021 FIG. 10-11) comprising a second side portion that extends outward from the second interposer side (“embedded trace attachment structure 194” of “embedded trace 190” is integral with and extending from a first surface 196 of the embedded trace planar portion 192”, para. 0021),
wherein the second side portion of the second conductive via is disposed within the conductive bump (“embedded trace attachment structures 194 extend into their respective solder interconnects 212” para. 0023 FIG. 11).
Huemoeller and Deng teach stacked packages. The “microelectronic substrate 188” in Deng uses “embedded trace 190” for external connection. Deng suggests that such attachment structure is simpler to form and its height can be better controlled than when forming an attachment structure after the formation of the embedded trace (para. 0022 and 0026). Deng further teaches that the protruding “embedded trace attachment structure 194” produces a more reliable connection due to their higher surface area compared to traces without the attachment structure (para. 0025). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that having a “via 924” in Huemoeller can be formed to protrude like “embedded trace 190” so there is greater surface area in contact with “interconnection balls 1150”. Although greater surface area may be achieved by forming a protruding structure under “via 924”, it would require further processing steps and its height is not a simple to control than forming a longer “via 924”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device in Huemoeller with the extending via as taught in Deng. A via that extends below the second surface of the interposer can be formed without significant processing steps and can achieve a more reliable contact with the solder conductive bump.
However, Huemoeller, modified by Deng, fails to teach an adhesive layer on the first die side.
Nevertheless, Lin’51 A1teaches
an adhesive layer (“thermally conductive adhesive 801” para. 0054 FIG. 2) on the first die side (top side of “semiconductor chip 51”, para. 0054).
Huemoeller, modified by Deng, and Lin’51 teach devices comprising a chip on an interposer. The device in Lin’51 features a “heat dissipation plate 81” in thermal contact with “semiconductor chip 51” through the “thermally conductive adhesive 801” (para. 0054). In this manner, heat can be dissipated away from the device. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that a “thermally conductive adhesive 801” can conduct heat from “semiconductor chip 51” towards a “heat dissipation plate 81”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught between Huemoeller and Deng with the adhesive layer taught in Lin’51. An adhesive with good thermal conduction can be used in conjunction with a heat dissipation plate to provide a path of heat dissipation for the device.
Regarding claim 32, Huemoeller, modified by Deng and Lin’51, teaches the semiconductor device of claim 31, comprising a conductive bump (“interconnection balls 1150” col 12 lines 47-48) coupled to the second conductive via.
Regarding claim 33, Huemoeller, modified by Deng and Lin’51, teaches the semiconductor device of claim 32, comprising an underbump metal layer between the second conductive via and the conductive bump (“surface finish 132”, which comprises a barrier layer, a ductile layer, and a solder wetting layer, para. 0016 FIG. 10-11); and wherein a first side of the under bump metal layer is coplanar with the second interposer side (a side of “surface finish 132” in contact with and thereby coplanar with “planar portion 192”, para. 0021 FIG. 10-11); and
wherein a second side the underbump metal layer extends outward from the second interposer side (a portion of “surface finish 132” is formed on “farthest point 198” of the “embedded trace attachment structure 194”, para. 0016 and 0026, seen in FIG. 10).
Regarding claim 34, Huemoeller, modified by Deng and Lin’51, teach the semiconductor device of claim 33, wherein the under bump metal layer comprises a lateral side between the first side and the second side of the under bump metal layer (a portion of “surface finish 132” is disposed on the lateral side of “embedded trace attachment structure 194”, connecting the portion in contact with “planar portion 192” and the portion on the farthest surface ; and
the conductive bump covers at least a portion of the lateral side of the under bump metal layer (“solder interconnects 212” in Deng are formed over “surface finish 132” and “embedded trace attachment structures 194”, such that the lateral side is covered as shown in FIG. 11).
Claims 21, 26-29, 38, and 40 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Warren et al. US 20120286408 A1 (hereinafter referred to as Warren) in view of Mizunashi US 20020139571 A1 (hereinafter referred to as Mizunashi), in view of Deng et al. US 20130241057 A1 (hereinafter referred to as Deng).
Regarding claim 21, Warren teaches
A semiconductor device (“WLP package with an interposer” para. 0049 FIG. 8B) comprising:
an interposer (“interposer 830” para. 0049) comprising:
a first interposer side (top side of “interposer 830” in FIG. 8B);
a second interposer side (bottom side of “interposer 830”) opposite the first interposer side;
a semiconductor die (“active die 812” para. 0049) comprising:
a first die side that faces away from the first interposer side (top of “active die 812” in FIG. 8B);
a first conductive via (“via 832” para. 0049);
a second die side (bottom of “active die 812”) that faces toward the first interposer side and comprises a die connection terminal (“metal pillars 822”) that is coupled to the first conductive via (“metal pillars 822” are coupled to “vias 832” through “bumps 824”, para. 0049); and
a lateral die side that extends between the first die side and the second die side (left and right lateral sides of “active die 812”);
an encapsulating material (“underfill 810”, which encapsulates the second die side and first side of interposer, para. 0049) over at least the second die side, wherein:
at least one other side of the semiconductor die is exposed from the encapsulating material (lateral sides of “active die 812” are exposed from “underfill 810);
the encapsulating material comprises an uppermost surface facing away from the interposer (“underfill 810” has a top side in contact with bottom of “active die 812” facing away from top side of “interposer 830”), a lowermost surface facing the interposer (“underfill 810” has a top side in contact with top side of “interposer 830” facing away from bottom of “active die 812”), and a lateral surface that extends between the uppermost surface and the lowermost surface (“underfill 810” has left and right lateral sides); and a lateral surface of the encapsulating material is parallel to the lateral die side (lateral sides of “underfill 810” are shown as coplanar in FIG. 8B after the dicing operation of the package shown in FIG. 8A); and
a conductive bump (“plating metal 836”, which may be solder material, para. 0049, 0071) coupled to the second conductive via.
However, Warren fails to teach a first dielectric layer at the first interposer side; a first conductive via that extends through at least the first dielectric layer; a second conductive via at the second interposer side; and a redistribution structure in contact with the first dielectric layer and electrically connected to the first conductive via and the second conductive via, teach the second conductive via that extends outward from the second interposer side such that a portion of the second conductive via is below the second interposer side, wherein the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump.
Nevertheless, Mizunashi teaches
a first dielectric layer (“insulating layer 21” para. 0043 FIG. 3) at the first interposer side (top side of “packaging substrate 1”, para. 0041);
a first conductive via (conductor in “via hole 23”, para. 0043) that extends through at least the first dielectric layer (“via hole 23” extends through “insulating layer 21”);
a second conductive via (conductor “via hole 33”) at the second interposer side (bottom side of “packaging substrate 1”); and
a redistribution structure (the structure comprising “core wiring layers 12 and 13”, which includes ground planes, signal line patterns, and power supply patterns, para. 0043-0044) in contact with the first dielectric layer (“core wiring layer 12” contacts “insulating layer 21”) and electrically connected to the first conductive via and the second conductive via (conductor in “via holes 23” is coupled to core wiring layer 12” and conductor in “via holes 33” are coupled to “core wiring layer 13”, para. 0046-0047).
Warren and Mizunashi teach devices comprising chips on interposer structures. The “interposer 830” only shows vias that have a similar pitch to the “metal pillars 822”. The “packaging substrate 1” in Mizunashi shows “flip chip terminals 5” of “device chip 3” having a certain pitch being redistributed by “core wiring layers 12 and 13” of “packaging substrate 1” to “solder balls 6” having a greater pitch. Mizunashi teaches in para. 0023 that device chips of different sizes can be bonded on “packaging substrate 1”. The device package can then be bonded onto another package or device with “solder balls 6”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the “package substrate 1” can redistribute signals from a “device chip 3” having “chip terminals 5” at a small pitch to another device having the pitch of the “solder balls 6”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught in Warren with the interposer as taught in Mizunashi. The multilayer interposer can accommodate chips of different sizes. Furthermore, having a redistribution layer and vias on each side of the interposer can route signals between chips having different external terminal pitches.
However, Warren, modified by Mizunashi, fails to teach the second conductive via that extends outward from the second interposer side such that a portion of the second conductive via is below the second interposer side, wherein the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump.
Nevertheless, Deng teaches
the second conductive via (“embedded trace 190” para. 0021 FIG. 10-11) that extends outward from the second interposer side such that a portion of the second conductive via is below the second interposer side (“embedded trace attachment structure 194” of “embedded trace 190” is integral with and extending from a first surface 196 of the embedded trace planar portion 192”, para. 0021. Flipping FIG. 10-11 180 degrees, “embedded trace attachment structure 194” is below the bottom side of “microelectronic substrate 188”, para. 0021)
wherein the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump (“embedded trace attachment structures 194 extend into their respective solder interconnects 212” para. 0023 FIG. 11).
Warren, modified by Mizunashi, and Deng teach stacked packages. The “microelectronic substrate 188” in Deng uses “embedded trace 190” for external connection. Deng suggests that such attachment structure is simpler to form and its height can be better controlled than when forming an attachment structure after the formation of the embedded trace (para. 0022 and 0026). Deng further teaches that the protruding “embedded trace attachment structure 194” produces a more reliable connection due to their higher surface area compared to traces without the attachment structure (para. 0025). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that having a “via 924” in Huemoeller can be formed to protrude like “embedded trace 190” so there is greater surface area in contact with “interconnection balls 1150”. Although greater surface area may be achieved by forming a protruding structure under “via 924”, it would require further processing steps an its height is not a simple to control than forming a longer “via 924”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught between Warren and Mizunashi with the extending via as taught in Deng. A via that extends below the second surface of the interposer can be formed without significant processing steps and can achieve a more reliable contact with the solder conductive bump.
Regarding claim 26, Warren, modified by Mizunashi and Deng, teaches the semiconductor device of claim 21, comprising solder (“bumps 824” which comprise solder, para. 0049, 0057) between the die connection terminal (“metal pillars 822”) and the first conductive via (“via 832”).
Regarding claim 27, Warren, modified by Mizunashi and Deng, teaches the semiconductor device of claim 21, wherein the die connection terminal comprises a conductive pillar (“metal pillar 822”) comprising:
a first pillar end toward the semiconductor die (upper end of “metal pillar 822” at “active die 812” side);
a second pillar end toward the interposer (lower end of “metal pillar 822” in contact with “bump 824”); and
a lateral pillar side that extends between the first pillar end and the second pillar end (“metal pillars 822” have lateral sides in contact with “underfill 810”).
Regarding claim 28, Warren, modified by Mizunashi and Deng, teaches the semiconductor device of claim 27, wherein the lateral pillar side is covered by the encapsulating material (“metal pillars 822” have lateral sides in contact with “underfill 810”).
Regarding claim 29, Warren, modified by Mizunashi and Deng, teaches the semiconductor device of claim 27, wherein the lateral surface of the encapsulating material is vertically longer than the conductive pillar (lateral surface of “underfill 810” extends from bottom of “active die 812” to top side of “interposer 830” while lateral side of “metal pillar 822” extends from bottom side of “active die 812” to the top of “bump 824”, as seen in FIG. 8B).
Regarding claim 38, Warren teaches
A method of manufacturing a semiconductor device (method of manufacturing “WLP package with an interposer” para. 0049 FIG. 8B), the method comprising:
Providing an interposer (“interposer 830” para. 0049) comprising:
a first interposer side (top side of “interposer 830” in FIG. 8B);
a second interposer side (bottom side of “interposer 830”) opposite the first interposer side;
providing a semiconductor die (“active die 812” para. 0049) comprising:
a first die side that faces away from the first interposer side (top of “active die 812” in FIG. 8B);
a first conductive via (“via 832” para. 0049);
a second die side (bottom of “active die 812”) that faces toward the first interposer side and comprises a die connection terminal (“metal pillars 822”) that is coupled to the first conductive via (“metal pillars 822” are coupled to “vias 832” through “bumps 824”, para. 0049); and
a lateral die side that extends between the first die side and the second die side (left and right lateral sides of “active die 812”);
providing an encapsulating material (“underfill 810”, which encapsulates the second die side and first side of interposer, para. 0049) over at least the second die side, wherein:
at least one other side of the semiconductor die is exposed from the encapsulating material (lateral sides of “active die 812” are exposed from “underfill 810);
the encapsulating material comprises an uppermost surface facing away from the interposer (“underfill 810” has a top side in contact with bottom of “active die 812” facing away from top side of “interposer 830”), a lowermost surface facing the interposer (“underfill 810” has a top side in contact with top side of “interposer 830” facing away from bottom of “active die 812”), and a lateral surface that extends between the uppermost surface and the lowermost surface (“underfill 810” has left and right lateral sides); and a lateral surface of the encapsulating material is parallel to the lateral die side (lateral sides of “underfill 810” are shown as coplanar in FIG. 8B after the dicing operation of the package shown in FIG. 8A); and
providing a conductive bump (“plating metal 836”, which may be solder material, para. 0049, 0071) coupled to the second conductive via.
However, Warren fails to teach a first dielectric layer at the first interposer side; a first conductive via that extends through at least the first dielectric layer; a second conductive via at the second interposer side; and a redistribution structure in contact with the first dielectric layer and electrically connected to the first conductive via and the second conductive via, the second conductive via that extends outward from the second interposer side such that a portion of the second conductive via is below the second interposer side, wherein the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump.
Nevertheless, Mizunashi teaches
a first dielectric layer (“insulating layer 21” para. 0043 FIG. 3) at the first interposer side (top side of “packaging substrate 1”, para. 0041);
a first conductive via (conductor in “via hole 23”, para. 0043) that extends through at least the first dielectric layer (“via hole 23” extends through “insulating layer 21”);
a second conductive via (conductor “via hole 33”) at the second interposer side (bottom side of “packaging substrate 1”); and
a redistribution structure (the structure comprising “core wiring layers 12 and 13”, which includes ground planes, signal line patterns, and power supply patterns, para. 0043-0044) in contact with the first dielectric layer (“core wiring layer 12” contacts “insulating layer 21”) and electrically connected to the first conductive via and the second conductive via (conductor in “via holes 23” is coupled to core wiring layer 12” and conductor in “via holes 33” are coupled to “core wiring layer 13”, para. 0046-0047).
Warren and Mizunashi teach devices comprising chips on interposer structures. The “interposer 830” only shows vias that have a similar pitch to the “metal pillars 822”. The “packaging substrate 1” in Mizunashi shows “chip terminals 5” of “device chip 3” having a certain pitch being redistributed by “core wiring layers 12 and 13” of “packaging substrate 1” to “solder balls 6” having a greater pitch. Mizunashi teaches in para. 0023 that device chips of different sizes can be bonded on “packaging substrate 1”. The device package can then be bonded onto another package or device with “solder balls 6”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the “package substrate 1” can redistribute signals from a “device chip 3” having “chip terminals 5” at a small pitch to another device having the pitch of the “solder balls 6”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing a semiconductor device taught in Warren with the interposer as taught in Mizunashi. The multilayer interposer can accommodate chips of different sizes. Furthermore, having a redistribution layer and vias on each side of the interposer can route signals between chips having different external terminal pitches.
However, Warren, modified by Mizunashi, fails to teach the second conductive via that extends outward from the second interposer side such that a portion of the second conductive via is below the second interposer side, wherein the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump.
Nevertheless, Deng teaches
the second conductive via (“embedded trace 190” para. 0021 FIG. 10-11) that extends outward from the second interposer side such that a portion of the second conductive via is below the second interposer side (“embedded trace attachment structure 194” of “embedded trace 190” is integral with and extending from a first surface 196 of the embedded trace planar portion 192”, para. 0021. Flipping FIG. 10-11 180 degrees, “embedded trace attachment structure 194” is below the bottom side of “microelectronic substrate 188”, para. 0021)
wherein the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump (“embedded trace attachment structures 194 extend into their respective solder interconnects 212” para. 0023 FIG. 11).
Warren, modified by Mizunashi, and Deng teach stacked packages. The “microelectronic substrate 188” in Deng uses “embedded trace 190” for external connection. Deng suggests that such attachment structure is simpler to form and its height can be better controlled than when forming an attachment structure after the formation of the embedded trace (para. 0022 and 0026). Deng further teaches that the protruding “embedded trace attachment structure 194” produces a more reliable connection due to their higher surface area compared to traces without the attachment structure (para. 0025). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that having a “via 924” in Huemoeller can be formed to protrude like “embedded trace 190” so there is greater surface area in contact with “interconnection balls 1150”. Although greater surface area may be achieved by forming a protruding structure under “via 924”, it would require further processing steps an its height is not a simple to control than forming a longer “via 924”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device between Warren and Mizunashi with the extending via as taught in Deng. A via that extends below the second surface of the interposer can be formed without significant processing steps and can achieve a more reliable contact with the solder conductive bump.
Regarding claim 40, Warren, modified by Mizunashi and Deng, teaches the method of claim 38, wherein providing the encapsulating material over at least the second die side comprises covering a lateral side of the die connection terminal with the encapsulating material (“metal pillars 822” have lateral sides in contact with “underfill 810”).
Claims 31, 35-37, and 42 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Warren, in view of Mizunashi, in view of Deng, and in view of Lin’51.
Regarding claim 31, Warren teaches
A semiconductor device (“WLP package with an interposer” para. 0049 FIG. 8B) comprising:
an interposer (“interposer 830” para. 0049) comprising:
a first interposer side (top side of “interposer 830” in FIG. 8B);
a second interposer side (bottom side of “interposer 830”) opposite the first interposer side;
a semiconductor die (“active die 812” para. 0049) comprising:
a first die side that faces away from the first interposer side (top of “active die 812” in FIG. 8B);
a first conductive via (“via 832” para. 0049);
a second die side (bottom of “active die 812”) that faces toward the first interposer side and comprises a die connection terminal (“metal pillars 822”) that is coupled to the first conductive via (“metal pillars 822” are coupled to “vias 832” through “bumps 824”, para. 0049); and
an encapsulating material (“underfill 810”, which encapsulates the second die side and first side of interposer, para. 0049) over at least the second die side, wherein:
at least one other side of the semiconductor die is exposed from the encapsulating material (lateral sides of “active die 812” are exposed from “underfill 810);
the encapsulating material comprises an uppermost surface facing away from the interposer (“underfill 810” has a top side in contact with bottom of “active die 812” facing away from top side of “interposer 830”), a lowermost surface facing the interposer (“underfill 810” has a top side in contact with top side of “interposer 830” facing away from bottom of “active die 812”), and a lateral surface that extends between the uppermost surface and the lowermost surface (“underfill 810” has left and right lateral sides); and a lateral surface of the encapsulating material is parallel to the lateral die side (lateral sides of “underfill 810” are shown as coplanar in FIG. 8B after the dicing operation of the package shown in FIG. 8A); and
a conductive bump (“plating metal 836”, which may be solder material, para. 0049, 0071) coupled to the second conductive via.
However, Warren fails to teach a first dielectric layer at the first interposer side; a first conductive via that extends through at least the first dielectric layer; a second conductive via comprising a second side portion that extends outward from the second interposer side; and a redistribution structure in contact with the first dielectric layer and electrically connected to the first conductive via and the second conductive via, an adhesive layer on the first die side, the second conductive via comprising a second side portion that extends outward from the second interposer side such that a portion of the second conductive via is below the second interposer side, wherein the second side portion of the second conductive via is disposed within the conductive bump.
Nevertheless, Mizunashi teaches
a first dielectric layer (“insulating layer 21” para. 0043 FIG. 3) at the first interposer side (top side of “packaging substrate 1”, para. 0041);
a first conductive via (conductor in “via hole 23”, para. 0043) that extends through at least the first dielectric layer (“via hole 23” extends through “insulating layer 21”);
a second conductive via (conductor “via hole 33”) at the second interposer side (bottom side of “packaging substrate 1”); and
a redistribution structure (the structure comprising “core wiring layers 12 and 13”, which includes ground planes, signal line patterns, and power supply patterns, para. 0043-0044) in contact with the first dielectric layer (“core wiring layer 12” contacts “insulating layer 21”) and electrically connected to the first conductive via and the second conductive via (conductor in “via holes 23” is coupled to core wiring layer 12” and conductor in “via holes 33” are coupled to “core wiring layer 13”, para. 0046-0047).
Warren and Mizunashi teach devices comprising chips on interposer structures. The “interposer 830” only shows vias that have a similar pitch to the “metal pillars 822”. The “packaging substrate 1” in Mizunashi shows “chip terminals 5” of “device chip 3” having a certain pitch being redistributed by “core wiring layers 12 and 13” of “packaging substrate 1” to “solder balls 6” having a greater pitch. Mizunashi teaches in para. 0023 that device chips of different sizes can be bonded on “packaging substrate 1”. The device package can then be bonded onto another package or device with “solder balls 6”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the “package substrate 1” can redistribute signals from a “device chip 3” having “chip terminals 5” at a small pitch to another device having the pitch of the “solder balls 6”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught in Warren with the interposer as taught in Mizunashi. The multilayer interposer can accommodate chips of different sizes. Furthermore, having a redistribution layer and vias on each side of the interposer can route signals between chips having different external terminal pitches.
However, Warren, modified by Mizunashi, fails to teach comprising an adhesive layer on the first die side, the second conductive via comprises a second side portion that extends outward from the second interposer side, wherein the portion of the second conductive via that is below the second interposer side is disposed within the conductive bump.
Nevertheless, Lin’51 teaches
an adhesive layer (“thermally conductive adhesive 801” para. 0054 FIG. 2) directly on the first die side (top side of “semiconductor chip 51”, para. 0054), wherein at least a portion of the adhesive layer is vertically higher from the interposer (“interposer 31” para. 0050) than the encapsulating material (“Encapsulant 71” para. 0054).
Warren, modified by Mizunashi, and Lin’51 teach devices comprising a chip on an interposer. The device in Lin’51 features a “heat dissipation plate 81” in thermal contact with “semiconductor chip 51” through the “thermally conductive adhesive 801” (para. 0054). In this manner, heat can be dissipated away from the device. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that a “thermally conductive adhesive 801” can conduct heat from “semiconductor chip 51” towards a “heat dissipation plate 81”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught between Warren and Mizunashi with the adhesive layer taught in Lin’51. An adhesive with good thermal conduction can be used in conjunction with a heat dissipation plate to provide a path of heat dissipation for the device.
However, Warren, modified by Mizunashi and Lin’51, fails to teach the second conductive via comprises a second side portion that extends outward from the second interposer side, wherein the second side portion of the second conductive via is disposed within the conductive bump.
Nevertheless, Deng teaches
the second conductive via (“embedded trace 190” para. 0021 FIG. 10-11) comprises a second side portion that extends outward from the second interposer side (“embedded trace attachment structure 194” of “embedded trace 190” is integral with and extending from a first surface 196 of the embedded trace planar portion 192”, para. 0021),
wherein the portion of the second conductive via is disposed within the conductive bump (“embedded trace attachment structures 194 extend into their respective solder interconnects 212” para. 0023 FIG. 11).
Warren, modified by Mizunashi and Lin’51, and Deng teach stacked packages. The “microelectronic substrate 188” in Deng uses “embedded trace 190” for external connection. Deng suggests that such attachment structure is simpler to form and its height can be better controlled than when forming an attachment structure after the formation of the embedded trace (para. 0022 and 0026). Deng further teaches that the protruding “embedded trace attachment structure 194” produces a more reliable connection due to their higher surface area compared to traces without the attachment structure (para. 0025). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that having a “via 924” in Huemoeller can be formed to protrude like “embedded trace 190” so there is greater surface area in contact with “interconnection balls 1150”. Although greater surface area may be achieved by forming a protruding structure under “via 924”, it would require further processing steps and its height is not a simple to control than forming a longer “via 924”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device between Warren, Mizunashi, and Lin’51 with the extending via as taught in Deng. A via that extends below the second surface of the interposer can be formed without significant processing steps and can achieve a more reliable contact with the solder conductive bump.
Regarding claim 35, Warren, modified by Minuzashi, Lin’51, and Deng, teaches the semiconductor device of claim 31, wherein the die connection terminal comprises a conductive pillar (“metal pillar 822”) comprising:
a first pillar end toward the semiconductor die (upper end of “metal pillar 822” at “active die 812” side);
a second pillar end toward the interposer (lower end of “metal pillar 822” in contact with “bump 824”); and
a lateral pillar side that extends between the first pillar end and the second pillar end (“metal pillars 822” have lateral sides in contact with “underfill 810”).
Regarding claim 36, Warren, modified by Minuzashi, Lin’51, and Deng, teaches the semiconductor device of claim 35, wherein the lateral pillar side is covered by the encapsulating material (“metal pillars 822” have lateral sides in contact with “underfill 810”).
Regarding claim 37, Warren, modified by Minuzashi, Lin’51, and Deng, teaches the semiconductor device of claim 36, wherein the lateral surface of the encapsulating material is vertically longer than the conductive pillar (lateral surface of “underfill 810” extends from bottom of “active die 812” to top side of “interposer 830” while lateral side of “metal pillar 822” extends from bottom side of “active die 812” to the top of “bump 824”, as seen in FIG. 8B).
Regarding claim 42, Warren, modified by Minuzashi, Lin’51, and Deng semiconductor device of claim 31, comprising:
an under bump metal layer comprising a portion that covers the second side portion of the second conductive via (“surface finish 132”, which comprises a barrier layer, a ductile layer, and a solder wetting layer, para. 0016, and covers “embedded trace attachment structure 194”, FIG. 10); and
wherein the portion of the under bump metal layer covering the second side portion of the second conductive via is disposed within the conductive bump (“embedded trace attachment structures 194 extend into their respective solder interconnects 212” para. 0023, and “surface finish 132” is on “embedded trace attachment structures 194”, such that they are within the “solder interconnects 212” as seen in FIG. 11).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC MULERO FLORES whose telephone number is (571)270-0070. The examiner can normally be reached Mon-Fri 8am-5pm (typically).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC MANUEL MULERO FLORES/ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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