DETAILED ACTION
This Office action responds to the Amendment file on October 15, 2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The Amendment filed on October 15, 2025, responding to the Office action mailed on July 16, 2025, has been entered. The present Office action is made with all the suggested amendments being fully considered. Applicant cancelled claims 4 and 5. Accordingly, pending in the application are claims 1-3 and 6-19.
Response to Amendment
Applicant’s amendments to the claims have overcome the objections to drawings, as previously set forth in the Non-Final Office action mailed on July 16, 2025. Accordingly, all previous drawings objections are hereby withdrawn.
Response to Amendment
Applicant’s arguments with respect to the claims filed on October 15, 2025 have been considered. Applicant argues the “the conductive structure is independently formed and subsequently positioned within the through hole”. The claim language “a plurality of conductive structures respectively oriented at the through holes” is broad and vague regarding when “a plurality of conductive structures” are manufactured prior to position them into the through holes. Even if “a plurality of conductive structures” are manufactured prior to position them into the through hole, the limitation “a plurality of conductive structures respectively oriented at the through holes” is merely a product-by-process limitation. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 227 USPQ 964, 966.
Applicant argues “the reference merely observes … and provide no structural solution to decoupled the conductive path from the hole wall”. However, the specification teaches “a part of the small-diameter segment directly contacts the hole wall” in paragraph [0014]; “at least a part of the small-diameter segment 122 of each conductive structure 12 directly contacts the hole wall W’ in paragraph [0057].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 7, 9-16, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Zhong et al. (Zhong hereinafter) (US 7,910,836) in view of Czaplewski et al. (Czaplewski hereinafter) (US 2017/0330316).
Regarding Claims 1, 3, 7, 9-16, 18, and 19:
Zhong (see, col.3/ll.65-66, col.10/ll.61-63, col.16/ll.39-44 and 60-63, col.65/ll.29 – col.66/ll.44 and Figs. 32-36) teaches multilayered printed circuit board comprising of patterned 18 µm-thick copper foils 4a formed on 1.0 mm-thick glass epoxy resin substrate 1, 1.0 mm-diameter through holes 18 formed by laser, electroless copper plating films 12a with a thickness of 0.6 to 3.0 µm, resin filler 10, and 20 µm-thick electrolytic copper plating films 13 overlaying the resin filer 10 and the electroless copper plating films 12a, the surfaces of the through holes 18 having surface roughness about 6 µm, the surfaces of the electroless plating films 12a being roughened, electronic parts, such as an IC chip being electrically connected with the multilayered printed circuit board, the laser drill forms 50-300 µm-diameter through holes and “after an IC chip is mounted on the multilayered printed circuit board”. However, Zhong does not explicitly teach the roughness of the electroless copper plating films 12a.
Czaplewski (see, ¶ [0005]-[0006], [0040], [0042]) teaches the roughness of the electrolytic copper plating is influenced by the roughness of the sidewall of the plated-through hole (PTH), the reliability of the PTH is strongly influenced by the sidewall roughness, rougher PTH walls can cause stress in the copper plating, and smoother PTH walls can be achieved by a negative etchback process and generally result in better performance.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Zhong to include the teaching of Czaplewski to form smother surface of the plated through hole for better performance of the circuit board.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Zhong et al. (Zhong hereinafter) (US 7,910,836) in view of Czaplewski et al. (Czaplewski hereinafter) (US 2017/0330316) as applied to claim 1, above, and further in view of Shimizu et al. (Shimizu hereinafter) (US 6,570,098).
Regarding Claim 2:
Zhong (see, col.65/ll.29 – col.66/ll.44 and Figs. 32-36) teaches multilayered printed circuit board, but does not explicitly teach resilient board.
Shimizu (see, col.9/ll.32 – col.10/ll.63, Table 1, and FIGs. 1 and 2) teaches “the flexible substrates 3 to 6 are stuck to the rigid substrate 2 by the adhesive 7”, “the adhesives 7… are each formed to a thickness of 12 to 25 µm”, and the flexible substrate formed of 30 µm-thick polyimides.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teaching of Zhong in the device of Czaplewski to further include the teaching of Shimizu to use the resilient/flexible board in addition to the rigid board to host the increased demand of I/O wiring pins and to join the rigid board and the resilient/flexible board with an adhesive layer with certain thicknesses to reduce the weight and size of the printed circuit/wiring boards.
Claims 6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Zhong et al. (Zhong hereinafter) (US 7,910,836) in view of Czaplewski et al. (Czaplewski hereinafter) (US 2017/0330316) as applied to claim 1, above, and further in view of Sarkhel et al. (Sarkhel hereinafter) (US 5,730,932).
Regarding Claims 6 and 8:
Zhong (see, col.65/ll.29 – col.66/ll.44 and Figs. 32-36) teaches multilayered printed circuit board, but does not explicitly teach one of the two larger-diameter caps and the small-diameter segment are formed to be a conductive pin as integrity.
Sarkhel (see, col.4/ll.52-67 and Fig. 3) teaches specific solder alloy composition is inserted into the plated through holes to form the integral form of top joints 40 and bottom joints 41 via the filled plated through holes.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teaching of Zhong in the device of Czaplewski to further include the teaching of Sarkhel to fill the plated through holes with specific solder alloy composition so that an I-shaped conductive structure can be formed at low temperature with automated, high-speed, and high through-put processes.
Claim 17 are rejected under 35 U.S.C. 103 as being unpatentable over Zhong et al. (Zhong hereinafter) (US 7,910,836) in view of Czaplewski et al. (Czaplewski hereinafter) (US 2017/0330316) as applied to claim 1, above, and further in view of Shigi et al. (Shigi hereinafter) (US 6,506,982).
Regarding Claim 17:
Zhong (see, col.65/ll.29 – col.66/ll.44 and Figs. 32-36) teaches multilayered printed circuit board, but does not explicitly teach an insulation sleeve sheathing the small-diameter segment and arranged between the small-diameter segment of the corresponding conductive structure and the hole wall of a corresponding one of the through holes.
Shigi (see, col.8/ll.40 – col.9/ll.29 and Figs. 7A-7B) teaches a multi-layer wiring substrate comprising a copper plating layer 27 (24a) formed on the sidewall of through holes/first windows 22, resin filled the plated through holes/first windows 22, the second windows 18 formed with a portion of an insulating resin 25a, and a copper/independent conducting paths 27 formed in the second windows 18.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teaching of Zhong in the device of Czaplewski to further include the teaching of Shigi to fill the through holes with insulating layer between the conductive plug and copper-plated through holes in order to control the impedance of signal in the through holes.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALICE W TANG whose telephone number is (571)272-7227. The examiner can normally be reached Monday-Friday: 8:30 am to 5 pm..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571)272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ALICE W TANG/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814