DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicants’ submission filed on March 10, 2026, has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 26, 2026, is being considered by the examiner.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed March 10, 2026, and the Supplemental amendment filed March 18, 2026. Claims 1, 5, 12, 15, and 20 are amended in the Amendment filed March 10, 2026, and claim 1 is further amended in the Supplemental Amendment filed March 18, 2026. The Examiner notes that claims 1-20 are examined.
Response to Arguments
Applicant’s arguments, see page 10, filed March 18, 2026, with respect to claim 1 and its dependents have been fully considered and are persuasive. The rejections under 35 U.S.C. § 103 of claims 1-11 have been withdrawn.
Applicant's arguments filed March 10, 2026 have been fully considered but they are not persuasive. Applicant argues that the differences in thicknesses are critical in part because the thicknesses are based on levels of adjacent structures for the purposes of preventing crystal defects, which is not contemplated by prior art. In response to applicant's argument that the prevention of crystal defects in relation to gate insulator thickness was not contemplated by prior art, the fact that the inventor has recognized another advantage which would flow naturally from following the suggestion of the prior art cannot be the basis for patentability when the differences would otherwise be obvious. See Ex parte Obiaya, 227 USPQ 58, 60 (Bd. Pat. App. & Inter. 1985). The prior art teaches that different thicknesses of gate insulators are results effective at tuning the operating voltages of transistors and the ordinary artisan would be motivated to arrive at the voltage relationship claimed for the purpose of tuning operating voltages.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12, 14-15, 17-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2021/0091105 A1) in view of Pal (US 7,932,143 A1) and Yamamoto (US 2006/0001108 A1).
With respect to claim 12, Kim teaches:
A semiconductor device, comprising:
a first element separation layer (isolation film 54, see annotated Fig. 5B) arranged on a substrate (52) and defining a first active region (active region AC, see annotated Fig. 5B);
a second element separation (isolation film 54, see annotated Fig. 5B) layer arranged on the substrate (52),
defining a second active region and a third active region (see annotated Fig. 5B),
a first transistor (transistor that includes first active region, gate PG and source/drain PSD) arranged on the substrate (52) (see annotated Fig. 5B above) and having a first threshold voltage,
the first transistor comprising:
the first active region (annotated Fig. 5B);
a second transistor arranged on the substrate and having a second threshold voltage (second active region in annotated Fig. 5B, gate and source/drain associated with it),
the second transistor comprising:
the second active region (annotated Fig. 5B);
and a second gate structure arranged on the second active region (PG above active region);
and a third transistor arranged on the substrate and having a third threshold voltage (third active region in annotated Fig. 5B, gate and source/drain associated with it),
the third transistor comprising:
the third active region (annotated Fig. 5B);
and a third gate structure arranged on the third active region (PG above third active region).
The Examiner takes the position that although Kim does not specifically mention that the transistors of the peripheral circuit have threshold voltages, a threshold voltage is an inherent property of a planar transistor. In the event that a threshold voltage is not inherent, which the Examiner does not concede, transistors with threshold voltages are conventional in the art and it would be obvious to an ordinary artisan to make transistors that have threshold voltages for the purpose of tuning the on/off properties to the needs of the device.
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Kim fails to teach:
and comprising an upper surface at a higher level than an upper surface of the first element separation layer;
a channel semiconductor layer arranged on the first active region and at a higher level than the upper surface of the first element separation layer;
the channel semiconductor layer comprising a tail portion extending downwardly over an edge of the first active region to contact the first element separation layer;
and a first gate structure arranged on the channel semiconductor layer;
the first gate structure comprising a first gate insulating layer arranged on the channel semiconductor layer and having a first thickness in the first direction;
the second gate structure comprising a second gate insulating layer arranged on the second active region and having a second thickness greater than the first thickness in the first direction;
the third gate structure comprising a third gate insulating layer arranged on the third active region and having a third thickness greater than the second thickness in the first direction.
Pal teaches:
a channel semiconductor layer (col. 5, lns. 27-28, epitaxial layer 53 comprises a channel silicon germanium) arranged on the first active region (col. 2 ln 66- col. 3 ln. 2 “An epitaxial layer is formed on the active region of the semiconductor substrate to define a lateral overhang portion in the divot at an interface of the active region and the shallow trench isolation region”) and at a higher level than an upper surface of the first element separation layer (STI region 60);
the channel semiconductor layer (53) comprising a tail portion (overhang portion 55) extending downwardly over an edge of the first active region (active portion of 58) to cover a portion of a sidewall of the first active region
a first gate structure (gate insulator 64, gate forming material 66, and second gate stack forming layer 70) arranged on the channel semiconductor layer (53);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Pal into the device of Kim to make the first transistor into a SiGe channel with an overhang that is covered on the side by a gate dielectric. The ordinary artisan would have been motivated to modify Kim in the manner set forth above for the purpose of protecting gate stacks from voids created in gate stack formation due to divots formed during planarization (col. 2 lns. 41-56).
Yamamoto teaches in Fig. 5E:
[a second element separation layer] (insulation film 2 in the high voltage region) comprising an upper surface (upper surface of 2 in the high voltage region) at a higher level than the upper surface of the first element separation layer (upper surface of 2 in the low voltage region, which is etched 15 nm lower than the surface of the active region;
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Yamamoto into the device of Kim/Pal to include a first isolation layer with a surface lower than the surface of the second isolation layer. The ordinary artisan would have been motivated to modify Kim/Pal in the manner set forth above for the purpose increasing the effective gate width and tuning the on-current (para. 27 of Yamamoto)
Kim/Pal/Yamamoto further teaches:
a first gate insulating layer (gate insulator material 64 of Pal) arranged on the channel semiconductor layer (53) and having a first thickness in a first direction substantially perpendicular to an upper surface of the substrate (Pal col. 6, lns. 23-26 of Pal, “Gate insulator material 64 preferably has a thickness of about 1-10 nm, although the actual thickness can be determined based on the application of the transistor in the circuit being implemented.”)
a second gate insulating layer (gate dielectric under gate PG, shown in Fig. 5B of Kim but not labeled) arranged on the second active region and having a second thickness;
a third gate insulating layer (gate dielectric shown under gate PG in Fig. 5B of Kim but not labeled) arranged on the third active region and having a third
Kim does not specify the thicknesses of the gate dielectric layers. Yamamoto teaches that different gate insulator thicknesses can be used depending on if a transistor is in a low voltage or high voltage region and teaches a thickness of 1.8 nm (para. 42) in a low voltage region and 5 nm in a high voltage region (para. 38). The range of the thickness of the first gate dielectic of 1 10 nm as taught be Pal includes a portion that is less than the thickness of 1.8 nm taught by the low voltage region of Yamamoto. It would be obvious to select a first thickness of 1 nm (lower bound taught by Pal), a second thickness of 1.8 nm (Yamamoto), and a third thickness of 5 nm (high voltage region of Yamamoto) such that:
wherein the second gate structure comprises:
a second gate insulating layer arranged on the second active region and having a second thickness greater (1.8 nm) than the first thickness in the first direction (1 nm)
a third gate insulating layer arranged on the third active region and having a third thickness (5 nm) greater than the second thickness (1.8 nm) in the first direction;
The ordinary artisan would be motivated to make the above modification for the purpose of tuning the transistors to meet the needs of the voltages in the areas of the peripheral circuit and/or because in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (MPEP 2144.05(I)).
With respect to claim 14, Pal further teaches:
wherein an edge portion of the first active region (top portion of 58 uncovered by divots) is not covered by the first element separation layer (60)
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Kim in view of Pal and Yamamoto as explained above.
With respect to claim 15, Kim/Pal/Yamamoto teaches:
wherein the first gate structure further comprises:
and a first gate electrode (Pal col. 7 lns. 17-20, second gate stack forming layer 70 which may comprise a conductive gate electrode forming material) arranged on the first gate insulating layer (64 of Pal),
wherein the second gate structure comprises:
and a second gate electrode (PG of Kim) arranged on the second gate insulating layer,
and wherein the third gate structure comprises:
and a third gate electrode (gate electrode PG of Kim) on the third gate insulating layer
With respect to claim 17, Pal further teaches:
and the first gate insulating layer (64) covers the tail portion (55) of the channel semiconductor layer on the edge portion of the first active region (58)
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Kim in view of Pal and Yamamoto as explained above.
With respect to claim 18, Pal further teaches:
wherein the first element separation layer (60) comprises a first side (inner side) contacting the first active region (58) and a second side (outer side) opposite to the first side, and an upper surface of the first element separation layer on the first side is arranged at a lower level than an upper surface of the first element separation layer on the second side (see Fig. 10).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Kim in view of Pal and Yamamoto as explained above.
With respect to claim 20, Kim teaches:
An electronic system (IC device 100), comprising:
a first substrate (upper substrate 110);
a semiconductor device (memory stack MS on top of first substrate and peripheral circuit on bottom of first substrate) on the first substrate (110);
and a controller electrically connected to the semiconductor device (para. 67 “Each of the plurality of through electrodes THV may be connected to at least one of the plurality of circuits CT through the multilayered interconnection structure MWS included in the peripheral circuit structure PCS, and may be connected between those circuits and a circuit or wiring line above the cell array structure CAS of the integrated circuit device 10 (e.g., to a controller)”),
wherein the semiconductor device comprises:
a periphery circuit structure (peripheral circuit structure PCS) arranged on a second substrate (lower substrate 52);
and a memory cell array (cell array structure CAS) arranged on the periphery circuit structure (PCS),
and comprising a plurality of memory cells (memory cell strings MS) arranged in a first direction (Z) substantially perpendicular to an upper surface of the second substrate (52, which has an upper surface in the X-Y plane),
wherein the periphery circuit structure (PCS) comprises:
a first element separation layer (isolation film 54, see annotated Fig. 5B) arranged on the second substrate (52) and defining a first active region (active region AC, see annotated Fig. 5B);
a second element separation (isolation film 54, see annotated Fig. 5B) layer arranged on the second substrate (52),
defining a second active region and a third active region (see annotated Fig. 5B),
a first transistor (transistor that includes first active region, gate PG and source/drain PSD) arranged on the second substrate (52) (see annotated Fig. 5B above) and having a first threshold voltage,
the first transistor comprising:
the first active region (annotated Fig. 5B);
a second transistor arranged on the second substrate and having a second threshold voltage (second active region in annotated Fig. 5B, gate and source/drain associated with it),
the second transistor comprising:
the second active region (annotated Fig. 5B);
and a second gate structure arranged on the second active region (PG above active region);
and a third transistor arranged on the second substrate and having a third threshold voltage (third active region in annotated Fig. 5B, gate and source/drain associated with it),
the third transistor comprising:
the third active region (annotated Fig. 5B);
and a third gate structure arranged on the third active region (PG above third active region).
The Examiner takes the position that although Kim does not specifically mention that the transistors of the peripheral circuit have threshold voltages, a threshold voltage is an inherent property of a planar transistor. In the event that a threshold voltage is not inherent, which the Examiner does not concede, transistors with threshold voltages are conventional in the art and it would be obvious to an ordinary artisan to make transistors that have threshold voltages for the purpose of tuning the on/off properties to the needs of the device.
Kim fails to teach:
and comprising an upper surface at a higher level than an upper surface of the first element separation layer;
a channel semiconductor layer arranged on the first active region and at a higher level than the upper surface of the first element separation layer, and comprising silicon germanium;
the channel semiconductor layer comprising a tail portion extending downwardly over an edge of the first active region to cover a portion of a sidewall of the first active region and contact the first element separation layer
and a first gate structure arranged on the channel semiconductor layer;
the first gate structure comprising a first gate insulating layer arranged on the channel semiconductor layer and having a first thickness in the first direction;
the second gate structure comprising a second gate insulating layer arranged on the second active region and having a second thickness greater than the first thickness in the first direction;
the third gate structure comprising a third gate insulating layer arranged on the third active region and having a third thickness greater than the second thickness in the first direction.
Pal teaches:
a channel semiconductor layer (col. 5, lns. 27-28, epitaxial layer 53 comprises a channel silicon germanium) arranged on the first active region (col. 2 ln 66- col. 3 ln. 2 “An epitaxial layer is formed on the active region of the semiconductor substrate to define a lateral overhang portion in the divot at an interface of the active region and the shallow trench isolation region”) and at a higher level than an upper surface of the first element separation layer (STI region 60), and comprising silicon germanium (col. 5, lns. 27-28).
the channel semiconductor layer (53) comprising a tail portion (overhang portion 55) extending downwardly over an edge of the first active region (active portion of 58) to cover a portion of a sidewall of the first active region
a first gate structure (gate insulator 64, gate forming material 66, and second gate stack forming layer 70) arranged on the channel semiconductor layer (53);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Pal into the device of Kim to make the first transistor into a SiGe channel with an overhang that is covered on the side by a gate dielectric. The ordinary artisan would have been motivated to modify Kim in the manner set forth above for the purpose of protecting gate stacks from voids created in gate stack formation due to divots formed during planarization (col. 2 lns. 41-56).
Yamamoto teaches in Fig. 5E:
[a second element separation layer] (insulation film 2 in the high voltage region) comprising an upper surface (upper surface of 2 in the high voltage region) at a higher level than the upper surface of the first element separation layer (upper surface of 2 in the low voltage region, which is etched 15 nm lower than the surface of the active region;
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Yamamoto into the device of Kim/Pal to include a first isolation layer with a surface lower than the surface of the second isolation layer. The ordinary artisan would have been motivated to modify Kim/Pal in the manner set forth above for the purpose increasing the effective gate width and tuning the on-current (para. 27 of Yamamoto)
Kim/Pal/Yamamoto further teaches:
a first gate insulating layer (gate insulator material 64 of Pal) arranged on the channel semiconductor layer (53) and having a first thickness in a first direction substantially perpendicular to an upper surface of the substrate (Pal col. 6, lns. 23-26 of Pal, “Gate insulator material 64 preferably has a thickness of about 1-10 nm, although the actual thickness can be determined based on the application of the transistor in the circuit being implemented.”)
a second gate insulating layer (gate dielectric under gate PG, shown in Fig. 5B of Kim but not labeled) arranged on the second active region and having a second thickness;
a third gate insulating layer (gate dielectric shown under gate PG in Fig. 5B of Kim but not labeled) arranged on the third active region and having a third
Kim does not specify the thicknesses of the gate dielectric layers. Yamamoto teaches that different gate insulator thicknesses can be used depending on if a transistor is in a low voltage or high voltage region and teaches a thickness of 1.8 nm (para. 42) in a low voltage region and 5 nm in a high voltage region (para. 38). The range of the thickness of the first gate dielectic of 1 10 nm as taught be Pal includes a portion that is less than the thickness of 1.8 nm taught by the low voltage region of Yamamoto. It would be obvious to select a first thickness of 1 nm (lower bound taught by Pal), a second thickness of 1.8 nm (Yamamoto), and a third thickness of 5 nm (high voltage region of Yamamoto) such that:
wherein the second gate structure comprises:
a second gate insulating layer arranged on the second active region and having a second thickness greater (1.8 nm) than the first thickness in the first direction (1 nm)
a third gate insulating layer arranged on the third active region and having a third thickness (5 nm) greater than the second thickness (1.8 nm) in the first direction;
The ordinary artisan would be motivated to make the above modification for the purpose of tuning the transistors to meet the needs of the voltages in the areas of the peripheral circuit and/or because in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (MPEP 2144.05(I)).
Claims 16 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2021/0091105 A1) in view of Pal (US 7,932,143 A1) and Yamamoto (US 2006/0001108 A1) as applied to claim 15 above and further in view of Yi (2020/0135274 A1).
With respect to claim 16, Pal further teaches:
wherein the upper surface of the first element separation layer (upper surface of 60) is at a lower level than an upper surface of the first gate insulating layer (64),
Kim/Pal/Yamamoto further fail to teach:
an upper surface of the second element separation layer is at a higher level than an upper surface of the second gate insulating layer,
and the upper surface of the second element separation layer is at a higher level than an upper surface of the third gate insulating layer.
Yi teaches in Fig 2H:
an upper surface of the second element separation layer (gate insulating layer 202) is at a higher level than an upper surface of the second gate insulating layer,
and the upper surface of the second element separation layer is at a higher level than an upper surface of the third gate insulating layer (see annotated Fig. 2H below).
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The element separation layer of Yi differs from the layer of Kim/Pal/Yamamoto in that the layer of Yi protrudes above the substrate and has an upper surface higher than the gate insulating layer. The insulating layer of Yi serves the same purpose as the separation layer of Kim/Pal/Yamamoto. It would be obvious to a person of ordinary skill in the art to substitute the isolation layers 202 of Yi in place of the second element separation layer of Kim with predictable results. The ordinary artisan would be motivated to do so to optimize the separation between the neighboring transistors.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2021/0091105 A1) in view of Pal (US 7,932,143 A1) and Yamamoto (US 2006/0001108 A1) as applied to claim 12 above and further in view of Ema (2009/0102010 A1).
With respect to claim 13, Kim/Pal/Yamamoto teaches all limitations of claim 12 upon which claim 13 depends. Pal further teaches:
wherein the first transistor comprises a p-channel metal-oxide- semiconductor (PMOS) transistor (col. 5, lns. 26-28 “For a PFET active region, in a preferred embodiment of the present invention, the epitaxial layer 53 comprises a channel Silicon Germanium (cSiGe) epitaxial layer”)
Kim/Pal/Yamamoto fails to teach:
the second transistor comprises a PMOS transistor or an n-channel metal oxide-semiconductor (NMOS) transistor,
and the third transistor comprises a PMOS transistor or an NMOS transistor
Ema teaches a memory and logic circuit for a in which devices operate at least three different threshold voltages. Ema teaches:
and the first transistor (gate electrode 118 of p-channel low voltage/low threshold voltage transistor (P-LV Low Vt), para. 87, see annotated Fig. 5H above for devices referenced) comprise a p-channel metal-oxide- semiconductor (PMOS) transistor,
the second transistor comprises a PMOS or an n-channel metal- oxide-semiconductor (NMOS) transistor (para. 88, p-channel middle voltage transistor (P-MV) transistor),
and the third transistor comprises a PMOS transistor or an NMOS transistor having a (para. 95, “the p-channel high voltage/high threshold voltage transistor (P-HV High Vt).)
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Ema into the device of Kim/Pal/Yamamoto to include PMOS transistors with three different threshold voltages. The ordinary artisan would have been motivated to modify Kim/Pal/Yamamoto in the manner set forth above for the purpose of tuning the consumption of power and meeting the needs of high integration and high speed in logic circuitry (para. 5 of Ema)
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2021/0091105 A1) in view of Pal (US 7,932,143 A1) and Yamamoto (US 2006/0001108 A1) as applied to claim 12 above and further in view of Kim-125 (US 2009/0085125 A1).
With respect to claim 19, Kim/Pal/Yamamoto fails to teach:
wherein the first element separation layer comprises a first liner layer arranged inside an element separation trench arranged inside the substrate, a second liner layer on the first liner layer,
and a filling insulation layer filling an inside of the element separation trench on the second liner layer.
Kim-125 teaches in Fig. 2A:
wherein the first element separation layer (isolation structure 110) comprises a first liner layer (oxide layer liner 111) arranged inside an element separation trench (isolation trench 100 a) arranged inside the substrate (substrate comprising N-well 101 and P-well 102), a second liner layer (nitride liner layer 112) on the first liner layer (111),
and a filling insulation layer (isolation layer 114) filling an inside of the element separation trench (100a) on the second liner layer (112).
The element separation layer of Kim-125 differs from the layer of Kim/Pal/Yamamoto in that the layer of Kim-125 includes a first and second lining layer. The insulating layer of Kim-125 serves the same purpose as the separation layer of Kim/Pal/Yamamoto of separating adjacent semiconductor devices. It would be obvious to a person of ordinary skill in the art to substitute the isolation structure of Kim-125 in place of the element separation structures of Kim/Pal/Yamamoto to include liner layers. The ordinary artisan would be motivated to do so to optimize the insulating properties of the element separation between adjacent transistors.
Allowable Subject Matter
Claims 1-11 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1, prior art of record does not fairly disclose or make obvious the claimed device as a whole. Specifically, the closest prior art (which has been made of record) fail to disclose (by themselves or in combination) the limitations of “a channel semiconductor layer arranged on the first active region and having an uppermost portion of an upper surface thereof at a higher level than an uppermost portion of an upper surface of the first element separation layer, the channel semiconductor layer comprising a tail portion extending downwardly over an edge of the first active region to cover a portion of a sidewall of the first active region” of claim 1 when considered in combination with the additionally claimed features, as are claimed by the Applicant. Thus, the Applicant’s claims are determined to be a novel and non-obvious way of forming a peripheral circuit structure for a memory cell array that accommodates transistors with different voltage and manufacturing process needs on the same peripheral circuit substrate.
Claims 2-11 are allowed at least for the same reason as independent claim 1 upon which they depend.
Upon completing an updated prior art search and considering the combination of limitations as presented as a whole for the claims, the features highlighted above are considered an improvement over the prior art and have not been found to be anticipated or rendered obvious by a combination of prior art.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON MICHAEL WEGNER whose telephone number is (571)270-7647. The examiner can normally be reached Mon-Fri 8:30 AM - 5 PM.
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/A.M.W./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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