Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 7 rejected under 35 U.S.C. 103 as being unpatentable over Song (U.S. Patent Pub. No. 2008/0164324) of record, in view of Zuo (U.S. Patent No. 11,206,392) of record, in view of Sasaki (U.S. Patent Pub. No. 2012/0140366) of record
Regarding Claim 1
FIG. 4 of Song discloses a semiconductor device, comprising: a first power metal ring for providing a power supply voltage [0005]; a first ground metal ring for providing a ground voltage (Claim 10); a first signal pad (63+70) configured to exchange an input/output signal with an input/output circuit [0027]; a dummy power pad (69) disposed adjacent to the first signal pad, wherein the dummy power pad includes a first ESD protection circuit (91) connected to at least one of the power metal lines (81) ,a dummy ground pad (68) disposed adjacent to the first signal pad, wherein the dummy power pad and the dummy ground pad are disposed in pairs and adjacent to each other.
Song is silent with respect to “the first signal pad includes a first diode circuit connected between the first power metal ring and the first ground metal ring”; the first ESD protection circuit includes “a first clamp circuit connected between the first power metal ring and the first ground metal ring”; “the first clamp circuit includes a transistor having a first end directly connected to the first power metal ring” and “a discharge path having the lowest resistance is constituted through the first diode circuit, the first power metal ring, the transistor of the first clamp circuit and the first ground metal ring when an electrostatic discharge (ESD) event occurs in the first signal pad”.
FIG. 3 of Zuo discloses a similar semiconductor device, comprising a dummy power pad (320), wherein the dummy power pad includes a first clamp circuit (336) connected between the first power metal ring (PIXVDD) and the first ground metal ring (AGND), and wherein the first clamp circuit includes a transistor having a first end directly connected to the first power metal ring.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Song, as taught by Zuo. The ordinary artisan would have been motivated to modify Song in the above manner for purpose of limiting voltage spikes to protect devices.
Song as modified by Zuo is silent with respect to “the first signal pad includes a first diode circuit connected between the first power metal ring and the first ground metal ring” and “a discharge path having the lowest resistance is constituted through the first diode circuit, the first power metal ring, the transistor of the first clamp circuit and the first ground metal ring when an electrostatic discharge (ESD) event occurs in the first signal pad”.
FIG. 3 of Sasaki discloses a similar semiconductor device, comprising: a first power metal ring (30) for providing a power supply voltage (VDD); a first ground metal ring (31) for providing a ground voltage (GND); a first signal pad (70) comprising power metal rings and configured to exchange an input/output signal with an input/output circuit; and a first clamp circuit (4, FIG. 6) connected between the first power metal ring (5) and the first ground metal ring (6), wherein the first signal pad includes a first diode circuit (1) connected between the first power metal ring and the first ground metal ring; the first clamp circuit (4) includes a transistor (10) having a first end directly connected to the first power metal ring (5), and wherein a discharge path having the lowest resistance is constituted through the first diode circuit, the first power metal ring, the transistor of the first clamp circuit and the first ground metal ring when an electrostatic discharge (ESD) event occurs in the first signal pad [0016]. Furthermore, the recitation “a discharge path having the lowest resistance is constituted through the first diode circuit, the first power metal ring, the transistor of the first clamp circuit and the first ground metal ring when an electrostatic discharge (ESD) event occurs in the first signal pad” is only a statement of the inherent properties of the device. When the structure recited in the prior art is substantially identical to that of the claimed invention, then the claimed properties or functions are presumed to be inherent. Or where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. See MPEP 2112.01.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Song, as taught by Sasaki. The ordinary artisan would have been motivated to modify Song in the above manner for purpose of ensuring ESD robustness ([0003] of Sasaki).
Regarding Claim 7
FIG. 4 of Song discloses the dummy ground pad (68) includes a second ESD protection circuit (92) connected between the first power metal ring (82) and the first ground metal ring (83).
Claim 2 rejected under 35 U.S.C. 103 as being unpatentable over Song, Zuo and Sasaki, in view of Ker (U.S. Patent Pub. No. 2011/0198678) of record.
Regarding Claim 2
Song as modified by Zuo and Sasaki discloses Claim 1.
Song as modified by Zuo and Sasaki is silent with respect to “a second power metal ring for providing an input/output power supply voltage; and a second ground metal ring for providing an input/output ground voltage”.
FIG. 1 of Ker discloses a similar semiconductor device, comprising a first power metal ring (VDD1) for providing a power supply voltage; a first ground metal ring (VSS1) for providing a ground voltage; a second power metal ring (VDD2) for providing an input/output power supply voltage; and a second ground metal ring (VSS2) for providing an input/output ground voltage.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Song, as taught by Ker. The ordinary artisan would have been motivated to modify Song in the above manner for purpose of improving ESD protection ([0007] of Ker).
Claim 3 rejected under 35 U.S.C. 103 as being unpatentable over Song, Zuo, Sasaki and Ker, in view of Stockinger (U.S. Patent Pub. No. 2020/0395751).
Regarding Claim 3
Song as modified by Zuo, Sasaki and Ker discloses Claim 2.
Song as modified by Zuo, Sasaki and Ker is silent with respect to “a capacitor connected between the first end of the transistor and a gate of the transistor; and a resistor directly connecting the gate of the transistor and a second end of the transistor to the first ground metal ring or the second ground metal ring, wherein the gate of the transistor is connected only to the capacitor and the resistor”.
FIG. 3A of Stockinger discloses a similar semiconductor device, comprising a capacitor (CGD) connected between the first end of the transistor (100) and a gate of the transistor; and a resistor (R) directly connecting the gate of the transistor and a second end (S) of the transistor to the first ground metal ring (VSS) or the second ground metal ring, wherein the gate of the transistor is connected only to the capacitor and the resistor.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Song, as taught by Stockinger. The ordinary artisan would have been motivated to modify Song in the above manner for purpose of protecting ICs from ESD events ([0002] of Stockinger).
Claims 4 and 5 rejected under 35 U.S.C. 103 as being unpatentable over Song, Zuo, Sasaki and Ker, in view of Hung (U.S. Patent Pub. No. 2016/0284692) of record.
Regarding Claim 4
Song as modified by Zuo, Sasaki and Ker discloses Claim 2.
Song as modified by Zuo, Sasaki and Ker is silent with respect to “a first diode circuit is connected to one of the first power metal ring and the second power metal ring and connected to one of the first ground metal ring and the second ground metal ring”.
FIG. 2 of Hung discloses a similar semiconductor device, comprising a first diode circuit (220/230) is connected to one of the first power metal ring (211) and the second power metal ring and connected to one of the first ground metal ring (213) and the second ground metal ring.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Song, as taught by Hung. The ordinary artisan would have been motivated to modify Song in the above manner for purpose of providing protection.
Regarding Claim 5
FIG. 2 of Hung discloses a first diode (220) having a cathode connected to the first power metal ring or the second power metal ring (211); and a second diode (230) having an anode connected to the first ground metal ring or the second ground metal ring (213), wherein the anode of the first diode is connected to a cathode of the second diode, and wherein the anode of the first diode and the cathode of the second diode are connected to a contact for transmitting the input/output signal (212).
Claim 9 rejected under 35 U.S.C. 103 as being unpatentable over Balatsos (U.S. Patent Pub. No. 2009/0049321) of record, in view of Choi (KR 20110033328) of record, in view of Sasaki, in view of Zuo.
Regarding Claim 9
FIG. 1 of Balatsos discloses a semiconductor device, comprising: a core logic unit (102) configured to receive a power and configured to receive and process an input signal to generate an output signal; signal pads (104) configured to transmit the input signal to the core logic unit or output the output signal from the core logic unit to an outside of the semiconductor device; a power/ground pad (106) configured to transfer the power provided from a power rail to the core logic unit, and (FIG. 3) a clamp circuit (230) comprises a transistor (310) having a first end directly connected to the first power metal ring (VDD) .
Balatsos is silent with respect to “a dummy power/ground pad disposed at a position of a filler pad”; “the dummy power/ground pad does not function exchange the power, the input signal, and the output signal with the core logic unit”; “the dummy power/ground pad is disposed adjacent to the signal pads, and wherein the dummy power/ ground pad are disposed in pairs and adjacent to each other”; “the power rail includes a plurality of power metal rings, wherein the plurality of power metal rings include a first power metal ring for providing a power supply voltage, and a first ground metal ring for providing a ground voltage”; a clamp circuit “is connected between the first power metal ring and the first ground metal ring on the dummy power/ground pad” and “a diode circuit is connected between the first power metal ring and the first ground metal ring on one of the signal pads, and wherein a discharge path having the lowest resistance is constituted through the diode circuit, the first power metal ring, the transistor of the clamp circuit and the first ground metal ring when an electrostatic discharge (ESD) event occurs in the first signal pad”.
FIG. 10 of Sasaki discloses a similar semiconductor device, wherein the power rail includes a plurality of power metal rings, wherein the plurality of power metal rings include a first power metal ring (30) for providing a power supply voltage (VDD), and a first ground metal ring (31) for providing a ground voltage (GND), and a clamp circuit (4) comprises a transistor (10, FIG. 8) having a first end directly connected to the first power metal ring (5) to provide ESD protection [0003] and is connected between the first power metal ring and the first ground metal ring, wherein a diode circuit (1, 2) is connected between the first power metal ring and the first ground metal ring on one of the signal pads (7), and wherein a discharge path (9) having the lowest resistance is constituted through the diode circuit, the first power metal ring, the transistor of the clamp circuit and the first ground metal ring when an electrostatic discharge (ESD) event occurs in the first signal pad [0045]. Moreover, the recitation “a discharge path having the lowest resistance is constituted through the first diode circuit, the first power metal ring, the transistor of the first clamp circuit and the first ground metal ring when an electrostatic discharge (ESD) event occurs in the first signal pad” is only a statement of the inherent properties of the device. When the structure recited in the prior art is substantially identical to that of the claimed invention, then the claimed properties or functions are presumed to be inherent. Or where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. See MPEP 2112.01.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Balatsos, as taught by Sasaki. The ordinary artisan would have been motivated to modify Balatsos in the above manner for purpose of ensuring ESD robustness ([0003] of Sasaki).
Balatsos as modified by Sasaki is silent with respect to “a dummy power/ground pad disposed at a position of a filler pad”; “the dummy power/ground pad does not function exchange the power, the input signal, and the output signal with the core logic unit”; “the dummy power/ground pad is disposed adjacent to the signal pads, and wherein the dummy power/ ground pad are disposed in pairs and adjacent to each other” and a clamp circuit “on the dummy power/ground pad”.
FIG. 2 of Choi discloses a similar semiconductor device, comprising a dummy power/ground pad (241/242) disposed at a position of a filler pad, wherein the dummy power/ground pad does not function exchange the power, the input signal, and the output signal with the core logic unit, and wherein the dummy power/ground pad is disposed adjacent to the signal pads (230), and wherein the dummy power/ ground pad are disposed in pairs and adjacent to each other, wherein the power rail includes a plurality of power metal rings, wherein the plurality of power metal rings include a first power metal ring for providing a power supply voltage (VDD), and a first ground metal ring for providing a ground voltage (VSS).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Balatsos, as taught by Choi. The ordinary artisan would have been motivated to modify Balatsos in the above manner for purpose of improving ESD protection performance (see, e.g., [0028] of Song).
Balatsos as modified by Sasaki and Choi is silent with respect to a clamp circuit “on the dummy power/ground pad”.
FIG. 3 of Zuo discloses a similar semiconductor device, comprising a dummy power pad (320), wherein the dummy power pad includes a first clamp circuit (336) connected between the first power metal ring (PIXVDD) and the first ground metal ring (AGND), and wherein the first clamp circuit includes a transistor having a first end directly connected to the first power metal ring.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Balatsos, as taught by Zuo. The ordinary artisan would have been motivated to modify Balatsos in the above manner for purpose of limiting voltage spikes to protect devices.
Claims 11-12 rejected under 35 U.S.C. 103 as being unpatentable over Balatsos, Sasaki, Choi and Zuo, in view of Ker (U.S. Patent Pub. No. 2011/0198678) of record.
Regarding Claim 11
Balatsos as modified by Sasaki, Choi and Zuo discloses Claim 9.
Balatsos as modified by Sasaki, Choi and Zuo is silent with respect to “a second power metal ring for providing an input/output power supply voltage; and a second ground metal ring for providing an input/output ground voltage”.
FIG. 1 of Ker discloses a similar semiconductor device, comprising a first power metal ring (VDD1) for providing a power supply voltage; a first ground metal ring (VSS1) for providing a ground voltage; a second power metal ring (VDD2) for providing an input/output power supply voltage; and a second ground metal ring (VSS2) for providing an input/output ground voltage.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Balatsos, as taught by Ker. The ordinary artisan would have been motivated to modify Balatsos in the above manner for purpose of improving ESD protection ([0007] of Ker).
Regarding Claim 12
FIG. 2 of Choi discloses the dummy power/ground pad is connected to the power metal ring. FIG. 1 of Ker discloses the plurality of power metal rings include a clamp circuit.
Claim 13 rejected under 35 U.S.C. 103 as being unpatentable over Balatsos, Sasaki Choi and Ker, in view of Stockinger.
Regarding Claim 13
Balatsos as modified by Sasaki, Choi, Zuo and Ker discloses Claim 12.
Balatsos as modified by Sasaki, Choi, Zuo and Ker is silent with respect to “a capacitor connected between the first end of the transistor and a gate of the transistor; and a resistor directly connecting the gate of the transistor and a second end of the transistor to the first ground metal ring or a second ground metal ring, wherein the gate of the transistor is connected only to the capacitor and the resistor”.
FIG. 3A of Stockinger discloses a similar semiconductor device, comprising a capacitor (CGD) connected between the first end of the transistor (100) and a gate of the transistor; and a resistor (R) directly connecting the gate of the transistor and a second end (S) of the transistor to the first ground metal ring (VSS) or the second ground metal ring, wherein the gate of the transistor is connected only to the capacitor and the resistor.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Balatsos, as taught by Stockinger. The ordinary artisan would have been motivated to modify Balatsos in the above manner for purpose of protecting ICs from ESD events ([0002] of Stockinger).
Claims 14 and 15 rejected under 35 U.S.C. 103 as being unpatentable over Balatsos, Sasaki, Choi and Ker, in view of Hung.
Regarding Claim 14
Balatsos as modified by Sasaki, Choi and Ker discloses Claim 11.
Balatsos as modified by Sasaki, Choi and Ker is silent with respect to “a diode circuit connected to one of the first power metal ring and the second power metal ring and one of the first ground metal ring and the second ground metal ring”.
FIG. 2 of Hung discloses a similar semiconductor device, comprising a first diode circuit (220/230) is connected to one of the first power metal ring (211) and the second power metal ring and connected to one of the first ground metal ring (213) and the second ground metal ring.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Balatsos, as taught by Hung. The ordinary artisan would have been motivated to modify Balatsos in the above manner for purpose of providing protection.
Regarding Claim 15
FIG. 2 of Hung discloses a first diode (220) having a cathode connected to the first power metal ring or the second power metal ring (211); and a second diode (230) having an anode connected to the first ground metal ring or the second ground metal ring (213), and a cathode connected to the signal input pad (212).
Pertinent Art
US 20200083705 and 20110198678 each discloses the first clamp circuit includes a transistor having a first end directly connected to the first power metal ring to provide ESD protection. Pertinent art also includes US 20120226929 and 20070018193.
Response to Arguments
Applicant’s arguments with respect to Claims 1 and 9 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897
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