DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Acknowledgement is made of the amendment received on 03/20/2026. Claims 1, 3-10, and 16-22 are pending in this application. Claims 1 and 4-8 are amended. Claim 2 is canceled. Claims 16-22 are new.
Claim Objections
Claim 20 is objected to because of the following informalities:
In claim 20, line 2, “layer is made of Al2O2, Al or Cu” should read --layer is made of Al2O3, Al or Cu-- (emphasis added).
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4, 7, 9, 16-19, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2019/0237382; hereinafter ‘Kim’) in view of Anaya calvo et al. (US 2017/0330816; hereinafter ‘Anaya’).
Regarding claim 1, Kim teaches a fan-out wafer-level package (100, FIG. 2, [0019]) comprising:
at least one integrated circuit (120) ,
an internal heat spreader (130) thermally connected to the at least one integrated circuit (130 thermally connected to 120, [0027]),
and bonded to the at least one integrated circuit via a thermally conductive interface layer (125 disposed between 120 and 130 and made of thermally conductive material, FIG. 5, [0042-0043]),
wherein the internal heat spreader is embedded in the fan-out wafer-level package (130 embedded in 100).
Kim does not teach that the thermally conductive interface layer having a thickness in the range of 20 nm to 500 nm.
Anaya teaches a fan-out wafer-level package (Figs. 1(a) and 1(b), [0011, 0068]) comprising a thermally conductive interface layer (a chromium layer bonded to the diamond heat spreader; hereinafter ‘CrL’) having a thickness in the range of 20 nm to 500 nm (CrL having a 50 nm to 250 nm, [0055]).
As taught by Anaya, one of ordinary skill in the art would utilize and modify the above teaching into Kim to obtain and achieve the fan-out wafer-level package comprising a thermally conductive interface layer having a thickness in the range of 20 nm to 500 nm as claimed, because it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Anaya in combination with Kim due to above reason.
Regarding claim 3, Kim in view of Anaya teaches the fan-out wafer-level package according to claim 1, wherein the internal heat spreader comprises Si or a metal (Kim: 130 comprises Cu, [0028]).
Regarding claim 4, Kim in view of Anaya teaches the fan-out wafer-level package according to claim 1, wherein the at least one integrated circuit comprises at least two integrated circuits (Kim: 120a and 120b, FIG. 8, [0051]), wherein the internal heat spreader is thermally connected to the at least two integrated circuits (130a is thermally connected to 120a and 120b).
Regarding claim 7, Kim in view of Anaya teaches the fan-out wafer-level package according to claim 1, additionally comprising
a redistribution layer (Kim: 110, FIG. 2, [0019]) on a backside of the fan-out wafer-level package (110 disposed on a lower portion of 120) and
at least one trough-substrate via (144, [0021]) electrically connecting the additional redistribution layer to a front of the fan-out wafer-level package, namely to the at least one integrated circuit (144 electrically connecting 110 to 120).
Regarding claim 9, Kim in view of Anaya teaches a module (Kim: 1000, FIG. 12, [0089]) comprising a fan-out wafer-level package according to claim 1 and at least one additional functional element either on top or on bottom of the fan-out wafer level package (second semiconductor package 300 disposed on first semiconductor package 100, [0089]).
Regarding claim 16, Kim in view of Anaya teaches the fan-out wafer-level package according to claim 1, Kim does not teach the fan-out wafer-level package, wherein the thermally conductive interface layer has a thickness in the range of 30 to 200 nm.
Anaya teaches the fan-out wafer-level package, wherein the thermally conductive interface layer has a thickness in the range of 30 to 200 nm (CrL having a 100 nm, [0068]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that in Anaya to include the fan-out wafer-level package wherein the thermally conductive interface layer has a thickness in the range of 30 to 200 nm as claimed, because it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Regarding claim 17, Kim in view of Anaya teaches the fan-out wafer-level package according to claim 1, Kim does not teach the fan-out wafer-level package, wherein the thermally conductive interface layer has a thickness in the range of 50 to 100 nm.
Anaya teaches the fan-out wafer-level package, wherein the thermally conductive interface layer has a thickness in the range of 50 to 100 nm (CrL having a 100 nm, [0068]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that in Anaya to include the fan-out wafer-level package wherein the thermally conductive interface layer has a thickness in the range of 50 to 100 nm as claimed, because it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Regarding claim 18, Kim in view of Anaya teaches the fan-out wafer-level package according to claim 1, wherein the thermally conductive interface layer is a multi-layer structure (Kim: 125 comprises a multiple layers, [0043]).
Regarding claim 19, Kim in view of Anaya teaches the fan-out wafer-level package according to claim 1, wherein the thermally conductive interface layer comprises a first layer and a second layer (Kim: 125 comprises a multiple layers, [0043].
Regarding claim 22, Kim in view of Anaya teaches the fan-out wafer-level package according to claim 1, Kim does not teach the fan-out wafer-level package, wherein the thermally conductive interface layer forms a bonding layer effecting a permanent bonding between the at least one integrated circuit and the internal heat spreader via a covalent bonding technique.
Anaya teaches the fan-out wafer-level package, wherein the thermally conductive interface layer forms a bonding layer effecting a permanent bonding between the at least one integrated circuit and the internal heat spreader via a covalent bonding technique (CrL forming chromium carbide bonding with the diamond heat spreader, [0047, 0052]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that in Anaya to include the fan-out wafer-level package wherein the thermally conductive interface layer forms a bonding layer effecting a permanent bonding between the at least one integrated circuit and the internal heat spreader via a covalent bonding technique as claimed, because carbide-forming bonding structures improve bonding stability and thermal transport across the bonding interface in semiconductor heat dissipation applications [0052, 0053].
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Kim. (US 2019/0237382) in view of Anaya (US 2017/0330816), and further in view of König et al. (US 2021/0247151; hereinafter ‘König’).
Regarding claim 5, Kim in view of Anaya teaches the fan-out wafer-level package according to claim 1, but does not teach the fan-out wafer-level package wherein the internal heat spreader comprises heat sink structures.
König teaches a semiconductor cooling assembly wherein the internal heat spreader comprises heat sink structures [0029, 0033].
Although, König does not explicitly teach that its heat sink structure is implemented within a fan -out wafer-level package.
König, however, provides a semiconductor cooling assembly that is closely analogous to a semiconductor package.
As taught by König, one of ordinary skill in the art would utilize and modify the above teaching into Kim in view of Anaya to obtain and achieve the fan-out wafer-level package wherein the internal heat spreader comprises heat sink structures as claimed, because additional heat sink structures are provided to improve thermal dissipation [0031].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by König in combination with Kim in view of Anaya due to above reason.
Regarding claim 6, Kim in view of Anaya and König teaches the fan-out wafer-level package according to claim 5, Kim in view of Anaya does not teach the fan-out wafer-level package wherein the heat sink structures are cooling ribs integrated into the internal heat spreader or wherein the heat sink structures are micro-channels of a microfluidic cooling system, which are integrated into the internal heat spreader.
König teaches that the heat sink structures are cooling ribs integrated into the internal heat spreader or wherein the heat sink structures are micro-channels of a microfluidic cooling system, which are integrated into the internal heat spreader (heat sink structure comprises a plurality of fins and/or pins and/or micro-channel, [0031]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that in König to include the fan-out wafer-level package wherein the additional heat sink structures are integrated cooling ribs or wherein the additional heat sink structures are micro-channels of a microfluidic cooling systems as claimed, because such structures are used to maximize surface area and thereby improve cooling efficiency [0031].
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kim. (US 2019/0237382) in view of Anaya (US 2017/0330816), and further in view of Hool (US 7115988).
Regarding claim 8, Kim in view of Anaya teaches the module according to claim 7, but does not teach the fan-out wafer-level package additionally comprising at least one area embedded in the internal heat spreader that includes at least one electrically active device or at least one electrically passive device.
Hool teaches a fan-out wafer-level package (100, FIGS. 1A and 1B, col. 6, line 11) additionally comprising at least one area embedded in the internal heat spreader (101, col. 6, line 11), that includes at least one electrically active device or at least one electrically passive device (130 embedded within 101, FIG. 1B, col. 6, line 47).
As taught by Hool, one of ordinary skill in the art would utilize and modify the above teaching into Kim in view of Anaya to obtain and achieve the fan-out wafer-level package additionally comprising at least one area embedded in the internal heat spreader that includes at least one electrically active device or at least one electrically passive device as claimed, because embedding a bypass capacitor within the heat spreader provides decoupling capacitance, minimizes simultaneous switching noise (SSN), and reduces inductance and resistance associated with electrical connections between the power source and the die, thereby improving package performance (col. 11, lines 23-51).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Hool in combination with Kim in view of Anaya due to above reason.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kim. (US 2019/0237382) in view of Anaya (US 2017/0330816), and further in view of NDIP et al. (US 2018/0191053; hereinafter ‘NDIP’).
Regarding claim 10, Kim in view of Anaya teaches the module according to claim 9, but does not teach the module comprising a redistribution layer and at least one embedded antenna as a functional element realized within the redistribution layer or as an aperture-type antenna, which is built to be fed with a feeding structure inside the redistribution layer together with an additional antenna structure within a bonding interface area of the fan-out wafer-level package, preferably the module further comprising a lens.
NDIP teaches a module (100, Fig. 4, [0072]) comprising a redistribution layer (16, Fig. 1, [0047]) and at least one embedded antenna as a functional element realized within the redistribution layer or as an aperture-type antenna (16a, [0047, 0051-0052]), which is built to be fed with a feeding structure (16v’, Fig. 3, [0066]) inside the redistribution layer together with an additional antenna structure (16*), within a bonding interface area of the fan-out wafer-level package, preferably the module further comprising a lens (21, Fig. 2e, [0062]).
As taught by NDIP, one of ordinary skill in the art would utilize and modify the above teaching into Kim in view of Anaya to obtain and achieve the module comprising a redistribution layer and at least one embedded antenna as a functional element realized within the redistribution layer or as an aperture-type antenna, which is built to be fed with a feeding structure inside the redistribution layer together with an additional antenna structure within a bonding interface area of the fan-out wafer-level package, preferably the module further comprising a lens as claimed, because embedding antennas in the redistribution layer and adding a lens provides shortened signal paths, improved signal integrity, and enhanced wireless functionality in high-frequency applications. Such measures are adopted to save space, enhance RF performance, and expand functionality [0003-0007].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by NDIP in combination with Kim in view of Anaya due to above reason.
Claims 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Kim. (US 2019/0237382) in view of Anaya (US 2017/0330816), and further in view of Snyder (US 2021/0210361).
Regarding claim 20, Kim in view of Anaya teaches the fan-out wafer-level package according to claim 1, but does not teach the fan-out wafer-level package wherein the thermally conductive interface layer is made of Al202, Al or Cu (see the above claim objection).
Snyder teaches a fan-out wafer-level package (semiconductor devices/power electronics devices mounted on a thermally conductive base plate for semiconductor cooling applications, [0010, 0018-0019]) wherein the thermally conductive interface layer is made of Al202, Al or Cu (an aluminum oxide layer (Al2O3 layer) positioned between a die of the power electronics devices and the base plate, [0018]).
As taught by Snyder, one of ordinary skill in the art would utilize and modify the above teaching into Kim in view of Anaya to obtain and achieve the fan-out wafer-level package wherein the thermally conductive interface layer is made of Al202, Al or Cu as claimed, because thermally conductive electrically insulating interface layers improve thermal transfer to thermally conductive base structures while maintaining electrical isolation in semiconductor cooling applications [0018, 0020].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Snyder in combination with Kim in view of Anaya due to above reason.
Regarding claim 21 Kim in view of Anaya teaches the fan-out wafer-level package according to claim 1, but does not teach the fan-out wafer-level package wherein the thermally conductive interface layer is electrically isolating.
Snyder teaches a fan-out wafer-level package (semiconductor devices/power electronics devices mounted on a thermally conductive base plate for semiconductor cooling applications, [0010, 0018-0019]) wherein the thermally conductive interface layer is electrically isolating (an electrical insulator comprising aluminum oxide (Al2O3) positioned between the power electronics devices and the base plate, [0020]).
As taught by Snyder, one of ordinary skill in the art would utilize and modify the above teaching into Kim in view of Anaya to obtain and achieve the fan-out wafer-level package wherein the thermally conductive interface layer is electrically isolating as claimed, because thermally conductive electrically insulating interface layers improve thermal transfer to thermally conductive base structures while maintaining electrical isolation in semiconductor cooling applications [0018, 0020].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Snyder in combination with Kim in view of Anaya due to above reason.
Response to Arguments
Applicant's arguments with respect to claims have been considered but are moot in view of the new ground of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 6/5/26
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