DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, per page 3, filed January 9, 2026, with respect to the title have been fully considered and are persuasive. The objection of October 9, 2025 has been withdrawn.
Applicant’s arguments, per pages 5-6, filed January 9, 2026, with respect to claim 19 have been fully considered and are persuasive. The rejection of October 9, 2025 has been withdrawn.
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on the combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Specifically Kidoh discloses (Fig. 4) where an insulating pad 51 can be a nitride and an insulating layer 34 is silicon oxide. See updated rejection below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2019/0035733) in view of Kidoh (US 2009/0212350).
Claim 1, Park discloses (see annotated Fig. 4 below) a three-dimensional semiconductor memory device, comprising: a substrate (10, substrate, Para [0044]) including a first region (r1) and a second region (r2), the second region extending from the first region (r2 extends from r1); a stack (ST, stacked structure, Para [0046]) including interlayer insulating layers (32, isolation insulating layer, Para [0050]) and gate electrodes (EL, plurality of electrodes, Para [0050]), which are alternately and repeatedly stacked on the substrate (32 and EL are alternately and repeatedly stacked on 10), the stack having a staircase structure on the second region (ST has a staircase structure on r2, hereinafter “stair”); an insulating layer (34/42, first insulating layer/second insulating layer, Para [0064]) covering the staircase structure of the stack (34/42 covers stair); first vertical channel structures (20/CEP/BLP in r1, vertical structures/cell pad/bit landing plug, Para [0056], [0065], hereinafter “vert1”) on the first region (vert1 is on r1), penetrating the stack, and in contact with the substrate (vert1 penetrates ST and is in contact with 10); first contact plugs (MC/CLP, contact plug/contact landing plug, Para [0059], hereinafter “plug1”) on the second region and penetrating the insulating layer and the stack (plug1 is on r2 and penetrates 34/42 and ST); and first insulating pads (under BRI, portions of 42 enclosing upper portions of plug1 are considered insulating pads, hereinafter “pad1”) in the insulating layer (pad1 is in 34/42) and enclosing upper portions of the first contact plugs, respectively (pad1 encloses upper portions of respective plug1), wherein the first insulating pads (pad1) overlap with the first vertical channel structures in a horizontal direction (pad1 overlaps with vert1 in x direction). Park does not explicitly disclose wherein the first insulating pads are formed of an insulating material that is different from an insulating material of the insulating layer.
However, Kidoh discloses (Fig. 4) wherein first insulating pads (51, wiring first insulating layer, Para [0086]) are formed of an insulating material (51 is made of silicon nitride, Para [0086]) that is different (51 is silicon nitride and 45 can be made of silicon oxide) from an insulating material (45 can be silicon oxide, Para [0072]) of an insulating layer (45, interlayer insulating layer, Para [0045]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing
date of the claimed invention to apply the teachings of Kidoh, including the specific material of the
insulating pad and insulating layer to the teachings of Park.
The motivation to do so is that the combination yields the predictable results of allowing for the
selection of a known material based on its suitability for the intended use as an insulation layer as they have different etch properties. Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See also MPEP 2144.07.
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Claim 2, Park in view of Kidoh discloses the semiconductor memory device as claimed in claim 1. Park discloses (see annotated figure of Claim 1 above) further comprising: second vertical channel structures (20/CEP/BLP in r2, vertical structures/cell pad/bit landing plug, Para [0056], [0065], where plurality would extend in y direction, hereinafter “vert2”) on the second region (vert2 is on r2), penetrating the insulating layer and the stack (vert2 penetrates 34/42 and ST), and being adjacent to each of the first contact plugs (vert2 is adjacent to plug1); and second insulating pads (under BRI, portions of 42 enclosing upper portions of vert2 are considered insulating pads, hereinafter “pad2”) in the insulating layer (pad2 is in 34/42) and enclosing upper portions of the second vertical channel structures, respectively (pad2 encloses upper portions of respective vert2), wherein the second insulating pads overlap with the first insulating pads in the horizontal direction (pad2 overlaps pad1 in x direction).
Claim 14, Park in view of Kidoh discloses the semiconductor memory device as claimed in claim 1. Park discloses (see annotated figure of Claim 1 above) wherein the stack (ST) includes mold pillars on the second region (r2) and extending in a vertical direction (as can be seen in figure above, there are column pillars of 34 in between pluralities of MC and ST that under BRI is considered mold pillar, hereinafter “pillar”).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2019/0035733) in view of Kidoh (US 2009/0212350) as applied to claim 2 above, and further in view of Baek (US 2020/0388624). Claim 3, Park in view of Kidoh discloses the semiconductor memory device as claimed in claim 1. Park discloses (figs. 1 and 4) the insulating layer (34/42) includes silicon oxide (34 may be silicon oxide, Para [0058]). Park in view of Kidoh does not explicitly disclose the first insulating pads and the second insulating pads each include silicon nitride. However, Baek discloses (Fig. 5) where insulating pads 246 and 248 may be silicon nitride (Para [0055]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing
date of the claimed invention to apply the teachings of Baek, including the specific material of the
silicon nitride to the teachings of Park in view of Kidoh.
The motivation to do so is that the combination yields the predictable results of allowing for the
selection of a known material based on its suitability for the intended use as an insulative pad. Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See also MPEP 2144.07.
Allowable Subject Matter
Claims 4-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The following is an examiner’s statement of reasons for allowance: the closest prior art of record, Park (US 2019/0035733), Kidoh (US 2009/0212350), Baek (US 2020/0388624), Hwang (US 2016/0268264), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 4 (from which claims 5-8 depend), each of the first contact plugs includes a first portion enclosed by the insulating layer, and a second portion on the first portion and enclosed by each of the first insulating pads, a side surface of the first portion has a convexly curved profile…
Regarding Claim 9 (from which claims 10-13 depend), the first insulating pads include lower insulating pads in the lower insulating layer and enclosing upper portions of the lower contact plugs, and upper insulating pads in the upper insulating layer and enclosing upper portions of the upper contact plugs.
Claims 15-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: The following is an examiner’s statement of reasons for allowance: the closest prior art of record, Park (US 2019/0035733), Kidoh (US 2009/0212350), Baek (US 2020/0388624), Hwang (US 2016/0268264), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 15 (from which claims 16-18 depend), a third insulating layer on the second insulating layer and coplanar with a topmost surface of the stack…
Regarding Claim 19 (from which claim 20 depends), wherein outer surfaces of the insulating pads are in contact with respective inner surfaces of the insulating layer…
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hwang (US 2016/0268264) discloses (annotated Fig. 4 below) a three-dimensional semiconductor memory device, comprising: a substrate (100, substrate, Para [0074]) including a first region (r1) and a second region (r2), the second region extending from the first region (r2 extends from r1); a stack (115/310, insulation pattern/gate electrodes, Para [0079]) including interlayer insulating layers (115) and gate electrodes (310), which are alternately and repeatedly stacked on the substrate (115 and 310 are repeatedly stacked on 100), the stack having a staircase structure on the second region (115/310 has staircase structure on r2, hereinafter “stair”); an insulating layer (130/140/240/340/390, first insulating interlayer/second insulating interlayer/third insulating interlayer/fourth insulating interlayer/fifth insulating interlayer, Para [0109] [0115], hereinafter “ins”) covering the staircase structure of the stack (ins covers stair); first vertical channel structures (550/230/210/160, third via/capping pattern/channel/semiconductor pattern, Para [0091] [0124], hereinafter “vchan”) on the first region (vchan is on r1), penetrating the stack, and in contact with the substrate (vchan penetrates 115/310 and contacts 100); first contact plugs (380, first contact plugs, Para [0076]) on the second region and penetrating the insulating layer and the stack (380 is on r2 and penetrates ins and 115/310); and first insulating pads (under broadest reasonable interpretation (BRI) portions of 340 surrounding each 380 are considered insulating pads, hereinafter “pad”) in the insulating layer (pad is in ins) and enclosing upper portions of the first contact plugs, respectively (each pad encloses upper portions of each respective 380), wherein the first insulating pads (pad) overlap with the first vertical channel structures (vchan) in a horizontal direction (pad overlaps with vchan in the horizontal direction).
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Hwang discloses (see annotated Fig. 4 of claim 1) the semiconductor memory device as claimed in claim 1, wherein the stack (115/310) includes mold pillars on the second region and extending in a vertical direction (as can be seen in figure above, there are column pillars of 130 in between pluralities of 385 and 115/310 under BRI is considered mold pillar, hereinafter “pillar”).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO G RAMALLO whose telephone number is (571)272-9227. The examiner can normally be reached Monday-Friday 10am - 6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/G.G.R/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812