The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tang et al. (U.S. Patent Application Publication 2016/0186726, hereinafter referred to as Tang).
As to claim 1, Tang teaches 1. An integrated circuit (IC) package comprising: a first IC die [102 in Fig. 3A for example] comprising first metallization features [118 in Fig. 3A] on a first side of the first IC die; a second IC die [102 in Fig. 3A] laterally adjacent to the first IC die and comprising second metallization features [118 in Fig. 3A] on a first side of the second IC die; a third IC die [128 in Fig. 3A] comprising third metallization features on a first side of the third IC die; a glass layer [124 in Fig. 3A] between the third IC die and both of the first IC die and the second IC die; a plurality of first through vias extending through the glass layer and coupling the third metallization features with first ones of the first metallization features and with first ones of the second metallization features; a plurality of second through vias extending through the glass layer [122 in Fig. 3A]; a dielectric material around the third die [104b in Fig. 3A]; and a package metallization within the dielectric material, the package metallization coupled to at least one of the first, second, or third IC die, and terminating at a plurality of package interconnect interfaces [106b in Fig. 5A].
As to claim 2, Tang teaches 2. The IC package of claim 1, wherein first ones of the first metallization features comprise predominantly Cu and are in direct contact with respective ones of the plurality of first through vias, and first ones of the second metallization features comprises predominantly Cu and are in direct contact with respective ones of the plurality of first through vias. [¶0064]
As to claim 3, Tang teaches 3. The IC package of claim 1, wherein the first through vias are coupled to the first ones of the first and second metallization features through a solder. [¶0078]
As to claim 4, Tang teaches 4. The IC package of claim 1, wherein the third metallization features comprise predominantly Cu and are in direct contact with respective ones of the plurality of first through vias. [¶0064]
As to claim 5, Tang teaches 5. The IC package of claim 1, wherein the plurality of second through vias couple the package metallization with second ones of the first metallization features and with second ones of the second metallization features, wherein the second ones of the first metallization features comprise predominately Cu and are in direct contact with respective ones of the second through vias; and the second ones of the second metallization features comprise predominately Cu and are in direct contact with respective ones of the second through vias. [¶0064]
As to claim 6, Tang teaches 6. The IC package of claim 1, wherein the plurality of second through vias couple the package metallization with second ones of the first metallization features and with second ones of the second metallization features, wherein the second through vias are coupled to the second ones of the first and second metallization features through a solder. [¶0078]
As to claim 7, Tang teaches 7. The IC package of claim 1, further comprising fourth metallization features on a second side of the third die opposite the first side of the third die, wherein the fourth metallization features are in direct contact with respective ones of the package interconnect interfaces. [¶0072]
As to claim 8, Tang teaches 8. The IC package of claim 1, further comprising fourth metallization features on a second side of the third IC die opposite the first side of the third die, wherein the package metallization comprises solder features connecting the fourth metallization features with respective ones of the package interconnect interfaces. [¶0078]
As to claim 9, Tang teaches 9. The IC package of claim 1, wherein the package metallization comprises through- dielectric interconnect features comprised predominately Cu and in direct contact with the plurality of second through vias and with respective ones of the package interconnect interfaces. [¶0064]
As to claim 10, Tang teaches 10. The IC package of claim 9, wherein a surface of the glass layer is parallel to the first side of the third IC die, the through-dielectric interconnect features extend a first distance in a first direction perpendicular to the surface of the glass layer, and the first distance is greater than or substantially equal to a thickness of the third die. [see Fig. 16 for example]
As to claim 11, Tang teaches 11. The IC package of claim 1, further comprising an adhesion layer between the glass layer and the dielectric material, wherein the adhesion layer comprises an epoxy polymer. [¶0059]
As to claim 12, Tang teaches 12. The IC package of claim 1, wherein the dielectric material comprises one of a mold compound, Ajinomoto Build-up Film (ABF), or a polyimide material. [¶0070]
As to claim 13, Tang teaches 13. The IC package of claim 1, further comprising a second dielectric material around the first and second IC die, and an adhesion layer between the glass layer and the second dielectric material, wherein the second dielectric material comprises one of a mold compound, Ajinomoto Build-up Film (ABF), or polyamide material, and the adhesion layer comprises an epoxy polymer. [¶0060]
As to claim 14, Tang teaches 14. The IC package of claim 1, wherein a thickness of the glass layer is less than 100 microns. [¶0060]
As to claim 15, Tang teaches 15. A system comprising: a microprocessor, wherein the microprocessor comprises circuitry on a first IC die and comprising first metallization features on a first side of the second IC die; a memory coupled to the microprocessor, wherein the memory comprises circuitry on a second IC die laterally adjacent to the first IC die and comprising second metallization features on a first side of the second IC die; a communication bridge, wherein the communication bridge comprises a third IC die comprising third metallization features on a first side of the third IC die; a glass layer between the third IC die and both of the first die and the second IC die; a plurality of first through vias extending through the glass layer and coupling the third metallization features with first ones of the first metallization features and with first ones of the second metallization features; and a dielectric material around the third IC die comprising a package metallization, wherein the package metallization is coupled to at least one of the first, second, or third IC die, and terminates at a plurality of package interconnect interfaces. [see rejection claim 1 above]
As to claim 16, Tang teaches 16. The system of claim 15, wherein first ones of the first metallization features comprise predominantly Cu and are in direct contact with respective ones of the plurality of first through vias, and first ones of the second metallization features comprises predominantly Cu and are in direct contact with respective ones of the plurality of first through vias. [¶0064]
As to claim 17, Tang teaches 17. The system of claim 15, wherein the third metallization features comprise predominantly Cu and are in direct contact with respective ones of the plurality of first through vias. [¶0064]
As to claim 18, Tang teaches 18. The system of claim 15, further comprising a plurality of second through vias extending through the glass layer, wherein the plurality of second through vias couple the package metallization with second ones of the first metallization features and with second ones of the second metallization features. [¶0064]
As to claim 19, Tang teaches 19. A method for fabricating an IC device structure, the method comprising: receiving a first IC die comprising first metallization features on a first side of the first die; receiving a second IC comprising second metallization features on a first side of the second die; receiving a third IC die comprising third metallization features on a first side of the third die; placing a glass layer between the third die and both of the first die and the second die, wherein the second IC die is laterally adjacent to the first die, a plurality of first through vias extend through the glass layer and couple the third metallization features with first ones of the first metallization features and with first ones of the second metallization features, and a plurality of second through vias extend through the glass layer; forming a dielectric material around the third die; and forming a package metallization within the dielectric material, the package metallization coupled to at least one of the first, second, or third IC die, and terminating at a plurality of package interconnect interfaces. [see rejection claim 1 above]
As to claim 20, Tang teaches 20. The method of claim 19, further comprising: bonding the third metallization features with respective ones of the plurality of first through vias, wherein the third metallization features comprise predominantly Cu and are in direct contact with respective ones of the plurality of first through vias. [¶0064]
Conclusion
Claims 1-20 are rejected as explained above.
The prior art made of record in the PTO-892 form and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAEHWAN OH whose telephone number is (571) 270-5800. The examiner can normally be reached on Monday - Friday 9:00 AM-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached on 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAEHWAN OH/
Primary Examiner, Art Unit 2899