Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
2. Claims 1-12 are presented for examination.
Claim Rejections - 35 USC § 102
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
5. Claims 1-12 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Li et al. US Pub. No. 8754794.
As per claims 1 and 7, Fig. 4 of is directed to an adjustable programming circuit for generating a programming voltage that comprises one of a plurality of different voltages to program a non-volatile memory cell (col. 3, lines 47-49) for a neural network to store one of a plurality of different voltages on a floating gate of the non- volatile memory cell, comprising: an operational amplifier (214) comprising a first input terminal (+ terminal of 214), a second input terminal (- terminal of 214), and an output terminal (TB), the first input terminal receiving a reference voltage (-Vref); a first switched capacitor network (218 or Fig. 5) coupled between the second input terminal of the operational amplifier and the output terminal of the operational amplifier; and a second switched capacitor network (216 or Fig. 5) coupled between an input voltage and the second input terminal of the operational amplifier; wherein the output terminal of the operational amplifier outputs a programming voltage (TB,) that varies (Fig. 6) in response to a capacitance (Fig. 5) of the first switched capacitor network and a capacitance (Fig. 5) of the second switched capacitor network.
As per claims 2 and 8, Fig. 4 or 5 of Li discloses wherein the first switched capacitor network comprises an adjustable capacitor (218).
As per claims 3-4 and 9-10 , Fig. 4 or 5 of Li discloses wherein the second switched capacitor network comprises an adjustable capacitor (216).
As per claims 5-6 and 11-12, a column 3, lines 47-52 of Li discloses wherein the non-volatile memory cell is a stacked-gate memory cell (other suitable types of memory).
6. Claims 1-4 and 7-10 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Nakamura et al. US Pub. No. 8754794.
As per claims 1 and 7, Fig. 8(a) or 8(c) of Nakamura is directed to an adjustable programming circuit for generating a programming voltage that comprises one of a plurality of different voltages to program a non-volatile memory cell for a neural network to store one of a plurality of different voltages on a floating gate of the non- volatile memory cell, comprising: an operational amplifier (800) comprising a first input terminal (+ terminal of 800), a second input terminal (- terminal of 800), and an output terminal (Out), the first input terminal receiving a reference voltage (GND); a first switched capacitor network (804) coupled between the second input terminal of the operational amplifier and the output terminal of the operational amplifier; and a second switched capacitor network (802) coupled between an input voltage and the second input terminal of the operational amplifier; wherein the output terminal of the operational amplifier outputs a programming voltage (Output) that varies in response to a capacitance (Fig. 8(a) or 8(c)) of the first switched capacitor network and a capacitance (Fig. 8(a) or 8(c)) of the second switched capacitor network.
As per claims 2 and 8, a claim 4 of Nakamura discloses wherein the first switched capacitor network comprises an adjustable capacitor (claim 4).
As per claims 3-4 and 9-10, a claim 2 of Nakamura discloses wherein the second switched capacitor network comprises an adjustable capacitor (claim 2).
7. The prior art made of record and not relied upon is considered pertinent to applicants’ disclosure. Note the additional references cited on the attached PTO-892 form which show further examples of a non-volatile memory cell for a neural network with a stacked-gate or/and a split-gate memory cell.
8. When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
9. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the date of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOAI V HO whose telephone number is (571)272-1777. The examiner can normally be reached 7:00 AM -- 5:30 PM from Thursday and Friday of the first week of a bi-week and Tuesday and Wednesday of the second week.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is (571)-273-8300.
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/HOAI V HO/Primary Examiner, Art Unit 2827
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