DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 09/23/2025 is in compliance with provisions of 37 CFR 1.97. Accordingly, the information disclosure is being considered by the Examiner.
Response to Amendment
The amendment with respect to claims 1-2, 7, 13, and 21 filed on 12/09/2025 have been fully considered for examination based on their merits. The previously presented claims 3-6, 8-11, 14-20, and 22 have been considered. Claims 12, and 23-27 are canceled. New claims 28-31 have been considered and entered.
Response to Arguments
Applicant’s arguments, see Remarks, pages 6-9, filed 12/09/2025, with respect to the rejection(s) of claim(s) 1-22 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of JEFFREY.
Regarding Independent Claim 1. Applicant argues that none of the prior art discloses or render obvious the amended features of claim 1 now recites, “A method comprising; providing a first chip having a substrate…stack on the substrate…wherein the coherence device layer comprises monocrystalline silicon…sacrificial material.” Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as mentioned in the above paragraph. For instance, the prior-art of JEFFREY teaches the amended limitations of claim 1, in regard to the manufacturing of the “carrier chip” including a multilayer wiring stack and a capping layer.
Regarding Dependent Claim 12. Applicant argues that the ROMANKIW in view of O’CONNEL fails to disclose or suggest the “coherence device layer is a monocrystalline silicon layer.” Applicant further canceled the claim 12, and rolled over within the independent claim 1. Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration of rolled over claim 12 into an independent claim 1, a new ground(s) of rejection is made as mentioned in the above paragraph. For instance, the prior-art of JEFFREY teaches the amended limitations of claim 1, in regard to the manufacturing of the “carrier chip” including a multilayer wiring stack and a capping layer. As per the Figure 1A of JEFFREY, the capping layer (16) is mapped to the coherent device layer, which is on the circuit element layer stack (12) in the plurality of layers (130), wherein the capping layer is formed from a low-loss dielectric material such as mono-crystalline silicon [0048].
Regarding Claims 2-11, 13-22, and 28-31. The independent Claim(s) 2-11, 13-22, and 28-31 follow similar arguments as Claim 1, upon further consideration, a new-grounds of rejection is made based on the prior-art mentioned above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-5, 18-22, and 28-29 is/are rejected under 35 U.S.C. 103 as being unpatentable Evan Jeffrey et al, (hereinafter JEFFREY), US 20210175095 A1, in view of Lubomyr Taras Romankiw, (hereinafter ROMANKIW), US 6596624 B1.
Regarding Claim 1, JEFFREY teaches a method (Figs. 3A-3F, manufacturing process of a quantum computing device, [0040]) comprising:
providing a first chip (Fig. 1A, 10, carrier chip) having:
a substrate (Fig. 1A, 140, substrate layers);
a circuit element layer stack (Fig. 1A, 100, multilayer wiring stack) on the substrate (Fig. 1A, 140, substrate layers), the circuit element layer stack (Fig. 1A, 100, multilayer wiring stack) comprising a plurality of circuit elements (Figs. 1A-1B, 12, one or more circuit elements (12a/12b/12c/12d; qubit readout resonator/filter/wiring lines/capacitive coupling element), [0045], [0050]) distributed across a plurality of layers (Fig. 1A, 130, wiring layers), and
a coherent device layer (Fig. 1A, 16, capping layer) on the circuit element layer stack (Figs. 1A-1B, 12, one or more circuit elements (12a/12b/12c/12d; qubit readout resonator/filter/wiring lines/capacitive coupling element), [0045], [0050]) in the plurality of layers (Fig. 1A, 130, wiring layers), wherein the coherent device layer (Fig. 1A, 16, capping layer) comprises monocrystalline silicon (Fig. 1A, 16, capping layer is formed from a low-loss dielectric material such mono-crystalline silicon, [0048]); and
JEFFREY does not explicitly disclose a method comprising: a sacrificial material filling a space between the plurality of circuit elements in the plurality of layers, and removing the sacrificial material.
ROMANKIW teaches in Figures 2C-2D, a method (processes useful for both thin film packages and multi-chip modules (MCM), [Col. 5, Line 1-5]) comprising:
a sacrificial material (Figs. 2C/2D/4C, 10/11, conductor level dielectric/via level dielectric, Col. 7, Lines 30-45) filling a space (annotated Figures 2C/2D) between the plurality of circuit elements (Figs. 2C/2D, 6, wiring, 9, conductive vias) in the plurality of layers (annotated Figures 2C/2D), and
removing the sacrificial material (annotated Figures 2C-2D, Step 10, [Col. 9, Lines 4-10).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have as modified JEFFREY to incorporate the teachings of ROMANKIW, such that a method comprising: a sacrificial material filling a space between the plurality of circuit elements in the plurality of layers, and removing the sacrificial material, so that resulting in a hollow structure having an overall dielectric constant about equal to 1, which is the ideal and closer to the value of air or vacuum (ROMANKIW, [Col 1, Lines 40-45], [Col. 11, Lines 10-15]).
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Regarding Claim 2, JEFFREY as modified by ROMANKIW teaches the method of claim 1.
JEFFREY further teaches, the method (Figs. 3A-3F, manufacturing process of a quantum computing device, [0040]) comprising:
bonding the first chip (Fig. 2A, 22, carrier chip) to a second chip (Fig. 2A, 24, qubit chip) in a flip-chip configuration, such that the coherent device layer (Figs. 1A/2A, 16, capping layer) faces the second chip (Fig. 2A, 24, qubit chip).
Regarding Claim 3, JEFFREY as modified by ROMANKIW teaches the method of claim 2.
ROMANKIW further teaches in Figures 2C-2D, the method (processes useful for both thin film packages and multi-chip modules (MCM), [Col. 5, Line 1-5]), wherein the first chip (Figs. 2C/2D, Si Chip) is bonded to the second chip (Figs. 2C/2D, package of chip carrier) at a bond point (Figs. 2C/2D, C4 or wire bonding, [Col. 4, Lines 50-55]), and
wherein the circuit element layer stack (annotated Figures 2C/2D) comprises a first mechanical support structure (Figs. 2C/2D, 7, Cu support stud, [Col. 7, Lines 15-25]) aligned with the bond point (Figs. 2C/2D, C4 or wire bonding, [Col. 4, Lines 50-55]), the first mechanical support structure (Figs. 2C/2D, 7, Cu support stud, [Col. 7, Lines 15-25]) extending vertically (annotated Figures 2C/2D) through two or more layers (plurality of layers, annotated Figure 2C) of the circuit element layer stack (annotated Figures 2C/2D).
Regarding Claim 4, JEFFREY as modified by ROMANKIW teaches the method of claim 3.
ROMANKIW further teaches in Figures 2C-2D, the method (processes useful for both thin film packages and multi-chip modules (MCM), [Col. 5, Line 1-5]), wherein the circuit element layer stack (annotated Figures 2C/2D) comprises a second mechanical support structure (dummy stud or dummy columns, [Col. 5, Lines 15-20]; Example 2, Step 9: fabrication of dummy studs, [Col. 9, Lines 45-55]; “dummy” support studs to form a second wiring level, [Col. 13, Lines 1-10]) extending vertically (annotated Figures 2C/2D) through two or more layers (plurality of layers, annotated Figure 2C) of the circuit element layer stack (annotated Figures 2C/2D),
wherein the second mechanical support structure (dummy stud or dummy columns, [Col. 5, Lines 15-20]; Example 2, Step 9: fabrication of dummy studs, [Col. 9, Lines 45-55]; “dummy” support studs to form a second wiring level, [Col. 13, Lines 1-10]) is not aligned with any bond point (“dummy columns strategically placed uniformly throughout the chip and in the chip periphery, [Col. 5, Lines 15-25]) between the first chip (Figs. 2C/2D, Si Chip) and the second chip (Figs. 2C/2D, package of chip carrier), and
wherein the first mechanical support (Figs. 2C/2D, 7, Cu support stud, [Col. 7, Lines 15-25]) structure is wider than (annotated Figures 2C/2D) the second mechanical support structure (dummy stud or dummy columns, [Col. 5, Lines 15-20]; Example 2, Step 9: fabrication of dummy studs, [Col. 9, Lines 45-55]; “dummy” support studs to form a second wiring level, [Col. 13, Lines 1-10]).
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Regarding Claim 5, JEFFREY as modified by ROMANKIW teaches the method of claim 2.
JEFFREY further teaches, the method (Figs. 3A-3F, manufacturing process of a quantum computing device, [0040]), wherein the first chip (Fig. 2A, 22, carrier chip) comprises a qubit control element or a qubit readout element (Fig. 1B, 12a, qubit readout resonator, [0050]) on the coherent device layer (Figs. 1A/2A, 16, capping layer), and
wherein the second chip comprises a qubit configured (Fig. 2A, 24, qubit chip, [0054]) to couple to the qubit control element or the qubit readout element (Figs. 1B/2B, 12a/28, qubit readout resonator/qubit circuit elements, [0050]).
Regarding Claim 18, JEFFREY as modified by ROMANKIW teaches the method of claim 1.
ROMANKIW further teaches in Figures 2C-2D, the method (processes useful for both thin film packages and multi-chip modules (MCM), [Col. 5, Line 1-5]), wherein removing the sacrificial material comprises (Figs. 2C/2D, 10/11, conductor level dielectric/via level dielectric) selectively etching the sacrificial material using a wet-chemical etch or a gaseous etch (Example 1, Step 9, [Col. 9, Lines 1-10]).
Regarding Claim 19, JEFFREY as modified by ROMANKIW teaches the method of claim 1.
ROMANKIW further teaches in Figures 2C-2D, the method (processes useful for both thin film packages and multi-chip modules (MCM), [Col. 5, Line 1-5]), wherein the plurality of circuit elements (Figs. 2B6, layers/wiring elements/qubit readout element/qubit control elements, 230/604/606/608/610) comprise superconductor wiring ([0052], [0074]).
Regarding Claim 20, JEFFREY as modified by ROMANKIW teaches the method of claim 1.
ROMANKIW further teaches in Figures 2C-2D, the method (processes useful for both thin film packages and multi-chip modules (MCM), [Col. 5, Line 1-5]), wherein the sacrificial material is an oxide, a nitride, or an oxynitride (temporary (aka sacrificial) dielectrics, [SiO2, Col. 8, Lines 1-10]).
Regarding Claim 21, JEFFREY as modified by ROMANKIW teaches the method of claim 1.
JEFFREY further teaches, the method (Figs. 3A-3F, manufacturing process of a quantum computing device, [0040]), wherein the coherent device layer (Figs. 1A/2A, 16, capping layer) has a dielectric loss tangent for microwave frequencies of less than 10-5 ([0048]).
Regarding Claim 22, JEFFREY as modified by ROMANKIW teaches the method of claim 1.
ROMANKIW further teaches in Figures 2C-2D, the method (processes useful for both thin film packages and multi-chip modules (MCM), [Col. 5, Line 1-5]), wherein the circuit element layer stack (annotated Figure 2D) comprises a thermalization structure composed of one or more non-superconductor metals (Fig. 2D, Cu support stud, a non-superconductor metal, [Col. 6, Lines 1-10]).
Regarding Claim 28, JEFFREY as modified by ROMANKIW teaches the method of claim 1.
JEFFREY further teaches, the method (Figs. 3A-3F, manufacturing process of a quantum computing device, [0040]), wherein the coherent device layer has a thickness in a range from 1 µm to 30 µm ([0017]).
Regarding Claim 29, JEFFREY as modified by ROMANKIW teaches the method of claim 28.
JEFFREY further teaches, the method (Figs. 3A-3F, manufacturing process of a quantum computing device, [0040]), wherein the thickness of the coherent device layer is in a range from 5 µm to 20 µm ([0017]).
Claim(s) 6-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over JEFFREY, in view of ROMANKIW, and further in view of Eric Peter Lewandowski et al, (hereinafter LEWANDOWSKI), US 20220020715 A1.
Regarding Claim 6, JEFFREY as modified by ROMANKIW teaches the method of claim 1.
ROMANKIW further teaches in Figures 2C-2D, the method (processes useful for both thin film packages and multi-chip modules (MCM), [Col. 5, Line 1-5]), wherein the circuit element layer stack (annotated Figures 2C/2D) comprises a mechanical support structure (Figs. 2C/2D, 7, Cu support stud, [Col. 7, Lines 15-25]) extending vertically (annotated Figures 2C/2D) through two or more layers (annotated Figures 2C/2D) of the circuit element layer stack (annotated Figures 2C/2D),
JEFFREY as modified by ROMANKIW does not explicitly disclose a method of claim 1, wherein the mechanical support structure has a lateral dimension between 5 µm and 60 µm.
LEWANDOWSKI teaches in Figure 16, a method of claim 1, wherein the mechanical support structure (Fig. 16, 608/1610, solder pillars) has a lateral dimension between 5 µm and 60 µm (the dimensions and/or geometries of pillar structures fabricated…although metal shadow…the lateral dimensions of the structures to around only 100 µm, [0029]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have JEFFREY as modified by ROMANKIW to incorporate the teachings of LEWANDOWSKI, such that a method of claim 1, wherein the mechanical support structure has a lateral dimension between 5 µm and 60 µm. For instance, the lateral dimensions of the solder pillars around 100 µm can therefore cause a spatially-uniform and/or even spatially-even gap be maintained between the qubit chip and the interposer chip (LEWANDOWSKI, [0041-0042]).
Regarding Claim 7, JEFFREY as modified by ROMANKIW and LEWANDOWSKI, teaches, the method of claim 6,
ROMANKIW further teaches in Figures 2C-2D, the method (processes useful for both thin film packages and multi-chip modules (MCM), [Col. 5, Line 1-5]) of claim 6, wherein the mechanical support structure (Figs. 2C/2D, 7, Cu support stud, [Col. 7, Lines 15-25]); (dummy stud or dummy columns, [Col. 5, Lines 15-20]; Example 2, Step 9: fabrication of dummy studs, [Col. 9, Lines 45-55]; “dummy” support studs to form a second wiring level, [Col. 13, Lines 1-10]) extends from a surface of the substrate (annotated Figures 2C/2D).
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Regarding Claim 8, JEFFREY as modified by ROMANKIW and LEWANDOWSKI, teaches, the method of claim 7,
ROMANKIW further teaches in Figures 2C-2D, the method (processes useful for both thin film packages and multi-chip modules (MCM), [Col. 5, Line 1-5]) of claim 6, wherein the mechanical support structure (Figs. 2C/2D, 7, Cu support stud, [Col. 7, Lines 15-25]); (dummy stud or dummy columns, [Col. 5, Lines 15-20]; Example 2, Step 9: fabrication of dummy studs, [Col. 9, Lines 45-55]; “dummy” support studs to form a second wiring level, [Col. 13, Lines 1-10]) extends from the surface of the substrate (annotated Figures 2C/2D) to the coherent device layer (Figs. 1A/2C-2D, 8, the top layer; a final cover layer of SiO2 with imbedded top surface, [Col. 5, Lines 35-40]; Step 8: “a cover layer of SiO2 is applied and planarized”, [Col. 9, Lines 45-50]).
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Regarding Claim 9, JEFFREY as modified by ROMANKIW and LEWANDOWSKI, teaches, the method of claim 7,
ROMANKIW further teaches in Figures 2C-2D, the method (processes useful for both thin film packages and multi-chip modules (MCM), [Col. 5, Line 1-5]) of claim 6, wherein the plurality of circuit elements (Figs. 2C/2D, 6, wiring, 9, conductive vias) comprise a first circuit element (annotated Figures 2C/2D) in a layer of the circuit element layer stack (annotated Figures 2C/2D) immediately below the coherent device layer (Figs. 1A/2C-2D, 8, the top layer; a final cover layer of SiO2 with imbedded top surface, [Col. 5, Lines 35-40]; Step 8: “a cover layer of SiO2 is applied and planarized”, [Col. 9, Lines 45-50]), and
wherein the mechanical support structure (Figs. 2C/2D, 7, Cu support stud, [Col. 7, Lines 15-25]); (dummy stud or dummy columns, [Col. 5, Lines 15-20]; Example 2, Step 9: fabrication of dummy studs, [Col. 9, Lines 45-55]; “dummy” support studs to form a second wiring level, [Col. 13, Lines 1-10]) extends from the surface of the substrate (annotated Figures 2C/2D) to the first circuit element (annotated Figures 2C/2D).
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Regarding Claim 10, JEFFREY as modified by ROMANKIW and LEWANDOWSKI, teaches, the method of claim 6,
ROMANKIW further teaches in Figures 2C-2D, the method (processes useful for both thin film packages and multi-chip modules (MCM), [Col. 5, Line 1-5]) of claim 6, wherein the mechanical support structure (Figs. 2C/2D, 7, Cu support stud, [Col. 7, Lines 15-25]); (dummy stud or dummy columns, [Col. 5, Lines 15-20]; Example 2, Step 9: fabrication of dummy studs, [Col. 9, Lines 45-55]; “dummy” support studs to form a second wiring level, [Col. 13, Lines 1-10]) is a single column extending vertically (annotated Figure 2, vertical direction) through the two or more layers (annotated Figures 2C/2D).
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Regarding Claim 11, JEFFREY as modified by ROMANKIW and LEWANDOWSKI, teaches, the method of claim 6,
ROMANKIW further teaches in Figures 2C-2D, the method (processes useful for both thin film packages and multi-chip modules (MCM), [Col. 5, Line 1-5]) of claim 6, wherein the mechanical support structure (Figs. 2C/2D, 7, Cu support stud, [Col. 7, Lines 15-25]); (dummy stud or dummy columns, [Col. 5, Lines 15-20]; Example 2, Step 9: fabrication of dummy studs, [Col. 9, Lines 45-55]; “dummy” support studs to form a second wiring level, [Col. 13, Lines 1-10]) is composed of a dielectric material (DLC and SiO2 can alternatively function as supports in places where it required that the supports not be electrically conductive, [Col. 6, Lines1-10]).
Claim(s) 13, 15 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over JEFFREY, in view of ROMANKIW, and further in view of Stephen George et al, (hereinafter GEORGE), US 20070275502 A1.
Regarding Claim 13, JEFFREY as modified by ROMANKIW teaches, the method of claim 1,
JEFFREY further teaches, the method (Figs. 3A-3F, manufacturing process of a quantum computing device, [0040]), wherein providing the first chip (Fig. 1A, 10, carrier chip) comprises forming a passivation layer (Fig. 1A, 120, dielectric layers) on one or more surfaces of the plurality of circuit elements (Figs. 1A-1B, 12, one or more circuit elements (12a/12b/12c/12d; qubit readout resonator/filter/wiring lines/capacitive coupling element), [0045], [0050]), the passivation layer (Fig. 1A, 120, dielectric layers) internal to the circuit element layer stack (Fig. 1A, 100, multilayer wiring stack) and between the coherent device layer (Fig. 1A, 16, capping layer) and the substrate (Fig. 1A, 140, substrate layers).
Though JEFFREY teaches the dielectric layers but not referred them as passivation layer, JEFFREY as modified by ROMANKIW does not explicitly disclose a method of claim 1, wherein providing the first chip comprises forming a passivation layer on one or more surfaces of the plurality of circuit elements.
GEORGE teaches in Figure 1, a method (Fig. 1, 100, packaging method) of claim 1, wherein providing the first chip (Figs. 7A-7B, 200, wafer substrate segment) comprises forming a passivation layer (Fig. 1, Step 106, depositing the cover layer; Figs. 7A-7B, 216, cover layer) on one or more surfaces of the plurality of circuit elements (Figs. 7A-7B, 201, device elements, [0043], [0048]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have JEFFREY as modified by ROMANKIW to incorporate the teachings of GEORGE, such that a method of claim 1, wherein providing the first chip comprises forming a passivation layer on one or more surfaces of the plurality of circuit elements, so that the cover layer (216) is applied over the sacrificial structure (212) , the cover layer fills the sacrificial sublayer openings (see Fig. 6B) to create cover layer support elements (218) (GEORGE, Figs. 6B/7A-7B, [0068]).
Regarding Claim 15, JEFFREY as modified by ROMANKIW and GEORGE teaches in a method of claim 13.
GEORGE further teaches in Figure 1, a method (Fig. 1, 100, packaging method), wherein the passivation layer (Fig. 1, Step 106, depositing the cover layer; Figs. 7A-7B, 216, cover layer) comprises an organic material (the cover layer (26) can be made from any suitable photoresist material, “e.g. SU-8”, [0066]).
Regarding Claim 17, JEFFREY as modified by ROMANKIW and GEORGE teaches in a method of claim 13.
GEORGE further teaches in Figure 1, a method (Fig. 1, 100, packaging method), wherein the passivation layer is formed (Fig. 1, Step 106, depositing the cover layer; Figs. 7A-7B, 216, cover layer) prior (Fig. 1, Step 106 is prior to Step 110) to removing (Fig. 1, Step 110, removing sacrificial structure) to removing the sacrificial material (Fig. 6B, sacrificial sublayer, 204 is preferably a polymer release layer, e.g. PiRL, [0052]), and wherein the method comprises:
subsequent to removing the sacrificial material, removing the passivation layer (Figs. 9A-9B, unexposed portions for the cover layer and the sacrificial structure have been dissolved and washed away, [0033-0034]).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over JEFFREY, in view of ROMANKIW, further in view of GEORGE, and further in view of William D. Oliver et al, (hereinafter OLIVER), US 20180013052 A1.
Regarding Claim 14, JEFFREY as modified by ROMANKIW and GEORGE teaches in a method of claim 13.
GEORGE further teaches in Figure 1, a method (Fig. 1, 100, packaging method), wherein the passivation layer is formed (Fig. 1, Step 106, depositing the cover layer; Figs. 7A-7B, 216, cover layer) prior (Fig. 1, Step 106 is prior to Step 110) to removing (Fig. 1, Step 110, removing sacrificial structure) the sacrificial material (Fig. 6B, sacrificial sublayer, 204 is preferably a polymer release layer, e.g. PiRL, [0052]).
JEFFREY as modified by ROMANKIW and GEORGE does not teach a method, wherein the passivation layer comprises a noble metal.
OLIVER teaches in Figure 8B, a method (Fig. 3, method for fabricating a superconducting resonator, [0014]) of claim 13, wherein the passivation layer comprises a noble metal (Fig. 8B, 142/144, A UBM may adhere well both the underlying superconducting circuit’s passivation layer, hermetically sealing the superconducting circuits from the environment; UBM may be provide include, but are not limited to Pt, Pd, Au etc. [0128], [0202]). [Note: Pt, Pd, and Au are some of the noble metal as cited in Wikipedia: https://en.wikipedia.org/wiki/Noble_metal]. Figure 8B of the OLIVER art and the Figure 5A of the Instant Application are compared below to show the passivation layer and interconnect transmission lines.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have JEFFREY as modified by ROMANKIW and GEORGE to incorporate the teachings of OLIVER, such that a method of claim 13, wherein the passivation layer comprises a noble metal such as Pt, Pd and/or Au, so that a UBM adhered passivation layer, hermetically sealing the underlying superconducting pad and the superconducting circuits from the environment (OLIVER, [00=128]).
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Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over JEFFREY, in view of ROMANKIW, further in view of GEORGE, further in view of Xibin Wang et al, (hereinafter WANG), NPL Reference: Appl Phys A, 113, 195-200 (2013), and further in view of Hiroyuki KAWASHIMA, (hereinafter KAWASHIMA), US 20190181168 A1.
Regarding Claim 16, JEFFREY as modified by ROMANKIW and GEORGE teaches in a method of claim 15.
GEORGE further teaches in Figure 1, a method (Fig. 1, 100, packaging method), wherein the passivation layer (Fig. 1, Step 106, depositing the cover layer; Figs. 7A-7B, 216, cover layer) is formed by deposition subsequent to removing (Fig. 1, Step 106 followed by Step 110; [0066]) the sacrificial material (Fig. 6B, sacrificial sublayer, 204 is preferably a polymer release layer, e.g. PiRL, [0052]).
JEFFREY as modified by ROMANKIW and GEORGE does not explicitly disclose a method of claim 15, wherein the organic material is a low-loss organic material.
WANG teaches a method (Fig. 2, fabrication process for SU-8-ridge waveguide using ICP etching), wherein the organic material (Fig. 1, SU-8 2005, polymer) is a low-loss (Fig. 10, measured propagation loss in the fabricated SU-8 ridge waveguides, Section 3.2, the propagation loss, obtained from the slow are less than 1.565 dB/cm for the dry etching SU-8 ridge waveguide and 1.541 dB/cm for wet etching SU-8 ridge waveguide) organic material (Fig. 1, SU-8 2005, polymer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have JEFFREY as modified by ROMANKIW and GEORGE to incorporate the teachings of WANG, such that method of claim 15, wherein the organic material is a low-loss organic material, so that one can fabricate low-lose ridge SU-8 waveguides for the large-core single mode device having low scattering loss and then the propagation loss (WANG, Fig 10, Conclusion section).
JEFFREY as modified by ROMANKIW and GEORGE and WANG does not explicitly disclose a method, wherein the passivation layer is formed by vapor deposition.
KAWASHIMA teaches in Figure 2, a method (Figs. 4-10, method of manufacturing the semiconductor device, [0018-0024]) of claim 15, wherein the passivation layer (Fig. 2, 540, protective layer, [0073]) is formed by vapor deposition (protective layer, 540 can be formed by introducing a raw material gas into the gap, 530…and performing…deposition, [0074]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have JEFFREY as modified by ROMANKIW and GEORGE to incorporate the teachings of KAWASHIMA, such that method of claim 15, wherein the passivation layer is formed by vapor deposition, so that the protective layer (540) can improve reliability of the wirings by preventing electromigration and time dependent breakdown (TDDB) in wiring-layers (300) and the through-vias (400) (KAWASHIMA, [0074]).
Claim(s) 30-31 is/are rejected under 35 U.S.C. 103 as being unpatentable over JEFFREY, in view of ROMANKIW, further in view of LEWANDOWSKI), and further in view of Theodore Charles White, (hereinafter WHITE), US 20190229094 A1.
Regarding Claim 30, JEFFREY as modified by ROMANKIW and LEWANDOWSKI, teaches, the method of claim 6,
JEFFREY as modified by ROMANKIW and LEWANDOWSKI the method, wherein the mechanical support structure is composed of polysilicon or amorphous silicon.
WHITE teaches the method (Fig. 1, 100, method of manufacturing the device, [0018]), wherein the mechanical support structure is composed of polysilicon or amorphous silicon ([0032]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have JEFFREY as modified by ROMANKIW to incorporate the teachings of WHITE, such that a method comprising: wherein the mechanical support structure is composed of polysilicon or amorphous silicon, so that the deposited dielectrics, typically have high loss and are suitable for high coherence/low decoherence superconducting quantum circuits (WHITE, [0032]).
Regarding Claim 31, JEFFREY as modified by ROMANKIW, LEWANDOWSKI, and WHITE teaches, the method of claim 6.
WHITE further teaches the method (Fig. 1, 100, method of manufacturing the device, [0018]), wherein the mechanical support structure is composed of a superconductor material ([0037]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
CN 108390153 A – [0078]
STATEMENT OF RELEVANCE – The dielectric resonator (2) is a square ceramic dielectric resonator with a dielectric constant ε r1 =16 and a dielectric loss tangent tanδ=1.5×10-4, where the dielectric loss tangent represents the dielectric material.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2812 /CHRISTINE S. KIM/ Supervisory Patent Examiner, Art Unit 2812