CTNF 18/080,721 CTNF 89973 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions 08-25-01 AIA Applicant’s election without traverse of Invention I, claims 1-17 in the reply filed on 04/14/2026 is acknowledged. 08-06 AIA Claim s 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention , there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 04/14/2026 . Claim Objections 07-29-01 AIA Claim 1 is objected to because of the following informalities: antecedent basis. The limitation in line 2, “phase change material” should be a phase change material . Appropriate correction is required. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim s 1, 10, 13-15, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et. al., U.S. Pat. 8,138,574, hereafter Chen, in view of Hekmatshoartabari et. al., U.S. Pat. Pub. 2023/0123050, hereafter ‘050 . Regarding claim 1, Chen discloses (Figs 1-6, Col. 1, line 65 – Col.2, line 3) A memory cell, comprising: a memory device comprising phase change material [211]; and a selector device [202] the selector device comprising a BJT circuit device. Chen fails to explicitly disclose the BJT circuit device comprising: a lateral bipolar junction transistor including an intrinsic base, an extrinsic base, a collector region and an emitter region, the collector region of the lateral bipolar junction transistor being electrically connected to the memory device; a vertical bipolar junction transistor, the extrinsic base of the lateral bipolar junction transistor comprising a collector region of the vertical bipolar junction transistor; one of the lateral bipolar junction transistor and the vertical bipolar junction transistor being a PNP transistor, the other of the lateral bipolar junction transistor and the vertical bipolar junction transistor being an NPN transistor, the lateral bipolar junction transistor and the vertical bipolar junction transistor comprising a Sziklai Darlington transistor pair. However, ‘050 discloses (Figs. 37, 44, see also Figs. 1-36) the BJT circuit device comprising: a lateral bipolar junction transistor (pars. [0007], [0075], [0113]) including an intrinsic base [550], an extrinsic base [350], a collector region [654], and an emitter region [652]; a vertical bipolar junction transistor (pars. [0008], [0073], [0075]), the extrinsic base [350] of the lateral bipolar junction transistor comprising a collector region [350] of the vertical bipolar junction transistor (par. [0075]); one of the lateral bipolar junction transistor and the vertical bipolar junction transistor being a PNP transistor, the other of the lateral bipolar junction transistor and the vertical bipolar junction transistor being an NPN transistor, the lateral bipolar junction transistor and the vertical bipolar junction transistor comprising a Sziklai Darlington transistor pair (Figs. 37, 44; pars [0078], [0220]). The limitation “the collector region of the lateral bipolar junction transistor being electrically connected to the memory device” is satisfied when the BJT of PCRAM of Chen is modified by Sziklai Darlington transistor pair of ‘050 as a selector device, because the output of the Sziklai Darlington transistor pair which is the collector region [654] of the lateral/amplifying BJT would be electrically connected to the phase change memory device [211] of Chen. It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to replace BJT selector of Chen with Sziklai Darlington transistor pair of ‘050 to increase selector current gain and provide improved programming current capability for the PCM of Chen. Regarding claim 10, Chen in view of ‘050 discloses everything as applied above. ‘050 further discloses (Fig. 37, see also Figs 1-36, par. [0020]) wherein the vertical bipolar junction transistor comprises an emitter [2950], further including a metal contact [3756] (par. [0199]) extending from the emitter [2950] of the vertical bipolar junction transistor, the metal contact being electrically connected to the emitter [2950] of the vertical bipolar junction transistor and the collector [654] of the lateral bipolar junction transistor (see Fig.37, electrical connection goes through the device, the collector has a separate contact [3758]). Regarding claim 13, Chen discloses a memory cell, comprising (Figs 1-6, Col. 1, line 65 – Col.2, line 3): a memory device [211] (Fig. 4), the memory device comprising a phase change memory device or a resistive random access memory device; and a selector device [202], the selector device comprising a BJT circuit device. Chen fails to explicitly disclose the BJT circuit device comprising a lateral bipolar junction transistor and a vertical bipolar junction transistor configured as a Sziklai Darlington transistor pair, the lateral bipolar junction transistor comprising a collector region, the collector region of the lateral bipolar junction transistor being electrically connected to the memory device. However, ‘050 discloses The BJT circuit device comprising (Fig. 37) a lateral bipolar junction transistor [652], [550], [654]and a vertical bipolar junction transistor [2950],[1650], [350 configured as a Sziklai Darlington transistor pair (par. [0078], [0220]), the lateral bipolar junction transistor comprising a collector region [654] The limitation “the collector region of the lateral bipolar junction transistor being electrically connected to the memory device” is satisfied when the BJT of PCRAM of Chen is modified by Sziklai Darlington transistor pair of ‘050 as a selector device, because the output of the Sziklai Darlington transistor pair which is the collector region [654] of the lateral/amplifying BJT would be electrically connected to the phase change memory device [211] of Chen. It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to replace BJT selector of Chen with Sziklai Darlington transistor pair of ‘050 to increase selector current gain and provide improved programming current capability for the PCM of Chen. Regarding claim 14, Chen in view of ‘050 discloses everything as applied above. Chen further discloses (Figs 1-6, Col. 1, line 65 – Col.2, line 3) wherein the memory device [211] (Fig. 2) is a phase change memory device. Regarding claim 15, Chen in view of ‘050 discloses everything as applied above. ‘050 further discloses (Fig. 37) wherein the lateral bipolar junction transistor comprises an extrinsic base [350], the extrinsic base [350] of the lateral bipolar junction transistor comprising a collector region [350] of the vertical bipolar junction transistor (par. [0075]) Regarding claim 17, Chen method of fabricating a memory cell, comprising: forming a BJT selector. Chen fails to explicitly disclose forming a Sziklai Darlington transistor pair including a lateral bipolar junction transistor and a vertical bipolar junction transistor atop the lateral bipolar junction transistor, the lateral bipolar junction transistor comprising an emitter region, a collector region, an intrinsic base region, and an extrinsic base region adjoining the intrinsic base region, wherein the extrinsic base region of the lateral bipolar junction transistor comprises a collector region of the vertical bipolar junction transistor; and forming a memory device electrically connected to the collector region of the lateral bipolar junction transistor. However, ‘050 discloses (Figs 1-37) forming a Sziklai Darlington transistor pair (par. [0078],[0220]) including a lateral bipolar junction transistor [652],[550],[654] and a vertical bipolar junction transistor [2950],[1650],[350] atop the lateral bipolar junction transistor, the lateral bipolar junction transistor comprising an emitter region [652], a collector region [654], an intrinsic base region [550], and an extrinsic base region [350] adjoining the intrinsic base region [550], wherein the extrinsic base region [350] of the lateral bipolar junction transistor comprises a collector region [350] of the vertical bipolar junction transistor (par. [0075] and Fig. 37). forming a memory device electrically connected to the collector region of the lateral bipolar junction transistor. It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to replace BJT selector of Chen with Sziklai Darlington transistor pair of ‘050 to increase selector current gain and provide improved programming current capability for the PCM of Chen . 07-21-aia AIA Claim s 2-3 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et. al., U.S. Pat. 8,138,574, hereafter Chen, in view of in view of Hekmatshoartabari et. al., U.S. Pat. Pub. 2023/0123050, hereafter ‘050, and further in view of Examiner’s Official Notice, hereafter ON . Regarding claim 2, Chen in view of ‘050 discloses everything as applied above. Chen in view of ‘050 fails to explicitly disclose wherein the memory device comprises a bottom electrode, a top electrode, the phase change material being positioned between the bottom electrode and the top electrode, the bottom electrode being electrically connected to the collector region of the lateral bipolar junction transistor. However, the Examiner takes an Official Notice that a typical phase change memory element has a bottom electrode, a top electrode, and a phase change material between said electrodes. It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to modify Chen in view of ‘050 with the electrodes provided by the Official Notice because said electrodes facilitate inclusion of the memory device (element) in the memory. The limitation “the bottom electrode being electrically connected to the collector region of the lateral bipolar junction transistor would be satisfied when the BJT of PCRAM of Chen is modified by Sziklai Darlington transistor pair of ‘050 as a selector device, because the output of the Sziklai Darlington transistor pair which is the collector region [654] of the lateral/amplifying BJT would be electrically connected to the phase change memory device [211] of Chen. It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to replace BJT selector of Chen with Sziklai Darlington transistor pair of ‘050 to increase selector current gain and provide improved programming current capability for the PCM of Chen. Regarding claim 3, Chen in view of ‘050 in view of ON discloses everything as applied above. Chen further discloses further including an interlevel dielectric layer [204], at least a portion of the BJT [202] being encased within the interlevel dielectric layer [204]. Similarly, ‘050 directly teaches (Figs 36, 37) further including an interlevel dielectric layer [3150], at least a portion of the vertical bipolar junction transistor [350], [1650], [2950] being encased within the interlevel dielectric layer [3150]. It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to encase the Sziklai Darlington transistor pair in the interlevel dielectric layer of Chen to protect the transistor pair from elements. Regarding claim 9, Chen in view of ‘050 in view of ON discloses everything as applied above. Chen further discloses (Fig. 2) further including a vertical contact opening [201] extending through the interlevel dielectric layer [204], the memory device [211] being positioned within the vertical contact opening [201] (the memory stack can be regarded as a continuation of the vertical contact opening [201]) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 4-8, 11-12, and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: the prior art of record fails to explicitly disclose or make obvious the limitations of claims 4, 11, and 16 . Claims 5-8 and 12 are dependent claims which contain all limitations of claims 4 and 11 . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. JP-2595780 teaches (e.g., Figs 4, 7) a Sziklai Darlington transistor pair a circuit device comprising (Figs 4,7) a first bipolar junction transistor [3], [4], [5]and a vertical bipolar junction transistor [7],[8], [9] configured as a Sziklai Darlington transistor pair (Fig. 7), the bipolar junction transistor comprising a collector region [3], and intrinsic and extrinsic base [4], depending on location of the layer between emitter [5] and collector [3], layer [6] of the vertical transistor can be thought of as comprising both a collector and an extrinsic base. However, both BJTs are vertical transistors. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR V BARZYKIN whose telephone number is (571)272-0508. The examiner can normally be reached Monday-Friday, 9am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRITT HANLEY can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VICTOR V BARZYKIN/Examiner, Art Unit 2893 /Britt Hanley/Supervisory Patent Examiner, Art Unit 2893 Application/Control Number: 18/080,721 Page 2 Art Unit: 2893 Application/Control Number: 18/080,721 Page 3 Art Unit: 2893 Application/Control Number: 18/080,721 Page 4 Art Unit: 2893 Application/Control Number: 18/080,721 Page 5 Art Unit: 2893 Application/Control Number: 18/080,721 Page 6 Art Unit: 2893 Application/Control Number: 18/080,721 Page 7 Art Unit: 2893 Application/Control Number: 18/080,721 Page 8 Art Unit: 2893 Application/Control Number: 18/080,721 Page 9 Art Unit: 2893
Prosecution Insights