Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/18/2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4 and 7-9 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Huang (Pub. No.: US 2024/0347598).
Re claim 1, Huang teaches a semiconductor structure, comprising:
a frontside source/drain region (260, FIG. 5B, ¶ [0016]); and
a dielectric stack (247/352) disposed on (indirectly) a bottom surface of the frontside source/drain region;
wherein the dielectric stack comprises a first dielectric layer (247) having vertical sidewalls and a bottom surface disposed within a second dielectric layer (352, ¶ [0027]).
Re claim 2, Huang teaches the semiconductor structure of claim 1, further comprising a backside power rail (273) disposed on the dielectric stack (247/269) and separated from the frontside source/drain region.
Re claim 3, Huang teaches the semiconductor structure of claim 2, further comprising a via-to-backside power rail (275) connected to the backside power rail (273).
Re claim 4, Huang teaches the semiconductor structure of claim 3, wherein the backside power rail (273) is connected to the via-to-backside power rail (275) from a backside of the semiconductor structure.
Re claim 7, Huang teaches the semiconductor structure of claim 2, further comprising a frontside source/drain contact (280 of FIG. 10E, [0040]) disposed on the frontside source/drain region (260), wherein the frontside source/drain contact is connected to the backside power rail (275) by a via-to-backside power rail (273).
Re claim 8, Huang teaches the semiconductor structure of claim 1, which is part of a backside power delivery network (273/275/358).
Re claim 9, Huang, FIG. 5E teaches the semiconductor structure of claim 1, wherein the first dielectric layer comprises a first dielectric material (247, [0026], said with silicon oxide material) and the second dielectric layer (352, [0027], said with SiOCN material) comprises a second dielectric material different from the first dielectric material.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-9 and 16-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over another Huang (Pub. No.: US 2022/0375860) (hereinafter `860) in view of Huang.
Re claim 1, `860, Figs. 1D-1E teaches a semiconductor structure, comprising:
a frontside source/drain region (108/110, ¶ [0016]); and
a dielectric stack (104/122, [0023]/[0059]) disposed on a bottom surface of the frontside source/drain region;
wherein the dielectric stack comprises a first dielectric layer (104) disposed on a top surface of a second dielectric layer (122).
`860 fails to teach wherein the dielectric stack comprises a first dielectric layer having vertical sidewalls and a bottom surface disposed within a second dielectric layer.
Huang teaches wherein the dielectric stack comprises a first dielectric layer (247, FIG. 5B) having vertical sidewalls and a bottom surface disposed within a second dielectric layer (352, ¶ [0027])
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of forming the backside of an IC with reduced resistance as taught by Huang, [0002].
Re claim 2, `860 teaches the semiconductor structure of claim 1, further comprising a backside power rail (118) disposed on the dielectric stack (104/122) and separated from the frontside source/drain region (108/110).
Re claim 3, `860 teaches the semiconductor structure of claim 2, further comprising a via-to-backside power rail (106) connected to the backside power rail (118).
Re claim 4, `860 teaches the semiconductor structure of claim 3, wherein the backside power rail (118) is connected to the via-to-backside power rail (106) from a backside of the semiconductor structure.
Re claim 5, `860, Figs. 1D-1E teaches the semiconductor structure of claim 3, wherein the via-to-backside power rail comprises a lower portion (152/120) located on the backside power rail and an upper portion (106) located on a sidewall of the frontside source/drain region.
Re claim 6, `860, Figs. 1D-1E teaches the semiconductor structure of claim 5, wherein the lower portion of the via- to-backside power rail comprises a step-wise configuration (152/120).
Re claim 7, `860 teaches the semiconductor structure of claim 2, further comprising a frontside source/drain contact (116) disposed on the frontside source/drain region (108/110), wherein the frontside source/drain contact is connected to the backside power rail (118) by a via-to-backside power rail (106).
Re claim 8, `860 teaches the semiconductor structure of claim 1, which is part of a backside power delivery network (106/152/120/118).
Re claim 9, `860, Figs. 1D-1E teaches the semiconductor structure of claim 1, wherein the first dielectric layer comprises a first dielectric material (104, [0023]) and the second dielectric layer (270) comprises a second dielectric material (122, [0059]) different from the first dielectric material.
Re claim 15, `860, Figs. 1D-1E teaches a semiconductor structure, comprising:
a first dielectric stack (104/122) disposed on a bottom surface of a first frontside source/drain region;
a first frontside source/drain contact (116) disposed on a top surface of the first frontside source/drain region;
a backside power rail (118) disposed on a bottom surface of the first dielectric stack and separated from the first frontside source/drain region; and
a via-to-backside power rail (106/152/120) disposed on a sidewall of the first frontside source/drain region to connect the backside power rail (118) to the first frontside source/drain contact (116);
wherein the first dielectric stack comprises a first dielectric layer (104) and a second dielectric layer (122).
`860 fails to teach wherein the first dielectric stack comprises a first dielectric layer having vertical sidewalls and a bottom surface disposed within a second dielectric layer.
Huang teaches wherein the dielectric stack comprises a first dielectric layer (247, FIG. 5B) having vertical sidewalls and a bottom surface disposed within a second dielectric layer (352, ¶ [0027]).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of forming the backside of an IC with reduced resistance as taught by Huang, [0002].
Re claim 16, `860, Figs. 1D-1E teaches the semiconductor structure of claim 15, further comprising:
a second frontside source/drain region adjacent the first frontside source/drain region;
a second dielectric stack (left (104/122)) disposed on a bottom surface of the second frontside source/drain region (left (108/110)) and on a top surface of the backside power rail; and
a second frontside source/drain contact (left (116)) disposed on a top surface of the second frontside source/drain region;
wherein the second dielectric stack comprises a first dielectric layer and a second dielectric layer (left (104/122)).
Re claim 17, `860, Figs. 1D-1E teaches the semiconductor structure of claim 15, wherein the via-to-backside power rail comprises a lower portion (152/120) located on the backside power rail and an upper portion (106) located on the sidewall of the first frontside source/drain region.
Re claim 18, `860, Figs. 1D-1E teaches the semiconductor structure of claim 17, wherein the lower portion of the via-to-backside power rail comprises a step-wise configuration (152/120).
Re claim 19, `860, Figs. 1D-1E teaches the semiconductor structure of claim 15, wherein the first dielectric layer comprises a first dielectric material (104, [0023]) and the second dielectric layer comprises a second dielectric material (122, [0059]) different from the first dielectric material.
Re claim 20, `860, Figs. 1D-1E teaches a semiconductor structure, comprising:
a backside source/drain contact (152/120) disposed on a bottom surface of a first frontside source/drain region (116);
a backside power rail (118) disposed on the backside source/drain contact and separated from the first frontside source/drain region;
a second frontside source/drain region (left (108/110)) adjacent the first frontside source/drain region (right (108/110)); and
a dielectric stack disposed on a bottom surface of the second frontside source/drain region (right (108/110)) and on a top surface of the backside power rail (118);
wherein the dielectric stack comprises a first dielectric layer (104) and a second dielectric layer (122).
`860 fails to teach wherein the dielectric stack comprises a first dielectric layer having vertical sidewalls and a bottom surface disposed within a second dielectric layer.
Huang teaches wherein the dielectric stack comprises a first dielectric layer (247) having vertical sidewalls and a bottom surface disposed within a second dielectric layer (352, ¶ [0027])
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of forming the backside of an IC with reduced resistance as taught by Huang, [0002].
Re claim 21, `860, Figs. 1D-1E teaches the semiconductor structure of claim 20, wherein the backside power rail (118) is connected to the backside source/drain contact (152/120) from a backside of the semiconductor structure (108/110).
Re claim 22, `860, Figs. 1D-1E teaches the semiconductor structure of claim 20, wherein an upper surface of the backside source/drain contact has a step-wise configuration (144/116) comprising a top portion (116) in contact with the first frontside source/drain region (108/110) and a bottom portion (144) extending (horizontally) between the first frontside source/drain region and the second frontside source/drain region.
Re claim 23, `860, Figs. 1D-1E teaches the semiconductor structure of claim 20, further comprising a frontside source/drain contact (right 116) disposed on a top surface of the second frontside source/drain region (right (108/110)).
Re claim 24, `860, Figs. 1D-1E teaches the semiconductor structure of claim 20, wherein the first dielectric layer comprises a first dielectric material (104, [0023]) and the second dielectric layer comprises a second dielectric material (122, [0059]) different from the first dielectric material.
Claim(s) 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of `860.
Re claim 5, Huang teaches all the limitation of claim 3.
Huang fails to teach the limitation of claim 3.
`860 teaches wherein the via-to-backside power rail (106/152/129, Figs. 1D/1E, [0013]/[0016]) comprises a lower portion (152/120) located on the backside power rail (118) and an upper portion (106) located on a sidewall of the frontside source/drain region (108/110).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of enhancing the connectivity on the backside power rail as taught by [0015]-[0016].
Re claim 6, in the combination, `860, Fig. 1D teaches the semiconductor structure of claim 5, wherein the lower portion of the via-to-backside power rail comprises a step-wise configuration (152/120).
Claim(s) 15-19 and 20-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiang (Pub. No.: US 2022/0367462) in view of `860.
Re claim 15, Chiang, FIGS. 12C/12D/12E teaches a semiconductor structure, comprising:
a first dielectric stack (233/232, [0034]) disposed on (indirectly) a bottom surface of a first frontside source/drain region;
a first frontside source/drain contact (354, FIG. 13E [flip it upside down], [0059]) disposed on a top surface of the first frontside source/drain region;
a backside power rail (239, FIG. 12D) disposed on the first dielectric stack (230/203) and separated from the first frontside source/drain region; and
a via-to-backside power rail (204) disposed on the first frontside source/drain region (260) to connect the backside power rail to the first frontside source/drain contact;
wherein the first dielectric stack comprises a first dielectric layer (233) having vertical sidewalls and a bottom surface disposed within a second dielectric layer (232).
Chiang fails to teach a via-to-backside power rail disposed on a sidewall of the first frontside source/drain region; and a backside power rail disposed on a bottom surface of the first dielectric stack.
`860 teaches a via-to-backside power rail (106/152, Fig. 1D) disposed on a sidewall of the first frontside source/drain region (108); and a backside power rail (118, ¶ [0018]) disposed on a bottom surface of the first dielectric stack (122, [0059]).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of enhancing the connectivity on the backside power rail as taught by [0015]-[0016].
Re claim 16, in the combination, Chiang, FIGS. 12C/12D/12E teaches the semiconductor structure of claim 15, further comprising:
a second frontside source/drain region 260 of FIG. 12E) adjacent the first frontside source/drain region;
a second dielectric stack (230/203) disposed on a bottom surface of the second frontside source/drain region and on a top surface of the backside power rail; and
a second frontside source/drain contact (354 of Fig 13E) disposed on a top surface of the second frontside source/drain region;
wherein the second dielectric stack comprises a first dielectric layer (230) and a second dielectric layer (203).
Re claim 17, in the combination, `860, Fig. 1D teaches the semiconductor structure of claim 15, wherein the via-to-backside power rail comprises a lower portion (152/120) located on the backside power rail and an upper portion (106) located on the sidewall of the first frontside source/drain region (108).
Re claim 18, in the combination, `860, Fig. 1D teaches the semiconductor structure of claim 17, wherein the lower portion of the via-to-backside power rail comprises a step-wise configuration (152/120).
Re claim 19, in the combination, Chiang, FIGS. 12C/12D/12E teaches the semiconductor structure of claim 15, wherein the first dielectric layer comprises a first dielectric material (230) and the second dielectric layer (203) comprises a second dielectric material different from the first dielectric material.
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Re claim 20, Chiang, FIGS. 12C/12D/12E teaches semiconductor structure, comprising:
a backside source/drain contact (239) disposed on a bottom surface of a first frontside source/drain region;
a backside power rail (204) disposed on the backside source/drain contact and separated from the first frontside source/drain region (260 of FIG. 12D);
a second frontside source/drain region (260 of FIG. 12E) adjacent the first frontside source/drain region; and
a dielectric stack (233/232) disposed on a bottom surface of the second frontside source/drain region;
wherein the first dielectric stack comprises a first dielectric layer (233) having vertical sidewalls and a bottom surface disposed within a second dielectric layer (232).
Chiang fails to teach a dielectric stack disposed on a top surface of the backside power rail.
`860 teaches a dielectric stack (104/122) disposed on a top surface of the backside power rail (118).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of enhancing the connectivity on the backside power rail as taught by [0015]-[0016].
Re claim 21, in the combination, Chiang, FIGS. 12C/12D/12E teaches the semiconductor structure of claim 20, wherein the backside power rail (204) is connected to the backside source/drain contact (239) from a backside of the semiconductor structure.
Re claim 22, in the combination, Chiang, FIGS. 12C/12D/12E teaches the semiconductor structure of claim 20, wherein an upper surface of the backside source/drain contact has a step-wise configuration comprising a top portion ([TP], FIG. 12D [as shown above]) in contact with the first frontside source/drain region and a bottom portion [BP] extending between the first frontside source/drain region (260 of FIG. 12D) and the second frontside source/drain region (260 of FIG. 12E).
Re claim 23, in the combination, Chiang, FIGS. 12C/12D/12E teaches the semiconductor structure of claim 20, further comprising a frontside source/drain contact [TP] disposed on a top surface of the second frontside source/drain region (260 of FIG. 2E).
Re claim 24, in the combination, Chiang, FIGS. 12C/12D/12E teaches the semiconductor structure of claim 20, wherein the first dielectric layer comprises a first dielectric material (230) and the second dielectric layer (203) comprises a second dielectric material different from the first dielectric material.
Response to Arguments
Applicant's arguments with respect to claims 1-9 and 16-24 on the remarks filed on 03/11/2026 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST.
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/TONY TRAN/Primary Examiner, Art Unit 2893
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