CTFR 18/080,907 CTFR 85098 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Response to Amendment Claims 1, 8, 11 and 16 have been amended; and claims 1-20 are currently pending. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. 07-34-05 AIA Claim 7 recites the limitation " the second interlayer " in line 1 . There is insufficient antecedent basis for this limitation in the claim. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-2, and 5-20 are rejected under 35 U.S.C. 103 as being unpatentable over Glass et al. (US 2020/0211842 A1, hereinafter “Glass”) in view of Chakraborty et al. (USPN 8105919 B2, hereinafter “Chakraborty”) . In regards to claim 1, Glass discloses (See, for example, Fig. 1) an integrated circuit structure, comprising: a substrate (102) comprising silicon; and a layer (110+106) comprising gallium and nitrogen above the substrate (102), the layer (110+106) comprising gallium and nitrogen having an interlayer (106A) therein, the interlayer (106A) confining a plurality of defects to a lower portion of the layer comprising gallium and nitrogen. Glass is silent about the interlayer intervening between the lower portion of the layer comprising gallium and nitrogen and an upper portion of the layer comprising gallium and nitrogen, the upper portion of the layer comprising gallium and nitrogen having a same composition as the lower portion of the layer comprising gallium and nitrogen, and the interlayer comprising an element not included in the layer comprising gallium and nitrogen. Chakraborty while disclosing a metho degrowing reduced defect density planar gallium nitride teaches (See, for example, Fig. 1) the interlayer (8) intervening between the lower portion of the layer (6) comprising gallium and nitrogen (HT UID GaN (6), See Col. 4 line 32) and an upper portion of the layer (“approximately 0.1 um thick UID GaN”, See Col. 4 lines 37-38) comprising gallium and nitrogen (“approximately 0.1 um thick UID GaN”, See Col. 4 lines 37-38), the upper portion of the layer comprising gallium and nitrogen (“approximately 0.1 um thick UID GaN”, See Col. 4 lines 37-38) having a same composition as the lower portion of the layer comprising gallium and nitrogen (HT UID GaN (6), See Col. 4 line 32), and the interlayer (8) comprising an element not included in the layer comprising gallium and nitrogen (“a thin layer of SiN nanomask (8)”, See Col. 4 line 33). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to incorporate Chakraborty’s in-situ SiN x interlayer within the GaN of Glass’s relaxed buffer stack, in order to reduce the threading dislocation density, and to relieve the strain to avoid cracks. In regards to claim 8, Glass discloses (See, for example, Fig. 1 and 4) an integrated circuit structure, comprising: a substrate (102) comprising silicon; a layer (106/402) comprising gallium and nitrogen above the substrate (102), the layer (106/402) comprising gallium and nitrogen having an interlayer (106A) therein; and a layer (110/404) comprising aluminum and gallium and nitrogen, the layer (110/404) comprising aluminum and gallium and nitrogen on the layer (106/402) comprising gallium and nitrogen, and the layer comprising aluminum and gallium and nitrogen (110/404) having an interlayer (110A/404A, 404C) therein. Glass is silent about the interlayer intervening between the lower portion of the layer comprising gallium and nitrogen and an upper portion of the layer comprising gallium and nitrogen, the upper portion of the layer comprising gallium and nitrogen having a same composition as the lower portion of the layer comprising gallium and nitrogen, and the interlayer comprising an element not included in the layer comprising gallium and nitrogen. Chakraborty while disclosing a metho degrowing reduced defect density planar gallium nitride teaches (See, for example, Fig. 1) the interlayer (8) intervening between the lower portion of the layer (6) comprising gallium and nitrogen (HT UID GaN (6), See Col. 4 line 32) and an upper portion of the layer (“approximately 0.1 um thick UID GaN”, See Col. 4 lines 37-38) comprising gallium and nitrogen (“approximately 0.1 um thick UID GaN”, See Col. 4 lines 37-38), the upper portion of the layer comprising gallium and nitrogen (“approximately 0.1 um thick UID GaN”, See Col. 4 lines 37-38) having a same composition as the lower portion of the layer comprising gallium and nitrogen (HT UID GaN (6), See Col. 4 line 32), and the interlayer (8) comprising an element not included in the layer comprising gallium and nitrogen (“a thin layer of SiN nanomask (8)”, See Col. 4 line 33). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to incorporate Chakraborty’s in-situ SiN x interlayer within the GaN of Glass’s relaxed buffer stack, in order to reduce the threading dislocation density, and to relieve the strain to avoid cracks. In regards to claim 11, Genesis discloses (See, for example, Figs. 1, 4 and 8/9) a computing device (800), comprising: a board (802); and a component ( devices and structures on both 840 and 842 of the board 802) coupled to the board (802), the component including an integrated circuit structure (820, 824, 826, 832), comprising: a substrate (102) comprising silicon; and a layer (110+106) comprising gallium and nitrogen above the substrate (102), the layer (110+106) comprising gallium and nitrogen having an interlayer (106A) therein, the interlayer (106A) confining a plurality of defects to a lower portion of the layer comprising gallium and nitrogen. Glass is silent about the interlayer intervening between the lower portion of the layer comprising gallium and nitrogen and an upper portion of the layer comprising gallium and nitrogen, the upper portion of the layer comprising gallium and nitrogen having a same composition as the lower portion of the layer comprising gallium and nitrogen, and the interlayer comprising an element not included in the layer comprising gallium and nitrogen. Chakraborty while disclosing a metho degrowing reduced defect density planar gallium nitride teaches (See, for example, Fig. 1) the interlayer (8) intervening between the lower portion of the layer (6) comprising gallium and nitrogen (HT UID GaN (6), See Col. 4 line 32) and an upper portion of the layer (“approximately 0.1 um thick UID GaN”, See Col. 4 lines 37-38) comprising gallium and nitrogen (“approximately 0.1 um thick UID GaN”, See Col. 4 lines 37-38), the upper portion of the layer comprising gallium and nitrogen (“approximately 0.1 um thick UID GaN”, See Col. 4 lines 37-38) having a same composition as the lower portion of the layer comprising gallium and nitrogen (HT UID GaN (6), See Col. 4 line 32), and the interlayer (8) comprising an element not included in the layer comprising gallium and nitrogen (“a thin layer of SiN nanomask (8)”, See Col. 4 line 33). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to incorporate Chakraborty’s in-situ SiN x interlayer within the GaN of Glass’s relaxed buffer stack, in order to reduce the threading dislocation density, and to relieve the strain to avoid cracks. In regards to claim 16, Genesis discloses (See, for example, Figs. 1, 4 and 8/9) a computing device (800, Fig. 8), comprising: a board (802, Fig. 8); and a component ( devices and structures on both 840 and 842 of the board 802) coupled to the board (802), the component including an integrated circuit structure (820, 824, 826, 832), comprising: a substrate (102) comprising silicon; a layer (106/402) comprising gallium and nitrogen above the substrate (102), the layer (106/402) comprising gallium and nitrogen having an interlayer (106A) therein; and a layer (110/404) comprising aluminum and gallium and nitrogen, the layer (110/404) comprising aluminum and gallium and nitrogen on the layer (106/402) comprising gallium and nitrogen, and the layer comprising aluminum and gallium and nitrogen (110/404) having an interlayer (110A/404A, 404C) therein. Glass is silent about the interlayer intervening between the lower portion of the layer comprising gallium and nitrogen and an upper portion of the layer comprising gallium and nitrogen, the upper portion of the layer comprising gallium and nitrogen having a same composition as the lower portion of the layer comprising gallium and nitrogen, and the interlayer comprising an element not included in the layer comprising gallium and nitrogen. Chakraborty while disclosing a metho degrowing reduced defect density planar gallium nitride teaches (See, for example, Fig. 1) the interlayer (8) intervening between the lower portion of the layer (6) comprising gallium and nitrogen (HT UID GaN (6), See Col. 4 line 32) and an upper portion of the layer (“approximately 0.1 um thick UID GaN”, See Col. 4 lines 37-38) comprising gallium and nitrogen (“approximately 0.1 um thick UID GaN”, See Col. 4 lines 37-38), the upper portion of the layer comprising gallium and nitrogen (“approximately 0.1 um thick UID GaN”, See Col. 4 lines 37-38) having a same composition as the lower portion of the layer comprising gallium and nitrogen (HT UID GaN (6), See Col. 4 line 32), and the interlayer (8) comprising an element not included in the layer comprising gallium and nitrogen (“a thin layer of SiN nanomask (8)”, See Col. 4 line 33). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to incorporate Chakraborty’s in-situ SiN x interlayer within the GaN of Glass’s relaxed buffer stack, in order to reduce the threading dislocation density, and to relieve the strain to avoid cracks. In regards to claim 2, Glass discloses (See, for example, Fig. 1) the interlayer (106A) comprises silicon and nitrogen, or aluminum and nitrogen, or aluminum and scandium and nitrogen. In regards to claim 5, Glass discloses (See, for example, Fig. 1) a layer (106) comprising aluminum and gallium and nitrogen (110A), the layer comprising aluminum and gallium and nitrogen on the layer comprising gallium and nitrogen (106) . In regards to claim 6, Glass discloses (See, for example, Fig. 1) the layer comprising aluminum and gallium and nitrogen (110) has a second interlayer (110A) therein. In regards to claim 7, Glass discloses (See, for example, Fig. 1) the second interlayer (110A) comprises silicon and nitrogen, or aluminum and nitrogen, or aluminum and scandium and nitrogen. In regards to claim 9, Genesis (See, for example, Fig. 1) the interlayer (not clear as to which one this limitation refers to, 106A, 110A) comprises silicon and nitrogen, or aluminum and nitrogen, or aluminum and scandium and nitrogen. In regards to claim 10, Genesis discloses (See, for example, Fig. 4) the interlayer is an etch stop layer (See, for example, Par [0039]). In regards to claims 12 and 17, Glass (See, for example, Figs1, 4 and 8) a memory (See, for example, 804) coupled to the board (802). In regards to claims 13 and 18, Glass discloses (See, for example, Figs. 1, 4 and 8/9) a communication chip (906, See Fig. 9) coupled to the board (902, See Fig. 9)). In regards to claims 14 and 19, Glass discloses (See, for example, Figs. 1, 4, and 8/9) a camera (CAMERA, See Fig. 9) coupled to the board (902). In regards to claims 15 and 20, Glass discloses (See, for example, Figs. 1, 4 and 8) the component is a packaged integrated circuit die (820, 824, 826, 832) . 07-22-aia AIA Claim s 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Glass in view of Chakraborty as applied to claim 1 above, and further in view of Suh et al. (US 2013/0175580 A1, hereinafter “Suh”) . In regards to claims 3 and 4. Glass discloses all limitation s of claim 1 above except that the layer comprising gallium and nitrogen is a Ga-polar GaN layer; and the layer comprising gallium and nitrogen is an N-polar GaN layer. However, Suh while disclosing a gallium nitride devices teaches that the Ga-faced devices naturally tend to form depletion mode devices, and it goes further and teach that many conventional III-nitride type devices are Ga-faced because a Ga-faced device can be easier to grow (See, for example, Par [0065]). Furthermore, Suh discloses that the selection of N-Polar orientation is a known design choice (See, for example, Figs. 19 and 21). And, it further teaches that enhancement mode or N-faced enhancement mode devices would provide low off state leakage current as well as low on resistance (See, Pars [0006] and [0014]). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to select between the N-polar and Ga-polar GaN layer is oriented to the specific application of a device and Ga-polar GaN is beneficial for it ease of manufacturing while the N-polar GaN is advantageous for facilitating normally-off device operation. It is also known in the art of manufacturing a semiconductor device to integrate both N-polar and Ga-polar GaN on a single substrate for the purpose of manufacturing logic circuits (inverters, gates) that are highly efficient and capable of operating at much higher voltages and temperatures. Response to Arguments Applicant’s arguments with respect to claim(s) 1, 8, 11 and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Correspondence Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERMIAS T WOLDEGEORGIS whose telephone number is (571)270-5350. The examiner can normally be reached on Monday-Friday 8 am - 5 pm E.S.T.. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERMIAS T WOLDEGEORGIS/Primary Examiner, Art Unit 2893 Application/Control Number: 18/080,907 Page 2 Art Unit: 2893 Application/Control Number: 18/080,907 Page 4 Art Unit: 2893 Application/Control Number: 18/080,907 Page 5 Art Unit: 2893 Application/Control Number: 18/080,907 Page 6 Art Unit: 2893 Application/Control Number: 18/080,907 Page 7 Art Unit: 2893 Application/Control Number: 18/080,907 Page 8 Art Unit: 2893 Application/Control Number: 18/080,907 Page 9 Art Unit: 2893 Application/Control Number: 18/080,907 Page 10 Art Unit: 2893 Application/Control Number: 18/080,907 Page 12 Art Unit: 2893 Application/Control Number: 18/080,907 Page 13 Art Unit: 2893
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