DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status Of Claims
Claims 1-20 are currently pending.
Information Disclosure Statement
There is no information disclosure statement filed for this application.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, and 5-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Glass et al. (US 2020/0211842 A1, hereinafter “Glass”).
In regards to claim 1, Glass discloses (See, for example, Fig. 1) an integrated circuit structure, comprising:
a substrate (102) comprising silicon; and
a layer (110+106) comprising gallium and nitrogen above the substrate (102),
the layer (110+106) comprising gallium and nitrogen having an interlayer (106A) therein, the interlayer (106A) confining a plurality of defects to a lower portion of the layer comprising gallium and nitrogen.
In regards to claim 8, Glass discloses (See, for example, Fig. 1 and 4) an integrated circuit structure, comprising:
a substrate (102) comprising silicon;
a layer (106/402) comprising gallium and nitrogen above the substrate (102),
the layer (106/402) comprising gallium and nitrogen having an interlayer (106A) therein; and
a layer (110/404) comprising aluminum and gallium and nitrogen,
the layer (110/404) comprising aluminum and gallium and nitrogen on the layer (106/402) comprising gallium and nitrogen, and
the layer comprising aluminum and gallium and nitrogen (110/404) having an interlayer (110A/404A, 404C) therein.
In regards to claim 11, Genesis discloses (See, for example, Figs. 1, 4 and 8/9) a computing device (800), comprising:
a board (802); and
a component (devices and structures on both 840 and 842 of the board 802) coupled to the board (802), the component including an integrated circuit structure (820, 824, 826, 832), comprising:
a substrate (102) comprising silicon; and
a layer (110+106) comprising gallium and nitrogen above the substrate (102),
the layer (110+106) comprising gallium and nitrogen having an interlayer (106A) therein, the interlayer (106A) confining a plurality of defects to a lower portion of the layer comprising gallium and nitrogen.
In regards to claim 16, Genesis discloses (See, for example, Figs. 1, 4 and 8/9) a computing device (800, Fig. 8), comprising:
a board (802, Fig. 8); and
a component (devices and structures on both 840 and 842 of the board 802) coupled to the board (802), the component including an integrated circuit structure (820, 824, 826, 832), comprising:
a substrate (102) comprising silicon;
a layer (106/402) comprising gallium and nitrogen above the substrate (102),
the layer (106/402) comprising gallium and nitrogen having an interlayer (106A) therein; and
a layer (110/404) comprising aluminum and gallium and nitrogen,
the layer (110/404) comprising aluminum and gallium and nitrogen on the layer (106/402) comprising gallium and nitrogen, and
the layer comprising aluminum and gallium and nitrogen (110/404) having an interlayer (110A/404A, 404C) therein.
In regards to claim 2, Glass discloses (See, for example, Fig. 1) the interlayer (106A) comprises silicon and nitrogen, or aluminum and nitrogen, or aluminum and scandium and nitrogen.
In regards to claim 5, Glass discloses (See, for example, Fig. 1) a layer (106) comprising aluminum and gallium and nitrogen (110A), the layer comprising aluminum and gallium and nitrogen on the layer comprising gallium and nitrogen (106).
In regards to claim 6, Glass discloses (See, for example, Fig. 1) the layer comprising aluminum and gallium and nitrogen (110) has a second interlayer (110A) therein.
In regards to claim 7, Glass discloses (See, for example, Fig. 1) the second interlayer (110A) comprises silicon and nitrogen, or aluminum and nitrogen, or aluminum and scandium and nitrogen.
In regards to claim 9, Genesis (See, for example, Fig. 1) the interlayer (not clear as to which one this limitation refers to, 106A, 110A) comprises silicon and nitrogen, or aluminum and nitrogen, or aluminum and scandium and nitrogen.
In regards to claim 10, Genesis discloses (See, for example, Fig. 4) the interlayer is an etch stop layer (See, for example, Par [0039]).
In regards to claims 12 and 17, Glass (See, for example, Figs1, 4 and 8) a memory (See, for example, 804) coupled to the board (802).
In regards to claims 13 and 18, Glass discloses (See, for example, Figs. 1, 4 and 8/9) a communication chip (906, See Fig. 9) coupled to the board (902, See Fig. 9)).
In regards to claims 14 and 19, Glass discloses (See, for example, Figs. 1, 4, and 8/9) a camera (CAMERA, See Fig. 9) coupled to the board (902).
In regards to claims 15 and 20, Glass discloses (See, for example, Figs. 1, 4 and 8) the component is a packaged integrated circuit die (820, 824, 826, 832).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Glass in view of Suh et al. (US 2013/0175580 A1, hereinafter “Suh”).
In regards to claims 3 and 4. Glass discloses all limitation s of claim 1 above except that the layer comprising gallium and nitrogen is a Ga-polar GaN layer; and the layer comprising gallium and nitrogen is an N-polar GaN layer.
However, Suh while disclosing a gallium nitride devices teaches that the Ga-faced devices naturally tend to form depletion mode devices, and it goes further and teach that many conventional III-nitride type devices are Ga-faced because a Ga-faced device can be easier to grow (See, for example, Par [0065]).
Furthermore, Suh discloses that the selection of N-Polar orientation is a known design choice (See, for example, Figs. 19 and 21). And, it further teaches that enhancement mode or N-faced enhancement mode devices would provide low off state leakage current as well as low on resistance (See, Pars [0006] and [0014]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to select between the N-polar and Ga-polar GaN layer is oriented to the specific application of a device and Ga-polar GaN is beneficial for it ease of manufacturing while the N-polar GaN is advantageous for facilitating normally-off device operation. It is also known in the art of manufacturing a semiconductor device to integrate both N-polar and Ga-polar GaN on a single substrate for the purpose of manufacturing logic circuits (inverters, gates) that are highly efficient and capable of operating at much higher voltages and temperatures.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERMIAS T WOLDEGEORGIS whose telephone number is (571)270-5350. The examiner can normally be reached on Monday-Friday 8 am - 5 pm E.S.T..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERMIAS T WOLDEGEORGIS/Primary Examiner, Art Unit 2893