DETAILED ACTION
This action is responsive to the following communication: the response filed 2/5/2026. The changes and remarks disclosed therein have been considered.
Claim(s) status: 1-14 pending.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/5/2026 has been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 6-8, 13-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hemink (US 2008/0117683).
Regarding claim 1, Hemink discloses a memory device comprising:
a memory array (100; fig. 1); and
control logic (120; fig. 1), operatively coupled with the memory array (100), to perform operations comprising:
causing a boost voltage (voltage VSPGM functions as a boosting voltage, i.e. “amounts of boosting created by these three soft programming voltage pulses [VSPGM1 - VSPGM3] are depicted as VBOOST3, VBOOST4, VBOOST5” fig. 21, para 0094) to be applied three or more times (a series of voltage VSPGM1 - VSPGM3 is shown applied at least three times; fig. 21) to a plurality of unselected wordlines (VSPGM applied to all word lines, essentially including unselected word lines; fig. 21) of a block (any of a block 90; fig. 4) of the memory array (100), the block comprising a plurality of sub-blocks (NAND strings 40 are sub-blocks of each respective block 90; fig. 4), and the boost voltage (VSPGM) to boost a channel potential (“a level of channel boosting in inhibited strings that is proportional thereto [i.e. VBOOST3, VBOOST4, VBOOST5]” para 0094, further channel potential Vch 750/752; fig. 21) of each of the plurality of sub-blocks (i.e. each of the NAND strings) by an amount (an amount proportional to VBOOST; para 0094) each time the boost voltage is applied (i.e. at each applied VSPGM pulse; fig. 21);
selectively discharging the amount of boost voltage (selectively discharging inhibited NAND strings from enabled NAND strings, to be discharged by the amount proportional to VBOOST, i.e. Vch of inhibited NAND strings 750 is shown discharged to 0V; fig. 21) from one or more of the plurality of sub-blocks (the NAND strings 40) after each time of the three or more times the boost voltage is applied (i.e. after each applied VSPGM1 - VSPGM3 pulse; fig. 21) to condition different sub-blocks (the inhibited NAND strings 40) of the plurality of sub-blocks (the NAND strings 40) to different channel potentials (Vch of the inhibited NAND strings 40 are boosted according to VBOOST, i.e. different VBOOST3, VBOOST4, VBOOST5 results in different channel potentials; para 0094-0095) according to a data pattern (a page of program data; para 0050) representing a sequence of bits (multiple bits of data values; para 0057) to be programmed (fig. 8) to respective memory cells of the plurality of sub-blocks (i.e. memory cells of NAND strings 40 coupled to a selected word line; fig. 4, 8); and
causing a single programming pulse (Vpgm; fig. 8 para 0051) to be applied to one or more selected wordlines (Vpgm is applied to selected word line at 214; fig. 8) of the block (i.e. the block 90 comprising the selected word line) to program the respective memory cells of the plurality of sub-blocks (the program data will be programmed into the memory cells; para 0051) according to the data pattern (i.e. the program data).
Regarding claim 6, Hemink discloses the memory device, wherein each sub-block comprises one or more bitlines (bit lines 26; fig. 4), and wherein the control logic is to perform further operations comprising: discharging a first portion of a sub-block (i.e. any portion of NAND strings 40 is discharged to 0V; fig. 21) coupled to a first bitline (a bit line 26) of the one or more bitlines by a first amount (VBOOST3; fig. 21) after applying the boost voltage for a first time (VSPGM1; fig. 21); and discharging a second portion of the sub-block (i.e. another portion of NAND strings 40 is discharged to 0V; fig. 21) coupled to a second bitline (i.e. another bit line 26) of the one or more bitlines by a second amount (VBOOST4; fig. 21) after applying the boost voltage for a second time (VSPGM2; fig. 21), wherein the first portion is associated with a first logic state and the second portion is associated with a second logic state (i.e. any of a first and second portion is programmable with any of a first and second E, A, B, C logic state(s); fig. 4, 8, 10).
Regarding claim 7, Hemink discloses the memory device, wherein the respective memory cells of the plurality of sub-blocks each store two or more bits (fig. 10).
Regarding claim 8, Hemink discloses a method, comprising:
causing a boost voltage (voltage VSPGM functions as a boosting voltage, i.e. “amounts of boosting created by these three soft programming voltage pulses [VSPGM1 - VSPGM3] are depicted as VBOOST3, VBOOST4, VBOOST5” fig. 21, para 0094) to be applied three or more times (a series of voltage VSPGM1 - VSPGM3 is shown applied at least three times; fig. 21) to a plurality of unselected wordlines (VSPGM applied to all word lines, essentially including unselected word lines; fig. 21) of a block (any of a block 90; fig. 4) of the memory array (100), the block comprising a plurality of sub-blocks (NAND strings 40 are sub-blocks of each respective block 90; fig. 4), and the boost voltage (VSPGM) to boost a channel potential (“a level of channel boosting in inhibited strings that is proportional thereto [i.e. VBOOST3, VBOOST4, VBOOST5]” para 0094, further channel potential Vch 750/752; fig. 21) of each of the plurality of sub-blocks (i.e. each of the NAND strings) by an amount (an amount proportional to VBOOST; para 0094) each time the boost voltage is applied (i.e. at each applied VSPGM pulse; fig. 21);
selectively discharging the amount of boost voltage (selectively discharging inhibited NAND strings from enabled NAND strings, to be discharged by the amount proportional to VBOOST, i.e. Vch of inhibited NAND strings 750 is shown discharged to 0V; fig. 21) from one or more of the plurality of sub-blocks (the NAND strings 40) after each time of the three or more times the boost voltage is applied (i.e. after each applied VSPGM1 - VSPGM3 pulse; fig. 21) to condition different sub-blocks (the inhibited NAND strings 40) of the plurality of sub-blocks (the NAND strings 40) to different channel potentials (Vch of the inhibited NAND strings 40 are boosted according to VBOOST, i.e. different VBOOST3, VBOOST4, VBOOST5 results in different channel potentials; para 0094-0095) according to a data pattern (a page of program data; para 0050) representing a sequence of bits (multiple bits of data values; para 0057) to be programmed (fig. 8) to respective memory cells of the plurality of sub-blocks (i.e. memory cells of NAND strings 40 coupled to a selected word line; fig. 4, 8); and
causing a single programming pulse (Vpgm; fig. 8 para 0051) to be applied to one or more selected wordlines (Vpgm is applied to selected word line at 214; fig. 8) of the block (i.e. the block 90 comprising the selected word line) to program the respective memory cells of the plurality of sub-blocks (the program data will be programmed into the memory cells; para 0051) according to the data pattern (i.e. the program data).
Regarding claim 13, Hemink discloses the method, wherein each sub-block comprises one or more bitlines (bit lines 26; fig. 4), the method further comprising: discharging a first portion of a sub-block (i.e. any portion of NAND strings 40 is discharged to 0V; fig. 21) coupled to a first bitline (a bit line 26) of the one or more bitlines by a first amount (VBOOST3; fig. 21) after applying the boost voltage for a first time (VSPGM1; fig. 21); and discharging a second portion of the sub-block (i.e. another portion of NAND strings 40 is discharged to 0V; fig. 21) coupled to a second bitline (i.e. another bit line 26) of the one or more bitlines by a second amount (VBOOST4; fig. 21) after applying the boost voltage for a second time (VSPGM2; fig. 21), wherein the first portion is associated with a first logic state and the second portion is associated with a second logic state (i.e. any of a first and second portion is programmable with any of a first and second E, A, B, C logic state(s); fig. 4, 8, 10).
Regarding claim 14, Hemink discloses the method, wherein the respective memory cells of the plurality of sub-blocks each store two or more bits (fig. 10).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hemink (US 2008/0117683) in view of Seol (US 2011/0013458).
Regarding claim 2, Hemink discloses the memory device, wherein the control logic is to perform further operations comprising: discharging sub-block by a first amount (an amount proportional to VBOOST3 corresponding to VSPPC and VSPGM1; fig. 21) after applying the boost voltage for a first time (i.e. VSPGM1); and discharging sub-block by a second amount (an amount proportional to VBOOST4 corresponding to VSPPC and VSPGM2; fig. 21) after applying the boost voltage a second time (i.e. VSPGM2).
Hemink does not expressly disclose discharging a first sub-block; and discharging a second sub-block.
Seol discloses discharging a first sub-block (first sub-block BL is discharged when USG1 is OFF; fig. 4C) by a first amount (i.e. any amount of discharge) after applying the boost voltage; and discharging a second sub-block (second sub-block BL is discharged when USG2 is OFF; fig. 4D) by a second amount (i.e. any amount of discharge) after applying the boost voltage (at phase B).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Hemink is modifiable as taught by Seol for the purpose of facilitating data accessing schemes by applying boosting voltage in multiple steps to achieve different boosting levels in different channels according to respective data, to improve efficiency of programming data to the device (Abstract, para 0057 of Seol).
Regarding claim 9, Hemink discloses the method, wherein the control logic is to perform further operations comprising: discharging sub-block by a first amount (an amount proportional to VBOOST3 corresponding to VSPPC and VSPGM1; fig. 21) after applying the boost voltage for a first time (i.e. VSPGM1); and discharging sub-block by a second amount (an amount proportional to VBOOST4 corresponding to VSPPC and VSPGM2; fig. 21) after applying the boost voltage a second time (i.e. VSPGM2).
Hemink does not expressly disclose discharging a first sub-block; and discharging a second sub-block.
Seol discloses discharging a first sub-block (first sub-block BL is discharged when USG1 is OFF; fig. 4C) by a first amount (i.e. any amount of discharge) after applying the boost voltage; and discharging a second sub-block (second sub-block BL is discharged when USG2 is OFF; fig. 4D) by a second amount (i.e. any amount of discharge) after applying the boost voltage (at phase B).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Hemink is modifiable as taught by Seol for the purpose of facilitating data accessing schemes by applying boosting voltage in multiple steps to achieve different boosting levels in different channels according to respective data, to improve efficiency of programming data to the device (Abstract, para 0057 of Seol).
Claim(s) 3-5, 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hemink (US 2008/0117683) in view of Seol (US 2011/0013458), and further in view of Dutta et al. (US 2012/0081963 ‒hereinafter Dutta).
Regarding claim 3, Hemink discloses the memory device, wherein the control logic is to perform further operations comprising: discharging sub-block by a third amount (an amount proportional to VBOOST5 corresponding to VSPPC and VSPGM3; fig. 21) after applying the boost voltage for a third time (i.e. VSPGM3).
Hemink, as modified, does not expressly disclose discharging a third sub-block; and refraining from discharging after applying the boost voltage one or more times.
Seol discloses discharging a third sub-block (third sub-block BL is discharged when USG3 is OFF; fig. 4D) by a third amount (i.e. any amount of discharge) after applying the boost voltage (at phase B); a fourth sub-block (fourth sub-block BL corresponding to USGN; fig. 4D).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Hemink is modifiable as taught by Seol for the purpose of facilitating data accessing schemes by applying boosting voltage in multiple steps to achieve different boosting levels in different channels according to respective data, to improve efficiency of programming data to the device (Abstract, para 0057 of Seol).
Dutta discloses applying the boost voltage for a third time (boosted voltage Vpass is applied a third time at t6; fig. 16); and refraining from discharging after applying the boost voltage one or more times (“the program portion of program loop j, the storage element reaches the inhibit or lockout condition, in which it remains [i.e. remains boosted with boost voltage Vboost] until the end of the programming pass” fig. 10D).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Hemink is further modifiable as taught by Dutta for the purpose of facilitating data accessing schemes by applying boosting voltage in multiple steps (i.e. one or more times) to achieve different boosting levels in different channels, which reduces disturbances such as coupling effects (para 0035-0038 of Dutta).
Regarding claim 4, Hemink discloses the memory device, wherein the respective memory cell of the first sub-block is programmed to a first logic state, the respective memory cell of the second sub-block is programmed to a second logic state, the respective memory cell of the third sub-block is programmed to a third logic state, and the respective memory cell of the fourth sub-block is programmed to fourth logic state (first to fourth sub-blocks, i.e. NAND strings 40, are programmed with respective memory cell(s) coupled to the selected word line to any of first to fourth logic state(s) E, A, B, and C; fig. 4, 8, 10) after the programming pulse is applied (para 0051).
Regarding claim 5, Hemink, as modified, does not expressly disclose the memory device, wherein a number of times the boost voltage is applied corresponds to a number of bits stored by the memory cells.
Dutta discloses a number of times the boost voltage is applied corresponds to a number of bits stored by the memory cells (boost voltage is applied four times, which corresponds to four data states, i.e. bits stored by the memory cells; fig. 7A, 10D).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Hemink is further modifiable as taught by Dutta for the purpose of facilitating data accessing schemes by applying boosting voltage in multiple steps (i.e. one or more times) to achieve different boosting levels in different channels, which reduces disturbances such as coupling effects (para 0035-0038 of Dutta).
Regarding claim 10, Hemink discloses the method, further comprising: discharging sub-block by a third amount (an amount proportional to VBOOST5 corresponding to VSPPC and VSPGM3; fig. 21) after applying the boost voltage for a third time (i.e. VSPGM3).
Hemink, as modified, does not expressly disclose discharging a third sub-block; and refraining from discharging after applying the boost voltage one or more times.
Seol discloses discharging a third sub-block (third sub-block BL is discharged when USG3 is OFF; fig. 4D) by a third amount (i.e. any amount of discharge) after applying the boost voltage (at phase B); a fourth sub-block (fourth sub-block BL corresponding to USGN; fig. 4D).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Hemink is modifiable as taught by Seol for the purpose of facilitating data accessing schemes by applying boosting voltage in multiple steps to achieve different boosting levels in different channels according to respective data, to improve efficiency of programming data to the device (Abstract, para 0057 of Seol).
Dutta discloses applying the boost voltage for a third time (boosted voltage Vpass is applied a third time at t6; fig. 16); and refraining from discharging after applying the boost voltage one or more times (“the program portion of program loop j, the storage element reaches the inhibit or lockout condition, in which it remains [i.e. remains boosted with boost voltage Vboost] until the end of the programming pass” fig. 10D).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Hemink is further modifiable as taught by Dutta for the purpose of facilitating data accessing schemes by applying boosting voltage in multiple steps (i.e. one or more times) to achieve different boosting levels in different channels, which reduces disturbances such as coupling effects (para 0035-0038 of Dutta).
Regarding claim 11, Hemink discloses the method, wherein the respective memory cell of the first sub-block is programmed to a first logic state, the respective memory cell of the second sub-block is programmed to a second logic state, the respective memory cell of the third sub-block is programmed to a third logic state, and the respective memory cell of the fourth sub-block is programmed to fourth logic state (first to fourth sub-blocks, i.e. NAND strings 40, are programmed with respective memory cell(s) coupled to the selected word line to any of first to fourth logic state(s) E, A, B, and C; fig. 4, 8, 10) after the programming pulse is applied (para 0051).
Regarding claim 12, Hemink, as modified, does not expressly disclose the method, wherein a number of times the boost voltage is applied corresponds to a number of bits stored by the memory cells.
Dutta discloses a number of times the boost voltage is applied corresponds to a number of bits stored by the memory cells (boost voltage is applied four times, which corresponds to four data states, i.e. bits stored by the memory cells; fig. 7A, 10D).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Hemink is further modifiable as taught by Dutta for the purpose of facilitating data accessing schemes by applying boosting voltage in multiple steps (i.e. one or more times) to achieve different boosting levels in different channels, which reduces disturbances such as coupling effects (para 0035-0038 of Dutta).
Response to Arguments
Applicant’s arguments with respect to the pending claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/UYEN SMET/
[AltContent: arrow] Primary Examiner, Art Unit 2824