DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This final office action is responsive to the amendments filed on 12/08/2025.
Claims 1-20 are pending.
Response to Amendment
Applicant has amended independent claims 1, 8, 14 and dependent claims 2-6, 8, 12 to include new/old limitations in a form not previously presented necessitating new search and considerations.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1 of the instant invention is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of co-pending Application 18/081,547 (hereafter ‘547). Following table illustrate the mapping between the claims:
Instant Invention
18/081,547 (‘547)
1. One of more processors, comprising:
1. A processor, comprising,
circuitry to, in response to a call to an application programming interface (API), cause information received by the API about one or more memory transactions to be stored.
one or more circuits to perform an application programming interface (API) to cause information about one or more memory transactions to be provided to one or more users.
As illustrated in above table, Claim 1 of instant application are rejected on over claim 1 of co-pending application ‘547. Claim 1 recites information received by the API while co-pending application do not recite the exact language of receiving by the API. Similarly, claim 1 of instant invention is directed to storing the information, while the co-pending application recites information to be provided to one or more user. Although the claims at issue are not identical, they are not patentably distinct from each other because in both application, claim is directed to the information accessed by the API and information being stored is being taught by the co-pending application ([0079]) and is only variant of claim 1 of the co-pending application.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claims 1 of the instant invention is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of co-pending Application 18/081,550 (hereafter ‘550) based on similar analysis as above. Following table illustrate the mapping between the claims:
Instant Invention
18/081,547 (‘550)
1. A processor, comprising:
1. A processor, comprising,
one or more circuits to perform an application programming interface (API) to cause information received by the API about one or more memory transactions to be stored.
one or more circuits to perform an application programming interface (API) to check for information provided in a token by one or more users about one or more memory transactions after a first amount of time indicated by the one or more users.
Claims 1 of the instant invention is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of co-pending Application 18/081,534 (hereafter ‘534) based on similar analysis as above. Following table illustrate the mapping between the claims:
Instant Invention
18/081,534 (‘534)
1. A processor, comprising:
1. A processor, comprising,
one or more circuits to perform an application programming interface (API) to cause information received by the API about one or more memory transactions to be stored.
one or more circuits to perform an application programming interface (API) to cause one or more memory transactions
to be performed without storing about the one or more memory transactions.
Claims 1 of the instant invention is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of co-pending Application 18/081,552 (hereafter ‘552) based on similar analysis as above. Following table illustrate the mapping between the claims:
Instant Invention
18/081,552 (‘552)
1. A processor, comprising:
1. A processor, comprising,
one or more circuits to perform an application programming interface (API) to cause information received by the API about one or more memory transactions to be stored.
one or more circuits to perform an application programming interface (API) to check for information provided by one or more users about the one or more memory transactions after a time out event indicated by the one or more users.
Claims 1 of the instant invention is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of co-pending Application 18/081,559 (hereafter ‘559) based on similar analysis as above. Following table illustrate the mapping between the claims:
Instant Invention
18/081,559 (‘559)
1. A processor, comprising:
1. A processor, comprising,
one or more circuits to perform an application programming interface (API) to cause information received by the API about one or more memory transactions to be stored.
one or more circuits to perform an application programming interface (API) to cause one or more software objects to indicate whether one or more memory transaction have been performed.
Claims 1 of the instant invention is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of co-pending Application 18/081,561 (hereafter ‘561) based on similar analysis as above. Following table illustrate the mapping between the claims:
Instant Invention
18/081,561 (‘561)
1. A processor, comprising:
1. A processor, comprising,
one or more circuits to perform an application programming interface (API) to cause information received by the API about one or more memory transactions to be stored.
one or more circuits to perform an application programming interface (API) to cause an amount of information to be accessed as result of one or more memory transaction to be provided to one or more users.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7-8, 13-14, 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kumar et al. (US 2006/0085591 A1, hereafter Kumar) in view of Apodaca et al. (US 2016/0364829 A1, hereafter Apodaca).
Kumar was cited in the last office action.
As per claim 1, Kumar teaches the invention substantially as claimed including one or more processors (fig. 1 processors 101), comprising:
circuitry to ([0025] processor, circuits), in response to a call to an application programming interface (API) ([0005] API, perform tasks requested by a function call [0007] transactional memory API, hardware/software only implementation [0044] responsive to an API request to access memory), cause information received by the API about one or more memory transactions to be stored ([0021] transactional memory accesses, use with API [0044] implement transactional memory accesses i.e. read and write memory operations, responsive to an application program interface request to access memory [0047] fig. 3 memory transaction ISA 300 [0007] [0008] transactional memory fig. 1 API request 116 processor 101 cache 132 memory 105).
Kumar doesn’t specifically teach information to be stored. However, Kumar teaches similar limitations write data to memory ([0035] [0063] fig. 1 116 101 132 105) and using transactional cache to preform read and write ([0044]).
Apodaca, however, teaches cause information received by the API about one or more memory transactions to be stored ([0122] API call, facilitates execution of a number of GPU commands, writing to GPU command buffer 1403B [0152] API call, transition of GPU memory).
It would have been obvious to one of ordinary skills in the art before the effective filing date of the invention was made to have combine the teachings of Kumar with the teachings of Apodaca of writing the GPU commands to the GPU command buffer to improve efficiency and allow received information by API to be stored to the method of Kumar as in the instant invention.
The combination would have been obvious because applying the known method of storing the commands received by API into the command buffer as taught by Apodaca to the method of Kumar to yield predictable results and improved efficiency.
As per claim 7, Kumar teaches wherein the API is to be performed without providing a token to indicate a state of a synchronization object ([0007] transactional memory application program interface [0035] TM ISA, transactional engine, API [0037] object, transaction. API, object, accessed i.e. no token or state of a synchronization).
Claim 8 recites a system for elements similar to claim 1. Therefore, it is rejected for the same rationale.
Claim 13 recites a system for elements similar to claim 7. Therefore, it is rejected for the same rationale.
Claim 14 recites a method for elements similar to claim 1. Therefore, it is rejected for the same rationale.
Claim 19 recites a method for elements similar to claim 7. Therefore, it is rejected for the same rationale.
Claim 20 recites non-transitory readable medium for elements similar to claim 1. Therefore, it is rejected for the same rationale.
Claims 2, 9 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kumar in view of Apodaca, as applied to above claims, and further in view of Shalom et al. (US 2023/0176769 A1, hereafter Shalom).
Shalom was cited in the last office action.
As per claim 2, Kumar teaches wherein the one or more memory transactions are asynchronous memory transactions ([0030] transactional memory transactions), and the circuitry is to cause the information to be stored by updating a thread synchronization object to be updated based, at least in part, on the information received by the API ([0004] transactional memory service, Application programming interface API, access memory [0021] transactional memory accesses, use with API [0037] transaction memory object, shared data object, thread, opens, object, API, read-only manner, object, manipulated [0011] lock-free synchronization).
Kumar and Apodaca, in combination, do not specifically teach asynchronous memory transactions.
Shalom, however, teaches asynchronous memory transactions ([0016] asynchronous, I/O API [0049] host, asynchronously access, memory [0067] memory transaction).
It would have been obvious to one of ordinary skills in the art before the effective filing date of the invention was made to combine the teachings of Kumar and Apodaca with the teachings of Shalom of asynchronous input/output application programming interface to asynchronously memory access to improve efficiency and allow asynchronous memory transactions to the method of Kumar and Apodaca as in the instant invention. The combination would have been obvious because substituting the API performing memory transaction taught by Kumar and Apodaca with asynchronous input/output memory access taught by Shalom to yield predictable results with reasonable expectation of success and improved efficiency.
Claim 9 recites a system for elements similar to claim 2. Therefore, it is rejected for the same rationale.
Claim 15 recites a method for elements similar to claim 2. Therefore, it is rejected for the same rationale.
Claims 3, 10 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kumar in view of Apodaca and further in view of Shalom, as applied to above claims, and further in view of Price et al. (US 2017/0236244 A1, hereafter Price).
Price was cited in the last office action.
As per claim 3, Kumar teaches wherein the one or more memory transactions are asynchronous memory transactions ([0004] transactional memory service, Application programming interface API, access memory [0021] transactional memory accesses, use with API) between a first memory and a second memory of a graphics processing unit (GPU) ( [0035] TM ISA, API, transactional cache 132, read/write data to memory 105 [0004] transactional memory service, Application programming interface API, access memory fig. 1 API request 116 processor 101 cache 132 memory 105), and the circuitry is to cause a thread synchronization object to be updated based, at least in part, on the information received by the API ([0004] transactional memory service, Application programming interface API, access memory [0021] transactional memory accesses, use with API [0037] transaction memory object, shared data object, thread, opens, object, API, read-only manner, object, manipulated [0011] lock-free synchronization).
Kumar and Apodaca doesn’t specifically teach asynchronous memory transaction between first memory and second memory of GPU.
Shalom, however, teaches asynchronous memory transaction ([0016] asynchronous, I/O API [0049] host, asynchronously access, memory [0067] memory transaction).
Price, however, teaches memory transaction between first memory and second memory of GPU ([0037] memory transaction between execution unit and the cache of the graphics processing unit [0100] cache routing data, graphics processing unit, maps different addresses to different caches, distribute cache load across the linked set of graphics processing units).
It would have been obvious to one of ordinary skills in the art before the effective filing date of the invention was made to combine the teachings of Kumar, Apodaca and Shalom with the teachings of Price of memory transaction between execution unit and the cache of the graphics processing unit with distributed cache load across the linked set of graphics processing unit to improve efficiency and allow memory transaction between first memory and second memory of GPU to the method of Kumar, Apodaca and Shalom as in the instant invention. The combination would have been obvious because supplementing the API performing memory transaction taught by Kumar, Apodaca and Shalom with memory to memory transaction on GPU taught by Price to yield predictable results with reasonable expectation of success and improved efficiency.
Claim 10 recites a system for elements similar to claim 3. Therefore, it is rejected for the same rationale.
Claim 16 recites a method for elements similar to claim 3. Therefore, it is rejected for the same rationale.
Claims 4-6, 11-12 and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kumar in view of Apodaca, and further in view of Shalom, and further in view of Price, as applied to above claims, and further in view of Sahu et al. (US 2007/0143755 A1, hereafter Sahu).
Sahu was cited in the last office action.
As per claim 4, Kumar teaches wherein the one or more memory transactions are asynchronous memory transactions ([0004] transactional memory service, Application programming interface API, access memory [0021] transactional memory accesses, use with API) between a first memory and a second memory of a graphics processing unit (GPU) ( [0035] TM ISA, API, transactional cache 132, read/write data to memory 105 [0004] transactional memory service, Application programming interface API, access memory fig. 1 API request 116 processor 101 cache 132 memory 105), and the circuitry is to update a barrier object to indicate that one or more threads have arrived at the barrier object based, at least in part, on the information received by API ([0004] transactional memory service, Application programming interface API, access memory [0021] transactional memory accesses, use with API [0037] transaction memory object, shared data object, thread, opens, object, API, read-only manner, object, manipulated [0011] lock-free synchronization).
Shalom, however, teaches asynchronous memory transaction ([0016] asynchronous, I/O API [0049] host, asynchronously access, memory [0067] memory transaction).
Price, however, teaches memory transaction between first memory and second memory of GPU ([0037] memory transaction between execution unit and the cache of the graphics processing unit [0100] cache routing data, graphics processing unit, maps different addresses to different caches, distribute cache load across the linked set of graphics processing units).
Kumar, Apodaca, Shalom, and Price, in combination, do not specifically teach update a barrier object to indicate that one or more threads have arrived at the barrier object.
Sahu, however, teaches update a barrier object to indicate that one or more threads have arrived at the barrier object (fig. 2 begin transactional memory based transaction 240 have all threads reached the barrier 280 yes/no [0011] each thread arriving at the barrier, increments the barrier variable, increment numberThreadsAtBarrier, barrier object).
It would have been obvious to one of ordinary skills in the art before the effective filing date of the invention was made to combine the teachings of Kumar, Apodaca, Shalom and Price with the teachings of Sahu of incrementing barrier object on the arrival of a thread at the barrier to improve efficiency and allow update a barrier object to indicate that one or more threads have arrived at the barrier object to the method of Kumar, Apodaca, Shalom and Price as in the instant invention. The combination would have been obvious because supplementing the API performing memory transaction taught by Kumar, Apodaca, Shalom and Price with barrier synchronisation method of updating the barrier object upon thread arrival at the barrier taught by Sahu to yield predictable results with reasonable expectation of success and improved serialization and efficiency.
As per claim 5, Kumar teaches wherein the circuitry is based, at least in part, on an amount of data to be asynchronously moved ([0004] transactional memory service, Application programming interface API, access memory [0021] transactional memory accesses, use with API [0044] transactional memory accesses, responsive to an application program interface request to access memory [0047] fig. 3 memory transaction ISA 300) [0007] [0008] transactional memory fig. 1 API request 116 processor 101 cache 132 memory 105).
Shalom teaches remaining claim elements of data to be asynchronous moved ([0016] asynchronous, I/O API [0049] host, asynchronously access, memory [0067] memory transaction).
Sahu teaches remaining claim elements of to update a barrier object to indicate that one or more threads have arrived at the barrier object based on data (fig. 2 begin transactional memory based transaction 240 have all threads reached the barrier 280 yes/no [0011] each thread arriving at the barrier, increments the barrier variable, increment numberThreadsAtBarrier, barrier object [0003] thread, reached the barrier, synchronization barrier).
As per claim 6, Shalom teaches a portion of an asynchronous data movement operation has been performed ([0016] asynchronous, I/O API [0049] host, asynchronously access, memory [0067] memory transaction).
Sahu teaches remaining claim elements wherein the circuitry is to update a barrier object to indicate that a portion of an asynchronous data movement operation has been performed (fig. 2 have all threads reached the barrier 280 commit transaction 290 [0011] numberThreadsAtBarrier, barrierObject, synchronization variable).
Claim 11 recites a system for elements similar to claim 4. Therefore, it is rejected for the same rationale.
Claim 12 recites a system for elements similar to claim 5. Therefore, it is rejected for the same rationale.
Claim 17 recites a method for elements similar to claim 4. Therefore, it is rejected for the same rationale.
Claim 18 recites a method for elements similar to claim 5. Therefore, it is rejected for the same rationale.
Examiners Note
Applicant is further reminded of that the cited paragraphs and in the references as applied to the claims above for the convenience of the applicant(s) and although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider all of the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Response to Arguments
The previous specification objections have been withdrawn.
The previous drawing objections have been withdrawn.
The previous double patent objections have been maintained until the time of allowance as Applicant has requested.
The previous 112(b) objections have been withdrawn.
Applicant's arguments filed on 07/26/2012 to overcome 35 USC 103 rejections have been fully considered but they are moot in view of new ground of rejection.
Allowable Subject Matter
Claims 1+4+5 would be allowable if rewritten in independent form including all of the limitations and overcome the rejections set forth in this office action.
Conclusion
Authorization for Internet Communication
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“Recognizing that internet communications are not secure, I hereby authorize the USPTO to communicate with the undersigned and practitioners in accordance with 37 CFR 1.33 and 37 CFR 1.34 concerning any subject matter of this application by video conferencing, instant messaging, or electronic mail. I understand that a copy of these communications will be made of record in the application file.”
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Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABU ZAR GHAFFARI whose telephone number is (571)270-3799. The examiner can normally be reached on Monday-Thursday 9:00 - 17:00 Hrs.
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/ABU ZAR GHAFFARI/Primary Examiner, Art Unit 2195