CTNF 18/081,537 CTNF 87245 DETAILED ACTION 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. This non-final office action is responsive to the RCE filed on 05/06/2026. Claims 1-20 are pending. Response to Amendment Applicant has amended independent claims 1, 8, 14 and dependent claims 2-6, 9-13, 15-16 to include new/old limitations in a form not previously presented necessitating new search and considerations. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp . Claims 1 of the instant invention is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of co-pending Application 18/081,547 (hereafter ‘547). Following table illustrate the mapping between the claims: Instant Invention 18/081,547 ( ‘547 ) 1. One of more processors, comprising: 1. A processor, comprising, circuitry to, in response to a call to an application programming interface (API), cause information received by the API about one or more memory transactions to be stored. one or more circuits to perform an application programming interface (API) to cause information about one or more memory transactions to be provided to one or more users. As illustrated in above table, Claim 1 of instant application are rejected on over claim 1 of co-pending application ‘547. Claim 1 recites information received by the API while co-pending application do not recite the exact language of receiving by the API. Similarly, claim 1 of instant invention is directed to storing the information, while the co-pending application recites information to be provided to one or more user. Although the claims at issue are not identical, they are not patentably distinct from each other because in both application, claim is directed to the information accessed by the API and information being stored is being taught by the co-pending application ([0079]) and is only variant of claim 1 of the co-pending application. This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented. Claims 1 of the instant invention is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of co-pending Application 18/081,559 (hereafter ‘559 ) based on similar analysis as above. Following table illustrate the mapping between the claims: Instant Invention 18/081,559 ( ‘559 ) 1. A processor, comprising: 1. A processor, comprising, one or more circuits to perform an application programming interface (API) to cause information received by the API about one or more memory transactions to be stored. one or more circuits to perform an application programming interface (API) to cause one or more software objects to indicate whether one or more memory transaction have been performed. Claims 1 of the instant invention is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of co-pending Application 18/081,561 (hereafter ‘561 ) based on similar analysis as above. Following table illustrate the mapping between the claims: Instant Invention 18/081,561 ( ‘561 ) 1. A processor, comprising: 1. A processor, comprising, one or more circuits to perform an application programming interface (API) to cause information received by the API about one or more memory transactions to be stored. one or more circuits to perform an application programming interface (API) to cause an amount of information to be accessed as result of one or more memory transaction to be provided to one or more users. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 1-20 are rejected under 35 U.S.C. 112 (b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or joint inventor regards as the invention. Claim 1 recites “ an amount of data to be moved ”. It is unclear how “the amount of data to be moved” is related to the rest of claim element i.e. if the amount data is associated with the transaction or the information received by the API or both. Claim 5 recites “ an amount of data to be asynchronously moved” while claim 1 recites “an amount of data to be moved”. It is unclear if the amount of data to be (asynchronously) moved are same or different. Claims 8 and 14 recite elements of claim 1 and have similar deficiency as claim 1. Therefore, they are rejected for the same rational. Remaining dependent claims 2-7, 9-13 and 15-20 are also rejected due to their dependency on the rejected independent claims. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kumar et al. (US 2006/0085591 A1, hereafter Kumar) in view of Apodaca et al. (US 2016/0364829 A1, hereafter Apodaca), and further in view of Sura et al. (US 2020/0151028 A1, hereafter Sura) . Kumar and Apodaca were cited in the last office action. As per claim 1, Kumar teaches the invention substantially as claimed including one or more processors (fig. 1 processors 101) , comprising: circuitry to ([0025] processor, circuits), in response to a call to an application programming interface (API) ([0005] API, routine, perform tasks requested by a function call [0007] transactional memory API, hardware/software only implementation [0044] implement transactional memory access responsive to an API request to access memory, perform read/write operations), cause information received by the API about one or more asynchronous memory transactions associated with a graphics processing unit (GPU) to be stored ([0021] transactional memory accesses, use with API [0044] implement transactional memory accesses, responsive to an application program interface request to access memory, perform read/write operations i.e. storing information [0047] fig. 3 memory transaction ISA 300 [0005] API[0007] [0008] transactional memory fig. 1 API request 116 processor 101 cache 132 memory 105 [0025] processor, refers, special purpose microprocessors, ASICs, signal processor) by updating a thread synchronization object based, at least in part, on the information received by the API ([0058] fig. 4 transaction from an API 402, [0074] lock acquired /initiated 502 sync. object is updated [005] perform read/write operations for the transactions, transaction complete/committed, lock is released i.e. sync. object updated). Kumar doesn’t specifically teach asynchronous memory transactions, information to be stored by updating a thread synchronization object, based, at least in part, on the an amount of data to be moved . However, Kumar teaches similar limitations write data to memory ([0035] [0063] fig. 1 116 101 132 105) and using transactional cache to preform read and write ([0044]). Apodaca, however, teaches cause information received by the API about one or more asynchronous memory transactions to be stored ([0122] API call, facilitates execution of a number of GPU commands, writing to GPU command buffer 1403B [0152] API call, transition of GPU memory [0158] transactional sequence, any number of them can be performed in parallel, asynchronously). It would have been obvious to one of ordinary skills in the art before the effective filing date of the invention was made to have combine the teachings of Kumar with the teachings of Apodaca of writing the GPU commands to the GPU command buffer performed asynchronously to improve efficiency and allow information received by the API about one or more asynchronous memory transactions to be stored to the method of Kumar as in the instant invention. The combination would have been obvious because applying the known method of storing the commands received by API into the command buffer asynchronously as taught by Apodaca to the method of Kumar to yield predictable results and improved efficiency. Kumar and Apodaca, in combination, do not specifically teach information stored by updating a thread synchronization object, based, at least in part, on an amount of data to be moved. Sura, however, teaches information stored by updating a thread synchronization object, based, at least in part, on an amount of data to be moved ([0015] barrier release should occur when a certain amount of data is updated in a specified memory region, [0017] barrier-like synchronization, barrier release condition, based, reaching a threshold one or more defined measures, e.g. number of process /threads and/or amount of data updated in a specified memory region [0056] signaling release of the barrier when threshold is met). It would have been obvious to one of ordinary skills in the art before the effective filing date of the invention was made to have combine the teachings of Kumar and Apodaca with the teachings of Sura of barrier like synchronization mechanism where a barrier release condition is based on reaching a threshold one or more defined measures including amount of data updated in a specified memory region to improve efficiency and allow information stored by updating a thread synchronization object, based, at least in part, on an amount of data to be moved to the method of Kumar and Apodaca as in the instant invention. The combination would have been obvious because applying the known method of releasing barrier based on amount of data updated in a specified memory region as taught by Sura to the method of Kumar and Apodaca to yield predictable results and improved efficiency. As per claim 2, Sura teaches wherein the thread synchronization object is to be updated to indicate arrival of one or more threads at the thread synchronization barrier ([0056] track threads hitting the barrier ). As per claim 3, Kumar teaches wherein the one or more memory transactions are asynchronous memory transactions are between a first memory and a second memory of the GPU ([0004] transactional memory service, Application programming interface API, access memory [0021] transactional memory accesses, use with API [0035] TM ISA, API, transactional cache 132, read/write data to memory 105 [0004] transactional memory service, Application programming interface API, access memory fig. 1 API request 116 processor 101 cache 132 memory 105). Apodaca teaches remaining claim elements of asynchronous memory transaction, ([0122] API call, facilitates execution of a number of GPU commands, writing to GPU command buffer 1403B [0152] API call, transition of GPU memory [0158] transactional sequence, any number of them can be performed in parallel, asynchronously), memory of the GPU (fig. 17 GPU command buffer 1731 GPU command buffer 1733). As per claim 4, Kumar teaches wherein the one or more memory transactions are asynchronous memory transactions are between a first memory and a second memory of the GPU ([0004] transactional memory service, Application programming interface API, access memory [0021] transactional memory accesses, use with API [0035] TM ISA, API, transactional cache 132, read/write data to memory 105 [0004] transactional memory service, Application programming interface API, access memory fig. 1 API request 116 processor 101 cache 132 memory 105), and updating the thread synchronization object comprises updating a object based, at least in part, on the information received by the API ([0058] fig. 4 transaction from an API 402, [0074] lock acquired /initiated 502 [0075] perform read/write operations for the transactions, transaction complete/committed, lock is released). Apodaca teaches remaining claim elements of asynchronous memory transaction, ([0122] API call, facilitates execution of a number of GPU commands, writing to GPU command buffer 1403B [0152] API call, transition of GPU memory [0158] transactional sequence, any number of them can be performed in parallel, asynchronously), memory of the GPU (fig. 17 GPU command buffer 1731 GPU command buffer 1733). Sura teaches remaining claim elements of updating a barrier object to indicate that one or more threads have arrived at the barrier object ( [0056] synchronization barrier, track threads hitting the barrier, signaling release of the barrier when threshold is met). As per claim 5, Sura teaches wherein updating the thread synchronization object comprises updating a barrier object to indicate that one or more threads have arrived at the barrier object based, at least in part, on an amount of data to be asynchronously moved ([0015] barrier release should occur when a certain amount of data is updated in a specified memory region, [0017] barrier-like synchronization, barrier release condition, based, reaching a threshold one or more defined measures, e.g. number of process /threads and/or amount of data updated in a specified memory region [0056] signaling release of the barrier when threshold is met, track threads hitting the barrier). As per claim 6, Sura teaches wherein updating the thread synchronization object comprises updating a barrier object to indicate that a portion of an asynchronous data movement operation has been performed ([0017] barrier-like synchronization, barrier release condition, based, reaching a threshold one or more defined measures, e.g. number of process /threads and/or amount of data updated in a specified memory region). As per claim 7, Sura teaches wherein the thread synchronization object is to be updated without providing token to indicate a state of synchronization object ([0017] barrier-like synchronization, barrier release condition, based, reaching a threshold one or more defined measures, e.g. number of process /threads and/or amount of data updated in a specified memory region [0056] signaling release of barrier ; i.e. No token for state is provided). Claim 8 recites a system for elements similar to claim 1. Therefore, it is rejected for the same rationale. Claim 9 recites a system for elements similar to claim 2. Therefore, it is rejected for the same rationale. Claim 10 recites a system for elements similar to claim 3. Therefore, it is rejected for the same rationale. Claim 11 recites a system for elements similar to claim 4. Therefore, it is rejected for the same rationale. Claim 12 recites a system for elements similar to claim 5. Therefore, it is rejected for the same rationale. Claim 13 recites a system for elements similar to claim 7. Therefore, it is rejected for the same rationale. Claim 14 recites a method for elements similar to claim 1. Therefore, it is rejected for the same rationale. Claim 15 recites a method for elements similar to claim 2. Therefore, it is rejected for the same rationale. Claim 16 recites a method for elements similar to claim 3. Therefore, it is rejected for the same rationale. Claim 17 recites a method for elements similar to claim 4. Therefore, it is rejected for the same rationale. Claim 18 recites a method for elements similar to claim 5. Therefore, it is rejected for the same rationale. Claim 19 recites a method for elements similar to claim 7. Therefore, it is rejected for the same rationale. Claim 20 recites non-transitory readable medium for elements similar to claim 1. Therefore, it is rejected for the same rationale. Examiners Note Applicant is further reminded of that the cited paragraphs and in the references as applied to the claims above for the convenience of the applicant(s) and although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider all of the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner . Response to Arguments The previous double patent objections have been maintained until the time of allowance as Applicant has requested. Applicant's arguments filed on 05/06/2026 to overcome 35 USC 103 rejections have been fully considered but they are moot in view of new ground of rejection. Allowable Subject Matter The previously allowable subject matter has been withdrawn in view of new grounds of rejections. Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Li, Zhan-Chuan (CN-107908472-A) teaches data synchronization device to perform synchronization tasks corresponding to the synchronization data. Stritzel; Adam et al. (US-20140172793-A1) teaches opportunistic priority based object synchronization Sudmeier; Reinhard (US-20240126774-A1) teaches control mechanism of extract transfer and load ETL processes to improve memory usage Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABU ZAR GHAFFARI whose telephone number is (571)270-3799. The examiner can normally be reached on Monday-Thursday 9:00 - 17:00 Hrs. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amiee Lee can be reached on 571-272-4169. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. 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If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ABU ZAR GHAFFARI/Primary Examiner, Art Unit 2195 Application/Control Number: 18/081,537 Page 2 Art Unit: 2195 Application/Control Number: 18/081,537 Page 3 Art Unit: 2195 Application/Control Number: 18/081,537 Page 4 Art Unit: 2195 Application/Control Number: 18/081,537 Page 5 Art Unit: 2195 Application/Control Number: 18/081,537 Page 6 Art Unit: 2195 Application/Control Number: 18/081,537 Page 7 Art Unit: 2195 Application/Control Number: 18/081,537 Page 8 Art Unit: 2195 Application/Control Number: 18/081,537 Page 9 Art Unit: 2195 Application/Control Number: 18/081,537 Page 10 Art Unit: 2195 Application/Control Number: 18/081,537 Page 11 Art Unit: 2195 Application/Control Number: 18/081,537 Page 13 Art Unit: 2195
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