Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-9 in the reply filed on 04/03/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation "first top VTFET" in lines 3 and 4 of the claim and “the second bottom VTFET” in line 4 of the claim. There is insufficient antecedent basis for these limitations in the claim.
Claim 3 recites the limitation "third bottom VTFET" in line 3 of the claim. There is insufficient antecedent basis for this limitation in the claim. Claim 4, which is dependent on claim 3, is similarly rejected.
Claim 5 recites the limitation "first top VTFET" in line 3 of the claim. There is insufficient antecedent basis for this limitation in the claim. Claims 6-9, which are dependent on claim 5, are similarly rejected.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US Patent Pub 20240021586 A1) in view of Wu et al. (US Patent Pub 20200343241 A1).
Regarding Claim 1, Li teaches a semiconductor device (Li, Fig. 1, semiconductor device CFET(100). For this action, the device CFET(100) will be interpreted such that the device is rotated 180 degrees along the Y axis, with the first contact layer being the new top of the device, and the second contact layer being the bottom of the device) comprising:
a top layer comprising a top field effect transistor (FET) (Li, Fig. 1, Top layer 130/132 comprising a top FET 102);
a bottom layer disposed beneath the top layer, wherein the bottom layer comprises a first bottom field effect transistor (FET) (Li, Fig. 1, bottom layer 130/136/138 comprising first bottom FET 104);
and a first frontside contact that wires, through a first backside contact and a first local interconnect, a bottom source/drain (S/D) epitaxial (epi) of the first bottom VTFET to a back end of line (BEOL) interconnect (Fig. 1, frontside contact VIA(1)/CON(5)/VIA(7) that wires a bottom source/drain (S/D) epitaxial (epi) 122A of the first bottom FET 104 to a BEOL interconnect 140 through a first backside contact CON(5)/VIA(7) and a first local interconnect VIA(1)).
Li fails to teach the semiconductor device comprising vertical-transport field effect transistors (VTFET) and instead the embodiments utilize a gate all around (GAA) FET structure.
However, Wu teaches a semiconductor device comprising stacked VTFETs (Wu, Fig. 12 and Abstract teach the semiconductor device is comprised of stacked VTFETs). Additionally, the background of Li discloses that GAA FETs and VTFETs are interchangeable in devices with a high level of performance (Li, paragraph 0002).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Wu into the method of Li by forming the semiconductor device with stacked VTFETs. The ordinary artisan would have been motivated to modify Li in the manner set forth above for at least the purpose of utilizing the VTFETs to provide higher density scaling and allow for relaxed gate lengths to better control device electrostatics, without sacrificing the gate contact pitch size (Wu, paragraph 0002).
Allowable Subject Matter
Claims 2-9 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
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/V.R.G./Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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