Prosecution Insights
Last updated: October 23, 2026
Application No. 18/081,795

STACKED VERTICAL-TRANSPORT FIELD EFFECT TRANSISTORS (VTFETs)

Final Rejection §103
Filed
Dec 15, 2022
Examiner
GONZALES, VICENTE ROLANDO
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
International Business Machines Corporation
OA Round
2 (Final)
100%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 100% — above average
100%
Career Allowance Rate
3 granted / 3 resolved
+32.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
24 currently pending
Career history
38
Total Applications
across all art units

Statute-Specific Performance

§103
57.0%
+17.0% vs TC avg
§102
27.0%
-13.0% vs TC avg
§112
14.0%
-26.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 3 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment The amendment filed 07/20/2026 has been entered. Applicant’s amendments to the claims have overcome each and every 112(b) rejection previously set forth in the Non-Final Office Action. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US Patent Pub 20240047455 A1) in view of Wu et al. (US Patent Pub 20200343241 A1, hereafter referred to as Wu 241). Regarding Claim 1, Li teaches a semiconductor device comprising: a top layer comprising a first top field effect transistor (FET) (Li, fig. 1, the top layer is the top half of the device comprising first top FET 104B (see annotated figure below)); a bottom layer disposed beneath the top layer, wherein the bottom layer comprises a first bottom TFET (Li, fig. 1, the bottom layer is the bottom half of the device comprising first bottom FET 106B (see annotated figure below)); a first backside contact that wires, through a local interconnect, a top source/drain (S/D) epitaxial (epi) of the first bottom FET to a backside interconnect (Li, fig. 1, a first backside contact 114(11)/136(2)/114(10) that wires, through a local interconnect 114(11), a left source/drain (S/D) epitaxial (epi) SD1-LB1 of the first bottom FET 106B to a backside interconnect 136(2)/114(10)) and a first frontside contact that wires, through a first backside contact and a first local interconnect, a bottom source/drain (S/D) epitaxial (epi) of the first bottom FET to a back end of line (BEOL) interconnect (Li, fig. 1, first frontside contact 114(12)/136(3)/114(8) that wires a bottom source/drain (s/D) epi SD1-LB2 of the first bottom FET 106B to a BEOL interconnect 120(6) through a first backside contact 136(3)/114(8) and a first local interconnect 114(12)). Li fails to teach the semiconductor device comprising vertical-transport field effect transistors (VTFET) and instead the embodiments utilize a complimentary (CMOS) field-effect transistor (CFET) structure. However, Wu 241 teaches a semiconductor device comprising stacked VTFETs (Wu 241, Fig. 12 and Abstract teach the semiconductor device is comprised of stacked VTFETs). The background of Li discloses a variety of transistors as being interchangeable in devices with a high level of performance (Li, paragraph 0002). Additionally, cited reference Wu 019 (US patent pub 20220393019 A1, referred to as Wu 019, paragraph 0028) teaches CMOS FETS can be interchangeable in semiconductor devices with VTFETS. It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Wu 241 into the method of Li by forming the semiconductor device with stacked VTFETs. The ordinary artisan would have been motivated to modify Li in the manner set forth above for at least the purpose of utilizing the VTFETs to provide higher density scaling and allow for relaxed gate lengths to better control device electrostatics, without sacrificing the gate contact pitch size (Wu 241, paragraph 0002). Additionally, art recognized suitability for an intended purpose has been recognized to be motivation to combine the VTFETS of Wu 241 in place of other transistor arrangements for at least the purpose of providing higher density scaling as described above (see MPEP 2144.07). Allowable Subject Matter Claims 2-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Response to Arguments Applicant’s arguments with respect to claim(s) 1 have been considered but are moot in view of the new grounds of rejection as applied above. Cited Prior Art The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. Applicants are directed to consider additional pertinent prior art included on the Notice of References Cited (PTO-892) attached herewith. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICENTE R GONZALES whose telephone number is (571)272-3365. The examiner can normally be reached Monday - Friday 7:30 am - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /V.R.G./Examiner, Art Unit 2899 /JOHN M PARKER/Primary Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Dec 15, 2022
Application Filed
Jun 20, 2024
Response after Non-Final Action
Apr 22, 2026
Non-Final Rejection mailed — §103
Jul 08, 2026
Interview Requested
Jul 20, 2026
Response Filed
Oct 08, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12740486
ELECTRONIC DEVICE INCLUDING STACKED SEMICONDUCTOR CHIPS AND METHOD OF MANUFACTURING THE SAME
2y 11m to grant Granted Sep 15, 2026
Study what changed to get past this examiner. Based on 1 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
100%
Grant Probability
99%
With Interview (+0.0%)
2y 9m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 3 resolved cases by this examiner. Grant probability derived from career allowance rate.

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