Prosecution Insights
Last updated: April 19, 2026
Application No. 18/082,238

Semiconductor Devices Including a Premolded Leadframe and a Semiconductor Package

Final Rejection §102§103
Filed
Dec 15, 2022
Examiner
PHAM, LONG
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Infineon Technologies AG
OA Round
2 (Final)
91%
Grant Probability
Favorable
3-4
OA Rounds
2y 6m
To Grant
97%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allow Rate
1493 granted / 1633 resolved
+23.4% vs TC avg
Moderate +6% lift
Without
With
+5.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
38 currently pending
Career history
1671
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
39.9%
-0.1% vs TC avg
§102
41.8%
+1.8% vs TC avg
§112
11.1%
-28.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1633 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s selection of device claims 1-22 is noted. The species restriction dated 7/10/25 has been withdrawn. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-6, 11-17, and 22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (US pub 20210366833). With respect to claim 1, Huang et al. teach a semiconductor device, comprising (see figs. 1-6, particularly figs. 2E and 2H and associated text): a premolded leadframe 260, comprising a main surface (bottom), at least one electrical contact 255 extending out of the main surface, and an opposite main surface (top) arranged opposite to the main surface; and a semiconductor package 100 arranged on the main surface and laterally displaced to the at least one electrical contact of the premolded leadframe, wherein the semiconductor package comprises a semiconductor chip 100 and at least one electrical contact 130, wherein surfaces of the at least one electrical contact of the premolded leadframe and the at least one electrical contact of the semiconductor package facing away from the main surface are flush. With respect to claim 2, Huang et al. teach the premolded leadframe comprises a cavity (area between 255), the at least one electrical contact of the premolded leadframe forms at least a portion of a sidewall of the cavity, and the semiconductor package is arranged in the cavity. Figs. 2C and 2D and associated text. With respect to claim 3, Huang et al. teach the electrical contacts of the premolded leadframe and the semiconductor package are configured to mechanically and electrically couple the semiconductor device to a printed circuit board P2. Figs. 2H and associated text. With respect to claim 4, Huang et al. teach the semiconductor package comprises a laminate material and the semiconductor chip is encapsulated in the laminate material. Figs. 2E and associated text. With respect to claim 5, Huang et al. teach the semiconductor package comprises a mold compound and the semiconductor chip is encapsulated in the mold compound. Figs. 2E and associated text. With respect to claim 6, Huang et al. teach a further semiconductor chip P2, wherein the further semiconductor chip is encapsulated in the semiconductor package or in a further semiconductor package arranged on the main surface. Figs. 2H and associated text. With respect to claim 11, Huang et al. teach the premolded leadframe comprises an electrical redistribution layer P1 arranged on the opposite main surface of the premolded leadframe. Figs. 2H and associated text. With respect to claim 12, Huang et al. teach the electrical redistribution layer is configured for a routing of logical signals. Figs. 2H and associated text. With respect to claim 13, Huang et al. teach a logic semiconductor chip 100 configured to drive and/or control at least the semiconductor chip 100. Figs. 2H and associated text. With respect to claim 14, Huang et al. teach the logic semiconductor chip is arranged on the opposite main surface of the premolded leadframe. Figs. 2H and associated text. With respect to claim 15, Huang et al. teach the logic semiconductor chip is encapsulated in the semiconductor package. Figs. 2H and associated text. With respect to claim 16, Huang et al. teach at least one passive electronic component 250 arranged on the opposite main surface of the premolded leadframe. See para 0038. With respect to claim 17, Huang et al. teach the at least one passive electronic component comprises an inductor. See para 0038. With respect to claim 14, Huang et al. teach a filling material 260 at least partly filling the cavity and/or the gap. Figs. 2H and associated text. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 7-10 are is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US pub 20210366833). With respect claims 7-9 and 10, Huang et al. teach the semiconductor chips contain active and passive devices, but fail to teach the chips contain DC-DC converter. It would have been obvious to one of ordinary skill in the art of making semiconductor devices to contain DC-DC converter in the chips to increase the integration of various devices to increase functionality. With respect to claim 10, Huang et al. teach the premolded leadframe comprises a portion (right or left 255) extending in a lateral direction, wherein the portion is configured to carry an electric current output by at least one of the transistors Allowable Subject Matter Claims 18-20 and 24-25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Response to Arguments Applicant's arguments filed 12/30/25 have been fully considered but they are not persuasive. See below. In response to the applicant’s arguments on pages 7 and 8 of the amendment dated 12/30/25, it is submitted that the claimed premolded or molded leaframe is defined as a conductive/metal structure having parts of it molded, fig. 2E of Huang et al. shows a leadframe comprises of metal contact 255 and metal circuit 230 that are molded by 260. Further it is submitted that the metal contact 255 carries the electrical signal of the metal circuit 230. Further, it is submitted that the metal contact 225 extending out from the main surface (top surface of the leadframe). Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. /LONG PHAM/Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Dec 15, 2022
Application Filed
Sep 28, 2025
Non-Final Rejection — §102, §103
Dec 30, 2025
Response Filed
Mar 16, 2026
Final Rejection — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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PACKAGE STRUCTURES WITH COLLAPSE CONTROL FEATURES
2y 5m to grant Granted Apr 14, 2026
Patent 12604754
PACKAGE STRUCTURES WITH NON-UNIFORM INTERCONNECT FEATURES
2y 5m to grant Granted Apr 14, 2026
Patent 12604766
SEMICONDUCTOR PACKAGE STRUCTURE
2y 5m to grant Granted Apr 14, 2026
Patent 12604739
Semiconductor Device and Method of Forming a 3-D Stacked Semiconductor Package Structure
2y 5m to grant Granted Apr 14, 2026
Patent 12599033
QUASI-MONOLITHIC INTEGRATED PACKAGING ARCHITECTURE WITH MID-DIE SERIALIZER/DESERIALIZER
2y 5m to grant Granted Apr 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
91%
Grant Probability
97%
With Interview (+5.6%)
2y 6m
Median Time to Grant
Moderate
PTA Risk
Based on 1633 resolved cases by this examiner. Grant probability derived from career allow rate.

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