Prosecution Insights
Last updated: August 17, 2026
Application No. 18/082,285

INTEGRATED CIRCUIT HAVING EXPOSED LEADS

Final Rejection §102§103§112
Filed
Dec 15, 2022
Examiner
DAS, PINAKI
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
2 (Final)
89%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
41 granted / 46 resolved
+21.1% vs TC avg
Moderate +9% lift
Without
With
+8.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
37 currently pending
Career history
88
Total Applications
across all art units

Statute-Specific Performance

§103
48.0%
+8.0% vs TC avg
§102
26.8%
-13.2% vs TC avg
§112
24.4%
-15.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 46 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Claim 25 is objected to because of the following informalities: Claim 25 recites, “..where a thickness of the -- flanged portion 122 -- can range..” in lines 2-3. Examiner believes that it should recite, “..where a thickness of the -- flanged portion -- can range..” Appropriate correction is required. Claim Rejections - 35 USC § 112 Prior rejection of Claim 3 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, is withdrawn in view of applicant’s amendments to the claim. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-5, 22-23 and 28-30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Koduri et al. (US 2019/0109108 A1, newly cited). Re Claim 1, Koduri teaches an electronic device (Fig. 5A) comprising: a semiconductor substrate (501, Fig. 5A, para [0058]); a conductive structure (503, Fig. 5A, para [0058]) disposed over the semiconductor substrate (501); an insulator layer (507, Fig. 5A, para [0058]) overlying the semiconductor substrate (501) with a tapered opening (see Fig. 5A) overlying a portion of the conductive structure (503); and a single piece flanged conductive column (509, Fig. 5A, para [0059]) having a base portion (510, Fig. 5A, para [0059]) disposed in the tapered opening (tapered opening within 507, see Fig. 5A) and coupled to the portion of the conductive structure (503) and a flanged portion (511, Fig. 5A, para [0059]) being configured to be exposed to provide a conductive contact to the electronic device (see Fig. 5A). Re Claim 2, Koduri teaches the electronic device of claim 1, wherein the flanged conductive column (509) comprises a solder coated (512, Fig. 5A, para [0059]) flanged copper column (copper column, para [0059]). Re Claim 3, Koduri teaches the electronic device of claim 2, wherein each of the base portion (510) and the flanged portion (511) of the solder coated flanged conductive column have a rectangular or square prism shape (510 and 511 have rectangular shapes, see Fig. 5A). Re Claim 4, Koduri teaches the electronic device of claim 1, wherein the semiconductor substrate (501) contains electronic circuitry and is formed from a portion of a semiconductor wafer (501 contains integrated circuits, para [0058]). Re Claim 5, Koduri teaches the electronic device of claim 1, wherein the insulator layer (507, Fig. 5A, para [0058]) is formed from polyimide (PI) (protective layer 507 is similar to the protective layer 107, which can be a polyimide layer, para [0027]). Re Claim 22, Koduri teaches the electronic device of claim 1, wherein each of the base portion and the flanged portion has a T-shaped cross-section (see Fig. 5A). Re Claim 23, Koduri teaches the electronic device of claim 1, wherein the base portion of the flanged conductive column has width w and a depth d (510, marked “w1” and “d1” in annotated Fig. 5B below) that is less than a width W and a depth D of the flanged portion (511, marked “w2” and “d2” in annotated Fig. 5B below, where w1 and d1 are smaller than w2 and d2). PNG media_image1.png 330 629 media_image1.png Greyscale Re Claim 28, Koduri teaches An electronic device (Fig. 5A) comprising: a semiconductor substrate (501, Fig. 5A, para [0058]); a conductive structure (503, Fig. 5A, para [0058]) disposed over the semiconductor substrate (501); an insulator layer (507, Fig. 5A, para [0058]) overlying the semiconductor substrate (501) with a tapered opening (see Fig. 5A) overlying a portion of the conductive structure (503); and a flanged conductive column of a same material (509, Fig. 5A, para [0059]) having a base portion (510, Fig. 5A, para [0059]) disposed in the tapered opening (tapered opening within 507, see Fig. 5A) and coupled to the portion of the conductive structure (503) and a flanged portion (511, Fig. 5A, para [0059]) being configured to be exposed to provide a conductive contact to the electronic device (see Fig. 5A). Re Claim 29, Koduri teaches the electronic device of claim 28, wherein the flanged conductive column (509) comprises a solder coated (512, Fig. 5A, para [0059]) flanged copper column (copper column, para [0059]). Re Claim 30, Koduri teaches the electronic device of claim 29, wherein each of the base portion (510) and the flanged portion (511) of the solder coated flanged conductive column have a rectangular or square prism shape (510 and 511 have rectangular shapes, see Fig. 5A). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Koduri et al. (US 2019/0109108 A1, newly cited), and further in view of Mishra et al. (US 2020/0035633 A1, of record). Re Claim 6, Koduri teaches the electronic device of claim 1, but does not disclose an encapsulation material layer that overlies the insulator layer and encapsulates the flanged conductive column leaving a mounting surface of the flanged conductive column exposed and extending beyond the encapsulation material layer to provide a conductive contact to the electronic device. However, related art, Mishra teaches encapsulation material layer (126, Fig. 1A, para [0017]) that overlies the insulator layer (106, Fig. 1A, para [0013], similar to the insulator layer 507, Fig. 5A of Koduri) and encapsulates the flanged conductive column (108+114+116, Fig. 1A, paras [0014] – [0016], similar to the conductive column 509, Fig. 5A of Koduri) leaving a mounting surface of the flanged conductive column exposed (top surface of 116 is exposed, Fig. 1A) and extending beyond the encapsulation material layer to provide a conductive contact to the electronic device (see Fig. 1A). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to include the encapsulation layer into device of Koduri as shown by Mishra, because the encapsulation layer will provide mechanical support for the conductive column, improving reliability of the electronic device (para [0017], Mishra). Re Claim 8, Koduri modified by Mishra teaches the electronic device of claim 6, wherein the encapsulation material layer (126, Fig. 1A, Mishra) is a mold compound (126 can be an epoxy mold compound, para [0017], Mishra). Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Koduri et al. (US 2019/0109108 A1, newly cited) and Mishra et al. (US 2020/0035633 A1, of record), further in view of over Meyer-Berg et al. (US 2010/0127386 A1, of record). Re Claim 7, Koduri modified by Mishra teaches the electronic device of claim 6, but does not disclose that the encapsulation material layer is a laminate. However, in a related semiconductor art, Meyer-Berg teaches that the encapsulation material can be any thermosetting material or laminate and may contain filler materials, an may be deposited by molding, potting, dispensing, jetting or lamination (para [0021]). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, that the encapsulation material layer of Mishra can be a laminate as disclosed by Meyer-Berg. The substitution of a known material for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). Additionally, the selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07. Claims 21 and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Koduri et al. (US 2019/0109108 A1, newly cited). Re Claim 21, Koduri teaches the electronic device of claim 2, wherein each of the base portion and the flanged portion of the solder coated flanged conductive column have a rectangular cross-section (see Fig. 5A) and does not show a circular cross-section. However, in another embodiment in Fig. 1A, Koduri teaches that the base portion (110, Fig. 1A) and the flange portion (111, Fig. 1A) of the conductive column (109, Fig. 1A), can have a circular cross-section (see Fig. 1A). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, that the cross-sectional shape of the base portion and the flange portion can be either rectangular (Fig. 5A) or circular (Fig. 1A), as taught by Koduri, both performing the same function of providing a bonding interconnection structure for the electronic device. The use of a known structure for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). Re Claim 31, Koduri teaches the electronic device of claim 29, wherein each of the base portion and the flanged portion of the solder coated flanged conductive column have a rectangular cross-section (see Fig. 5A) and does not show a circular cross-section. However, in another embodiment in Fig. 1A, Koduri teaches that the base portion (110, Fig. 1A) and the flange portion (111, Fig. 1A) of the conductive column (109, Fig. 1A), can have a circular cross-section (see Fig. 1A). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, that the cross-sectional shape of the base portion and the flange portion can be either rectangular (Fig. 5A) or circular (Fig. 1A), as taught by Koduri, both performing the same function of providing a bonding interconnection structure for the electronic device. The use of a known structure for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). Claims 24-27 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Koduri et al. (US 2019/0109108 A1, newly cited), and further in view of Haba et al. (US 2012/0007232 A1, newly cited). Re Claim 24, Koduri teaches the electronic device of claim 1, but does not disclose that a width w and depth d of the base portion can range from 0.05 mm to 0.30 mm and a width W and depth D of the flanged portion can range from 0.10 mm to 0.40 mm. In a related semiconductor art, Haba teaches a plurality of conductive posts (110, Fig. 1B, para [0071]) where the bases (126, Fig. 1B, equivalent to the base portion 510, Fig. 5A of Koduri) and the cap-portion (130, Fig. 1B, equivalent to the flange portion 511, Fig. 5A of Koduri) can have a diameter between 0.03 mm and 0.15 mm (paras [0071] – [0072]), overlapping the claimed ranges. Examiner notes that the widths and depths are equivalent to the diameter of a circular cross-section. It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the widths and depths of the base and the flange portions, depending on the design needs of the electronic device of Koduri and using the known dimensions from Haba, and arrive at the claimed ranges. With respect to the limitations of the claim, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed ranges of the widths and depths of the base and the flange portions of the conductive column would have been obvious to one of ordinary skill in the art. Re Claim 25, Koduri teaches the electronic device of claim 1, but does not disclose that the height of the flanged conductive column can range from 0.10 mm to 0.30 mm where a thickness of the flanged portion can range from 0.03 mm to 0.10 mm. In a related semiconductor art, Haba teaches a plurality of conductive posts (110, Fig. 1B, para [0069]) where the height of the bases (H2, Fig. 1B, paras [0069] and [0073]) is over 0.05 mm (para [0069]) and can extend up to 0.3 mm (para [0062]). The height of the cap-portion, H3 can be between 0.025 mm and 0.08 mm (para [0072]), overlapping the claimed range of the thickness of the flanged portion. Thus, the total height H2+H3 can be in the range 0.075 mm and 0.38 mm, also overlapping the claimed range of the overall height. It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the overall height of the column and the thickness of the flanged portion, depending on the design needs of the electronic device of Koduri and using the known dimensions from Haba, and arrive at the claimed ranges. With respect to the limitations of the claim, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed ranges of the overall height of the column and the thickness of the flanged portion would have been obvious to one of ordinary skill in the art. Re Claim 26, Koduri teaches the electronic device of claim 21, but does not disclose that the diameter of the base portion can range from 0.05 mm to 0.30 mm and a diameter of the flanged portion can range from 0.10 mm to 0.40 mm. In a related semiconductor art, Haba teaches a plurality of conductive posts (110, Fig. 1B, para [0071]) where the bases (126, Fig. 1B, equivalent to the base portion 510, Fig. 5A of Koduri) and the cap-portion (130, Fig. 1B, equivalent to the flange portion 511, Fig. 5A of Koduri) can have a diameter between 0.03 mm and 0.15 mm (paras [0071] – [0072]), overlapping the claimed ranges. It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the diameter of the base and the flange portions, depending on the design needs of the electronic device of Koduri and using the known dimensions from Haba, and arrive at the claimed ranges. With respect to the limitations of the claim, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed ranges of the diameter of the base and the flange portions would have been obvious to one of ordinary skill in the art. Re Claim 27, Koduri teaches the electronic device of claim 21, but does not disclose that the overall height of the flanged conductive column can range from 0.10 mm to 0.30 mm and the thickness of the flanged portion can range from 0.03 mm to 0.10 mm. In a related semiconductor art, Haba teaches a plurality of conductive posts (110, Fig. 1B, para [0069]) where the height of the bases (H2, Fig. 1B, paras [0069] and [0073]) is over 0.05 mm (para [0069]) and can extend up to 0.3 mm (para [0062]). The height of the cap-portion, H3 can be between 0.025 mm and 0.08 mm (para [0072]), overlapping the claimed range of the thickness of the flanged portion. Thus, the total height H2+H3 can be in the range 0.075 mm and 0.38 mm, also overlapping the claimed range of the overall height. It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the overall height of the column and the thickness of the flanged portion, depending on the design needs of the electronic device of Koduri and using the known dimensions from Haba, and arrive at the claimed ranges. With respect to the limitations of the claim, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed ranges of the overall height of the column and the thickness of the flanged portion would have been obvious to one of ordinary skill in the art. Re Claim 32, Koduri teaches the electronic device of claim 28, but does not disclose that a width w and depth d of the base portion can range from 0.05 mm to 0.30 mm and a width W and depth D of the flanged portion can range from 0.10 mm to 0.40 mm. In a related semiconductor art, Haba teaches a plurality of conductive posts (110, Fig. 1B, para [0071]) where the bases (126, Fig. 1B, equivalent to the base portion 510, Fig. 5A of Koduri) and the cap-portion (130, Fig. 1B, equivalent to the flange portion 511, Fig. 5A of Koduri) can have a diameter between 0.03 mm and 0.15 mm (paras [0071] – [0072]), overlapping the claimed ranges. Examiner notes that the widths and depths are equivalent to the diameter of a circular cross-section. It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the widths and depths of the base and the flange portions, depending on the design needs of the electronic device of Koduri and using the known dimensions from Haba, and arrive at the claimed ranges. With respect to the limitations of the claim, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed ranges of the widths and depths of the base and the flange portions of the conductive column would have been obvious to one of ordinary skill in the art. Response to Arguments Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to PINAKI DAS whose telephone number is (703)756-5641. The examiner can normally be reached M-F 8-5 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JULIO MALDONADO can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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Prosecution Timeline

Dec 15, 2022
Application Filed
Nov 17, 2025
Non-Final Rejection mailed — §102, §103, §112
Apr 14, 2026
Response Filed
May 26, 2026
Final Rejection mailed — §102, §103, §112 (current)

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Prosecution Projections

3-4
Expected OA Rounds
89%
Grant Probability
98%
With Interview (+8.7%)
3y 6m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 46 resolved cases by this examiner. Grant probability derived from career allowance rate.

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