DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/23/2026 has been entered.
Response to Arguments
Applicant's arguments filed 03/11/2026 have been fully considered but they are not persuasive. Regarding claim 11, the 35 U.S.C. § 103 rejection below meets the amended limitations of the claims. Examiner notes that the recited limitations “a size of a first portion of the channel structure” in the 12th line of claim 11 and “a size of a second portion of the channel structure” in the 13th line of claim 11 have been given their broadest reasonable interpretation consistent with the specification. The interpretation of these limitations: “a size” and “a portion”, meets the plain meaning of the claim (MPEP 2111.01). When looking to the specification for additional support, Examiner notes that the specification does not provide a specific definition of these terms.
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Haller (US 2021/0066460 A1, hereinafter Haller ‘460) in view of Yamanaka (US 10,211,222 B1, hereinafter Yamanaka ‘222), in view of the following arguments.
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With respect to Claim 1 Haller ‘460 discloses a method for forming a three-dimensional memory (Fig 1-20A), comprising:
providing a base structure (16, Fig 8, Para [0035]) comprising a first protective layer (24, Fig 8, Para [0035]), a first sacrificial layer (26, Fig 8, Para [0035]), a second protective layer (28, Fig 8, Para [0035]), sequentially from bottom to top (Fig 8 discloses 24, 26, 28 sequentially from bottom to top);
forming a first channel hole (30, Fig 6, Para [0040]) in the base structure (16), the first channel hole (30) penetrating through, the second protective layer (28), the first sacrificial layer (26), and the first protective layer (24);
forming a third protective layer (34, Fig 6, Para [0041]) on a side wall (sidewall of 26 as shown in Fig 6) of the first sacrificial layer (26), wherein the side wall (sidewall of 26 as shown in Fig 6) of the first sacrificial layer (26) is exposed by (Para [0040] discloses creating hole 30 through 26 which would expose the sidewalls of 26, Para [0041] discloses then forming layer 34 within the opening of 30) the first channel hole (30);
forming a second sacrificial layer (36, Fig 6, Para [0043]) in the first channel hole (30), wherein a top surface (top of 36 as shown in Fig 7) of the second sacrificial layer (36);
forming a first stacked structure (42, Fig 8, Para [0049]), the first stacked structure (42) comprising gate sacrificial layers (48, Fig 8, Para [0049]) and dielectric layers (50, Fig 8, Para [0049]), wherein the gate sacrificial layers (48) and dielectric layers (50) are alternately stacked (48 and 50 alternately stacked shown in Fig 8);
forming a second channel hole (52, Fig 9, Para [0051]) in the first stacked structure (42), the second channel hole (52) penetrating vertically (52 penetrating vertically through 42 disclosed in Fig 9) through the first stacked structure (42), and an orthographic projection (Fig 20A) of the second channel hole (52) being entirely located within the first channel hole (30)(Fig 20A discloses structure 54/56/58 (which fill second channel hole 52 as described below)) entirely located within 60 (which fills 30 as described below)), wherein in a sectional view (Fig 9), a width of the second channel hole (a width of 52 shown in annotated Fig 9 of Haller ‘460) is less than a width of the first channel hole (a width of 30 shown in annotated Fig 9 of Haller ‘460), a bottom of the second channel hole (bottom of 52) is entirely arranged on the second sacrificial layer (36) and is spaced inwardly from the second sacrificial layer (36) in all lateral directions (annotated Fig 9 discloses a width of 52 is less than a width of 30 , a bottom of 52 is entirely arranged on 36 and is spaced inwardly from 36);
removing the second sacrificial layer (36)(Para [0052] discloses 36 is removed in a process of extending the opening of 52); and
forming a channel structure (54/56/60/74, Fig 11, Para [0053-0056 and 0066]) in the first channel hole (30) and the second channel hole (52)(channel structure formed in 30 and 52 disclosed in Fig 11 and Para [0053-0056]), the channel structure (54/56/60/74) including a channel layer (54/74, Fig 20, Para [0053 and 0066]) and a storage stacked layer (60, Fig 20, Para [0056]) surrounding an outer side surface (outer side of 54/74 shown in Fig 20) and an outer bottom surface (bottom of 54/74 shown in Fig 20) of the channel layer (54/74), wherein in a horizontal direction (horizontal direction shown in annotated Fig 20 of Haller ‘460), a size of a first bottom portion (a size of a first bottom portion of 54/56/60/74 shown in annotated Fig 20 of Haller ‘460) of the channel structure (54/56/60/74), at which the third protective layer (34) is located (arrangement show in annotated Fig 20 of Haller ‘460), is greater than a size of a portion (a size of a portion of 54/56/60/74 in 42 shown in annotated Fig 20 of Haller ‘460) of the channel structure (54/56/60/74) in the first stacked structure (42) (a size of a first bottom portion of 54/56/60/74 being greater than a size of 54/56/60/74 in 42 is shown in annotated Fig 20 of Haller ‘460), and after the gate sacrificial layers (48) are replaced (disclosed in Para [0068]) by gate metal layers (70, Fig 18, Para [0068]),
But Haller ‘460 fails to explicitly disclose a bottom dielectric layer, the first channel hole penetrating through the bottom dielectric layer, wherein a top surface of the second sacrificial layer is flush with or below a top surface of the bottom dielectric layer, forming a first stacked structure on the bottom dielectric layer, a size of a second bottom portion of the channel structure in the bottom dielectric layer is greater than the size of the portion of the channel structure in the first stacked structure.
Nevertheless, in a related endeavor (second embodiment, Fig 10-16B of Yamanaka ‘222), Yamanaka ‘063 teaches a bottom dielectric layer (21, Fig 10 of Yamanaka ‘222, Col 7, Lines 65-66).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Yamanaka ‘222’s bottom dielectric layer into Haller ‘460’s method. Haller ‘460 discloses a method for forming channel structures in a memory stack consisting of conductive and insulative layers over a base structure comprising, from bottom to top, a first protective layer, a first sacrificial layer, and a second protective layer. Yamanaka ‘222 also teaches a method for forming channel structures in a memory stack consisting of conductive and insulative layers over a base structure comprising, from bottom to top, a first protective layer, a first sacrificial layer, and a second protective layer but further teaches the formation of a dielectric layer over the second protective layer. The ordinary artisan would have been motivated to modify Haller ‘460 in the manner set forth above, at least, because this second protective layer, a dielectric layer, would provide additional protection to the second protective layer during the subsequent etching process to form the channel holes.
As incorporated, the bottom dielectric layer (21) of Yamanaka ‘222 would be used over the second protection layer (28) of Haller ‘460.
Therefore, Haller ‘460 as modified by Yamanaka ‘222 further discloses the first channel hole (30) penetrating through (as incorporated above 21 of Yamanaka ‘222 is over layer 28, therefore the channel hole 30 penetrates bottom dielectric layer) the bottom dielectric layer (21 of Yamanaka ‘222 as incorporated above), wherein a top surface (top surface of 36) of the second sacrificial layer (36) is flush with (reference annotated Fig 20 of Haller ‘460, as incorporated above 21 of Yamanaka ‘222 as incorporated above, is over layer 28, and channel hole 30 penetrates bottom dielectric layer 21, therefore 36 would be flush with bottom dielectric layer) or below a top surface of the bottom dielectric layer, forming a first stacked structure (42) on the bottom dielectric layer (21 of Yamanaka ‘222 as incorporated above) (as incorporated above 21 of Yamanaka ‘222 is over layer 28, therefore the stack structure 42 is on the bottom dielectric layer), a size of a second bottom portion of the channel structure in the bottom dielectric layer (a size of a second bottom portion of the channel structure (54/56/60/74) in the bottom dielectric layer 21 of Yamanaka ‘222 as incorporated in Haller ‘460 above, is shown in annotated Fig 20 of Haller ‘460) is greater than the size of the portion of the channel structure in the first stacked structure (a size of a the portion of the channel structure (54/56/60/74) in the first stacked structure 42, is shown in annotated Fig 20 of Haller ‘460)(a size of a second bottom portion of the channel structure in the bottom dielectric layer is greater than the size of the portion of the channel structure in the first stacked structure is disclosed in annotated Fig 20 of Haller ‘460).
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Haller ‘460 in view of Lee et al. (US 2016/0268263 A1, hereinafter Lee ‘263), in view of the following arguments.
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With respect to Claim 11 Haller ‘460 discloses a three-dimensional memory (Fig 1-20A) comprising:
a bottom silicon layer (68, Fig 20, Para [0064]);
a bottom dielectric layer (lowermost layer 50, Fig 20, Para [0049]) on the bottom polysilicon layer (68);
a plurality of conductive layers (70, Fig 20, Para [0068]) stacked above the bottom dielectric layer (lowermost layer 50), wherein a dielectric layer (50, Fig 20, Para [0049]) is disposed between adjacent conductive layers (70)(alternating stack of 50 and 70 shown in Fig 20); and
a channel structure (54/56/58/60/40/74/90/92, Fig 21, Para [0046, 0053, 0055, 0056, 0066, 0076], hereinafter CS) penetrating vertically (shown in Fig 20) through the plurality of conductive layers (70) and the dielectric layer (50) and extending down through the bottom silicon layer (68)(extension of CS through 50 and 70 and 68 shown in Fig 20), the channel structure (CS) including a channel layer (54/74, Fig 20, Para [0053 and 0066]) and a storage stacked layer (60, Fig 20, Para 0056]) surrounding an outer side surface (side of 54/74 shown in Fig 20) and an outer bottom surface (bottom of 54/74 shown in Fig 20) of the channel layer (54/74), the bottom silicon layer (68) extending laterally through the storage stacked layer (60) to connect the channel layer (54/75)(68 extending laterally through 60 to connect with 54/74 shown in Fig 20);
wherein
in a horizontal direction (horizontal direction as shown in annotated Fig 20_2 of Haller ‘460), a size of a first portion (a size of a first portion of CS disclosed in annotated Fig 20_2 of Haller ‘460) of the channel structure (CS) in the bottom dielectric layer (lowermost layer 50) is greater than a size of a second portion (a size of a second portion of CS disclosed in annotated Fig 20 of Haller ‘460) of the channel structure (CS) in the plurality of conductive layers (70)(annotated Fig 20_2 of Haller ‘460 discloses a first portion of CS in the lowermost layer 50 is greater than a size of a second portion of the channel structure in the plurality of conductive layers);
a third protective layer (34, Fig 6, Para [0041]) is configured to continuously cover (annotated Fig 20_2 discloses 34 continuously covering a bottommost surface of CS) a bottommost surface (bottommost surface of CS shown in annotated Fig 20 of Haller ‘460) of the channel structure (CS) and arranged entirely below the bottom silicon layer (68)(annotated Fig 20_2 of Haller ‘460 discloses 34 is arranged entirely below 68);
a size (shown in annotated Fig 20_2 of Haller ‘460) of the channel structure (CS) varies at a position corresponding to the bottom dielectric layer (lowermost layer 50)(Annotated Fig 20_2 of Haller ‘460 discloses the size of the first portion of CS in lowermost layer 50 varies from the size of a second portion of CS above lowermost layer 50); and
a portion (portion of 68 shown in annotated Fig 20 of Haller ‘460) of the bottom silicon layer (68), adjacent to and surrounding the channel layer (54/74)(annotated Fig 20_2 of Haller ‘460 discloses portion of 68 adjacent to and surrounding channel layer 54/75) of the channel structure (CS), has a uniform thickness (uniform thickness of 68 where it is adjacent to and surrounding 54/74 is disclosed in annotated Fig 20_2 of Haller ‘460) in a vertical direction (vertical direction shown in annotated Fig 20_2 of Haller ‘460) perpendicular to the horizontal direction (horizontal direction shown in annotated Fig 20_2 of Haller ‘460).
But Haller ‘460 fails to explicitly disclose a bottom polysilicon layer.
Nevertheless in a related endeavor (Fig 2 of Lee ‘263), Lee ‘263 teaches a bottom polysilicon layer (13, Fig 2 of Lee ‘263, Para [0033]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Lee ‘263’s bottom polysilicon layer into Haller ‘460’s device. Haller ‘460 teaches a multilayer conductive contact structure in a memory device and discloses silicon as a material for the structure. Lee ‘263 teaches a multilayer conductive structure in a memory device and teaches the use of polysilicon for that layer. The ordinary artisan therefore would be motivated to replace one well known material for a second well known material for the same purpose to achieve the well-known advantage of polysilicon having a higher resistivity and electrical performance than monocrystalline or amorphous silicon.
As incorporated, the polysilicon of Lee ‘263 would be used in the bottom silicon layer (68) of Haller ‘460 so that the bottom silicon layer, 68, is a bottom polysilicon layer.
With respect to Claim 12 Haller ‘460 as modified by Lee ‘263 discloses all limitations of the three-dimensional memory of claim 11, and Haller ‘460 further discloses wherein a bottom of the channel structure (bottom of CS as shown in annotated Fig 20_2 of Haller ‘460) comprises:
the first portion (first portion of CS shown in annotated Fig 20 of Haller ‘460) of the channel structure (CS) located in the bottom dielectric layer (lowermost layer 50)(annotated Fig 20 of Haller ‘460 discloses the first portion of CS located in the bottom dielectric layer); and
a third portion (third portion of CS shown in annotated Fig 20 of Haller ‘460) of the channel structure (CS) in a substrate (24, Fig 21, Para [0036]), wherein the bottom polysilicon layer (68 as modified by Lee ‘263 above) is located between the substrate (24) and the bottom dielectric layer (lowermost layer 50)(location of 68 between 24 and 50 is shown in annotated Fig 20 of Haller ‘460).
Claims 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Haller ‘460 in view of Lee ‘263 in view of Nishikawa et al. (US 2016/0365351 A1, hereinafter Nishikawa ‘351) and in further view of Lai et al. (US 2019/0035802 A1, hereinafter Lai ‘802), in view of the following arguments.
With respect to Claim 14 Haller ‘460 as modified by Lee ‘263 discloses all limitations of the three-dimensional memory of claim 11, and Haller ‘460 as modified by Lee ‘263 further discloses wherein the three-dimensional memory further comprises:
a substrate (24, Fig 21, Para [0036]), wherein the bottom polysilicon layer (68 as modified by Lee ‘263 as above) is located between the substrate (24) and the bottom dielectric layer (lowermost layer 50) (location of 68 between 24 and 50 is shown in annotated Fig 21 of Haller ‘460); and
But Haller ‘460 as modified by Lee ‘263 fails to explicitly discloses a step region comprising an annular groove structure, the annular groove structure penetrating vertically through the bottom polysilicon layer and extending down into the substrate.
Nevertheless, in a related endeavor (Fig 1-13E of Nishikawa ‘351), Nishikawa ‘351 teaches a step region (400, Fig 4 of Nishikawa ‘351, Para [0094]) comprising a groove structure (7P, Fig 6A of Nishikawa ‘351, Para [0118]), the groove structure (7P) penetrating vertically through the bottom polysilicon layer (12, Fig 4 of Nishikawa ‘351, Para [0086]) and extending down into the substrate (10, Fig 6A of Nishikawa ‘351, Para [0118])(Para [0118] discloses 7P extends “at least to the top surface of the substrate 10”, therefore an embodiment exists wherein 7P penetrates 10).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Nishikawa ‘351 of forming a groove structure penetrating vertically through the bottom polysilicon layer and extending down into the substrate in Haller ‘460 as modified by Lee ‘263’s device. The ordinary artisan would have been motivated to modify Haller ‘460 as modified by Lee ‘263’s method in the manner set forth above, at least, because, the step region provides as taught by Nishikawa ‘351 in Para [0118] these structures “provide support for the insulator layers in subsequent processing steps, and especially, during replacement of sacrificial material layers with conductive material layers”, so these step regions with support structures result in a more reliable manufacturing process.
As incorporated, the step region with groove structure as taught by Nishikawa ‘351 and described above would be used in the method of Haller ‘460 as modified by Lee ‘263.
But Haller ‘460 as modified by Lee ‘263 and further modified by Nishikawa ‘351 fails to explicitly disclose the groove is annular.
Nevertheless, in a related endeavor, (Fig 11 of Lai ‘802), Lai ‘802 teaches an annular groove (315, Fig 11 of Lai ‘802, Para [0057]) (Para [0058] of Lai ‘802 discloses, “the profile of the etching stop structure may be linear, corrugated, wavy, circular, polygonal, curved or the arbitrary combination thereof”).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Lai ‘802 of an annular groove in the device of Haller ‘460 as modified by Lee ‘263 and further modified by Nishikawa ‘351. The ordinary artisan would have been motivated to modify Haller ‘460 as modified by Lee ‘263 and further modified by Nishikawa ‘351 in the manner set forth above, at least, because, as taught by Lai ‘802 in Para [0058] (Col 14, Lines 41-45) “the profile of the etching stop structure may be linear, corrugated, wavy, circular, polygonal, curved or the arbitrary combination thereof”, so an annular structure could be used, which would provide more surface area for etch resistance and would allow regions to be protected from etching.
As incorporated, the annular groove of Lai ‘802 as described above would be used in the groove (7P) of the device of Haller ‘460 as modified by Lee ‘263 and further modified by Nishikawa ‘351.
With respect to Claim 15 Haller ‘460 as modified by Lee ‘263 and modified by Nishikawa ‘351 and further modified by Lai ‘802 discloses all limitations of the three-dimensional memory of claim 14, and Lai ‘802 further discloses wherein the annular groove (315) is in a shape of a polygonal ring, a circular ring, or an elliptical ring. (Para [0058] of Lai ‘802 discloses that the annular ring structure “may be linear, corrugated, wavy, circular, polygonal, curved or the arbitrary combination thereof”).
With respect to Claim 16 Haller ‘460 as modified by Lee ‘263 and modified by Nishikawa ‘351 and further modified by Lai ‘802 discloses all limitations of the three-dimensional memory of claim 14, and Nishikawa ‘351 further discloses wherein the step region (400) comprises a plurality of dummy channel hole structures (7Q, Fig 6A of Nishikawa ‘351, Para [0118]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the further teachings of Nishikawa ‘351 of forming a plurality of dummy channel holes in the device of Haller ‘460 as modified by Lee ‘263 and modified by Nishikawa ‘351 and further modified by Lai ‘802. The ordinary artisan would have been motivated to modify Haller ‘460 as modified by Lee ‘263 and modified by Nishikawa ‘351 and further modified by Lai ‘802 in the manner set forth above, at least, because, as taught by Nishikawa ‘351 in Para [0118] these structures “provide support for the insulator layers in subsequent processing steps, and especially, during replacement of sacrificial material layers with conductive material layers”, so these support structures result in a more reliable manufacturing process.
As incorporated, the plurality of dummy channels as further taught by Nishikawa ‘351 as described above would be used in the device of Haller ‘460 as modified by Lee ‘263 and modified by Nishikawa ‘351 and further modified by Lai ‘802.
With respect to Claim 17 Haller ‘460 as modified by Lee ‘263 and modified by Nishikawa ‘351 and further modified by Lai ‘802 discloses all limitations of the three-dimensional memory of claim 16, and Haller ‘460 as modified by Lee ‘263 and modified by Nishikawa ‘351 and further modified by Lai ‘802 further discloses wherein
at least one of the plurality of dummy channel hole structures is located within a surrounding area of the annular groove structure; or
at least one of the plurality of dummy channel hole structures (7Q of Nishikawa ‘351) is located outside the surrounding area of the annular groove structure (315 as taught by Lai ‘802)(Fig 6B of Nishikawa ‘351 discloses the dummy channels 7Q outside of structure 7P of Nishikawa ‘351. As implemented above the groove 315 of Lai ‘802 is used as the groove structure in Yamanaka ‘222 as modified by Nishikawa ‘351 and further modified by Lai ‘802, therefore the dummy pillars 7Q are outside of the annular groove).
Allowable Subject Matter
Claims 18-20 are allowed.
Claims 2-10 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 2, Allowable subject matter has been indicated because the closest prior art references of record, Haller (US 2021/0066460 A1) and Yamanaka (US 10,211,222 B1), either alone or in combination, fails to teach or fairly suggest the features " wherein after forming the second channel hole and before removing the second sacrificial layer, the method further comprises: forming a third sacrificial layer in the second channel hole; and forming a third channel hole in the second stacked structure, the third channel hole penetrating vertically through the second stacked structure, and an orthographic projection of the third channel hole onto the first stacked structure being located within the second channel hole, wherein a side wall of the third channel hole comprises a polysilicon liner layer; removing the polysilicon liner layer and the third sacrificial layer; and forming the channel structure in the third channel hole after removing the polysilicon liner layer, the third sacrificial layer, and the second sacrificial layer", along with the rest of the limitations of the claim.
Closest prior art of record Haller (US 2021/0066460 A1) and Yamanaka (US 10,211,222 B1) teaches a memory stack structure and a method of forming channel structures of the limitations of claim 1 but Haller (US 2021/0066460 A1) and Yamanaka (US 10,211,222 B1) either alone or in combination do not provide obvious motivation for forming a second stack with a third channel hole lined with polysilicon, then removing the polysilicon and third sacrificial layer, then forming the channel structure after forming the second channel hole and before removing the second sacrificial layer.
Regarding Claims 3-10, Allowable subject matter has been indicated because the closest prior art references of record, Haller (US 2021/0066460 A1) and Yamanaka (US 10,211,222 B1), either alone or in combination, fails to teach or fairly suggest the features “ forming an array common source structure in the gate line slit” along with the rest of the limitations of the claim.
Haller (US 2021/0066460 A1) and Yamanaka (US 10,211,222 B1) teach “forming a gate line slit, the gate line slit penetrating vertically through the first stacked structure and extending at least down into the first sacrificial layer; forming a side wall protective layer on a side wall of the gate line slit; removing the first sacrificial layer to obtain a bottom lateral slit; removing a portion of the storage stacked layer via the bottom lateral slit to expose a portion of the channel layer and removing the first protective layer and the second protective layer; forming a bottom polysilicon layer in the bottom lateral slit; removing the gate sacrificial layers to obtain a plurality of gate lateral slits; forming a conductive layer in the gate lateral slits” along with the limitations of Claim 1, but Haller (US 2021/0066460 A1) and Yamanaka (US 10,211,222 B1) either alone or in combination do not provide an obvious motivation for forming an array common source in the gate line slit.
Regarding Claim 13, Allowable subject matter has been indicated because the closest prior art references of record, Haller (US 2021/0066460 A1) and Lee et al. (US 2016/0268263 A1), either alone or in combination, fails to teach or fairly suggest the features “wherein a fourth portion of the channel structure in the plurality of conductive layers is divided into at least two segments, wherein a width of an upper segment of the channel structure is less than a width of a lower segment of the channel structure, the at least two segments of the channel structure being located above the bottom dielectric layer”, along with the rest of the limitations of the claim.
Haller (US 2021/0066460 A1) and Lee et al. (US 2016/0268263 A1) disclose the limitations of Claim 11 but either alone or in combination do not provide an obvious motivation for “wherein a fourth portion of the channel structure in the plurality of conductive layers is divided into at least two segments, wherein a width of an upper segment of the channel structure is less than a width of a lower segment of the channel structure, the at least two segments of the channel structure being located above the bottom dielectric layer”.
Regarding Claims 18-20, Allowable subject matter has been indicated because the closest prior art references of record, Haller (US 2021/0066460 A1) fails to teach or fairly suggest the features “the protruding portion of the channel structure comprising the first portion of the channel structure and a bottom end portion of the channel structure covered by a third protective layer;…and the third protective layer is entirely arranged below the bottom polysilicon layer” along with the rest of the limitations of the claim.
Haller (US 2021/0066460 A1) teaches the limitations “A three-dimensional memory comprising: a bottom polysilicon layer; a bottom dielectric layer located on the bottom polysilicon layer; a plurality of conductive layers stacked above the bottom dielectric layer, with a dielectric layer disposed between adjacent conductive layers; and a channel structure penetrating vertically through the plurality of conductive layers and the dielectric layer and extending down through the bottom polysilicon layer, the channel structure including a channel layer and a storage stacked layer surrounding an outer side surface and an outer bottom surface of the channel layer, the bottom polysilicon layer extending laterally across the storage stacked layer to connect the channel layer, wherein in a horizontal direction, a size of a first portion of the channel structure in the bottom dielectric layer is greater than a size of a second portion of the channel structure in the plurality of conductive layers; the channel structure comprises a protruding portion entirely below a top surface of the bottom dielectric layer”. However, Haller (US 2021/0066460 A1) fails to disclose “the protruding portion of the channel structure comprising the first portion of the channel structure and a bottom end portion of the channel structure covered by a third protective layer;…and the third protective layer is entirely arranged below the bottom polysilicon layer”.
Conclusion
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/PAUL A BERRY/Examiner, Art Unit 2898
/JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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