DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/05/2025 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-7 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. U.S. Patent Publication No. 2018/0374426 (hereinafter Chen) in view of Jang et al. U.S. Patent Publication No. 2022/0148522 (hereinafter Jang) and further in view of Lai et al. U.S. Patent Publication No. 2022/0208797 (hereinafter Lai).
Consider claim 1, Chen teaches a display device comprising: a display panel configured to display a display image and including a display area in which pixels are disposed (Figure 2 and [0082], central display region), and a sub-display area surrounding the display area and in which dummy pixels are disposed (Figure 2, edge display region (e.g. lowest brightness pixel 01)); wherein a size of a driving transistor included in each of the pixels disposed in the display area is different from a size of a driving transistor included in each of the dummy pixels disposed in the sub-display area ([0082], width-to length ratio), wherein a size of the driving transistor disposed in the second display area is greater than a size of the driving transistor disposed in the sub-display area ([0053], channel of the width-to-length ratio of the channel of the driver transistor of the furthest pixel in the edge display region from the central display region is no greater than 5% of the width-to-length ratio of the channel of the driver transistor of the pixel in the central display region. The width-to-length ratio of the channel of the driver transistor of the pixel in the edge display region immediately adjacent to the central display region is 40% to 60% of the width-to-length ratio of the channel of the driver transistor of the pixel in the central display region), and a size of the driving transistor disposed in the first display area is greater than the size of the driving transistor disposed in the second display area [0053].
Chen does not appear to specifically disclose an image shift controller configured to generate a display image shift signal including information on a path through which the display image is shifted; and a controller configured to receive the display image shift signal to generate input image data to which the display image shift signal is applied, wherein the display area includes a first display area which covers a center of the display panel and a second display area surrounding the first display area, wherein a whole of the first display area and a whole of the second display area output the display image during a predetermined initial time, and the sub-display area does not output the display image during the predetermined initial time, wherein the whole of the first display area always outputs the display image while the display image is displayed, and the whole or a part of the second display area selectively outputs the display image during a second time in which the display image is shifted.
However, in a related field of endeavor, Jang teaches a pixel shift processing unit (abstract) and further teaches an image shift controller configured to generate a display image shift signal including information on a path through which the display image is shifted ([0084-0085], active pixel region APA to be shifted. Figure 1, 130 and 110); and a controller configured to receive the display image shift signal to generate input image data to which the display image shift signal is applied ([0082], when the active pixel region APA is shifted, the timing controller 130 may modulate only pixel data to be written in the active pixel AP and the dummy pixel DP existing at the boundary between the active pixel region APA and the dummy pixel region DPA), wherein the display area includes a first display area which covers a center of the display panel and a second display area surrounding the first display area (Figure 9, center area where “APA” is located. Area adjacent to center area is considered second area), wherein a whole of the first display area and a whole of the second display area output the display image during a predetermined initial time (Figure 9, center area before shifting), and the sub-display area does not output the display image during the predetermined initial time (Figure 9, peripheral areas (e.g. black areas) before shifting) , wherein the whole of the first display area always outputs the display image while the display image is displayed (Figure 9, center areas), and the whole or a part of the second display area selectively outputs the display image during a second time in which the display image is shifted (Figure 9, area adjacent to the center area after one shift (see “1” in figure 9).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to shift an image as taught by Jang with the benefit that afterimages and deterioration of pixels are prevented and movement of an image on a screen is not visually recognized as suggested in [0007].
Chen does not appear to specifically a size of a gate electrode.
However, in a related field of endeavor, Lai teaches a display panel (abstract) and further teaches in figure 5, size of gate electrodes 20G-30G of transistors 20-30 are related to the size of the transistor (e.g. see width W1-W2).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to have size of gate electrodes based on size of transistor (e.g. width) with the benefit that the channel region of the first transistor 20 is the region where the first active layer 201 of the first transistor 20 overlaps the first gate electrode 20G and the channel region of the second transistor 30 is the region where the second active layer 301 of the second transistor 30 overlaps the second gate electrode 30G as suggested in [0049].
Consider claim 2, Chen, Jang and Lai teach all the limitations of claim 1. In addition, Chen teaches wherein the driving transistor included in each of the pixels disposed in the display area is defined as a first driving transistor, and the first driving transistor includes a first active pattern and a first gate electrode (Figures 4-5 and [0059], M2), the driving transistor included in each of the dummy pixels disposed in the sub-display area is defined as a second driving transistor, and the second driving transistor includes a second active pattern and a second gate electrode (Figures 4-5 and [0059], M2), and a size of the first driving transistor is greater than a size of the second driving transistor [0059].
Consider claim 3, Chen, Jang and Lai teach all the limitations of claim 1. In addition, Chen teaches wherein each of sizes of the driving transistor included in each of the pixels disposed in the second display area and the driving transistor included in each of the dummy pixels disposed in the sub-display area is gradually decreased in a direction from the first display area to the sub-display area ([0053], channel of the width-to-length ratio of the channel of the driver transistor of the furthest pixel in the edge display region from the central display region is no greater than 5% of the width-to-length ratio of the channel of the driver transistor of the pixel in the central display region. The width-to-length ratio of the channel of the driver transistor of the pixel in the edge display region immediately adjacent to the central display region is 40% to 60% of the width-to-length ratio of the channel of the driver transistor of the pixel in the central display region).
Consider claim 4, Chen, Jang and Lai teach all the limitations of claim 3. In addition, Chen teaches wherein each of the driving transistors included in the pixels disposed in the first display area has a same size ([0059], central display region).
Consider claim 5, Chen, Jang and Lai teach all the limitations of claim 4. In addition, Chen teaches wherein the display image is output through the first display area and the second display area, or output through the first display area, at least a part of the second display area, and at least a part of the sub-display area ([0021], display region AA as shown in figure 2).
Consider claim 6, Chen, Jang and Lai teach all the limitations of claim 1. In addition, Chen teaches wherein the size of the driving transistor included in each of the dummy pixels is gradually decreased as a distance between each of the dummy pixels and the display area is increased ([0053], channel of the width-to-length ratio of the channel of the driver transistor of the furthest pixel in the edge display region from the central display region is no greater than 5% of the width-to-length ratio of the channel of the driver transistor of the pixel in the central display region. The width-to-length ratio of the channel of the driver transistor of the pixel in the edge display region immediately adjacent to the central display region is 40% to 60% of the width-to-length ratio of the channel of the driver transistor of the pixel in the central display region).
Consider claim 7, Chen, Jang and Lai teach all the limitations of claim 1. In addition, Chen teaches wherein the pixels and the dummy pixels are arranged in a matrix shape (Figure 2, pixels 01 in the edge region).
Consider claim 21, Chen teaches an electronic device comprising (Figure 1): a display panel configured to display a display image and including a display area in which pixels are disposed (Figure 2 and [0082], central display region), and a sub-display area surrounding the display area and in which dummy pixels are disposed (Figure 2, edge display region (e.g. lowest brightness pixel 01)); wherein the display area includes a first display area which covers a center of the display panel and a second display area surrounding the first display area (Figure 2, plurality of regions in the center display region), and wherein a size of the driving transistor disposed in the second display area is greater than a size the driving transistor disposed in the sub-display area ([0053], channel of the width-to-length ratio of the channel of the driver transistor of the furthest pixel in the edge display region from the central display region is no greater than 5% of the width-to-length ratio of the channel of the driver transistor of the pixel in the central display region. The width-to-length ratio of the channel of the driver transistor of the pixel in the edge display region immediately adjacent to the central display region is 40% to 60% of the width-to-length ratio of the channel of the driver transistor of the pixel in the central display region), and a size of the driving transistor disposed in the first display area is greater than the size of the driving transistor disposed in the second display area [0053].
Chen does not appear to specifically disclose a host processor, an image shift controller configured to generate a display image shift signal including information on a path through which the display image is shifted; and a controller configured to receive an input control signal from the host processor and the display image shift signal from the image shift controller to generate input image data to which the display image shift signal is applied; wherein a whole of the first display area and a whole of the second display area output the display image during a predetermined initial time, and the sub-display area does not output the display image during the predetermined initial time, wherein the whole of the first display area always outputs the display image while the display image is displayed, and the whole or a part of the second display area selectively outputs the display image during a second time in which the display image is shifted.
However, Jang teaches a host processor ([0083], host system), an image shift controller (Figure 1, 130 and 110) configured to generate a display image shift signal including information on a path through which the display image is shifted ([0084] and figure 1) and a controller configured to receive an input control signal from the host processor [0081] and the display image shift signal from the image shift controller ([0082], when the active pixel region APA is shifted, the timing controller 130 may modulate only pixel data to be written in the active pixel AP and the dummy pixel DP existing at the boundary between the active pixel region APA and the dummy pixel region DPA) to generate input image data to which the display image shift signal is applied (Figure 9); wherein a whole of the first display area and a whole of the second display area output the display image during a predetermined initial time (Figure 9, center area before shifting), and the sub-display area does not output the display image during the predetermined initial time (Figure 9, peripheral areas (e.g. black areas) before shifting) , wherein the whole of the first display area always outputs the display image while the display image is displayed (Figure 9, center areas), and the whole or a part of the second display area selectively outputs the display image during a second time in which the display image is shifted (Figure 9, area adjacent to the center area after one shift (see “1” in figure 9).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to shift an image as taught by Jang with the benefit that afterimages and deterioration of pixels are prevented and movement of an image on a screen is not visually recognized as suggested in [0007].
Chen does not appear to specifically a size of a gate electrode.
However, in a related field of endeavor, Lai teaches a display panel (abstract) and further teaches in figure 5, size of gate electrodes 20G-30G of transistors 20-30 are related to the size of the transistor (e.g. see width W1-W2).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to have size of gate electrodes based on size of transistor (e.g. width) with the benefit that the channel region of the first transistor 20 is the region where the first active layer 201 of the first transistor 20 overlaps the first gate electrode 20G and the channel region of the second transistor 30 is the region where the second active layer 301 of the second transistor 30 overlaps the second gate electrode 30G as suggested in [0049].
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument (see new reference Jang).
Conclusion
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/ROBERTO W FLORES/Primary Examiner, Art Unit 2621