DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-8 are presented for examination based on the application filed on December 16, 2022.
Claims 1-5 are rejected under 35 U.S.C. § 112(a) or 35 U.S.C. § 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement.
Claims 1-5 and 8 are rejected under 35 U.S.C. § 112(b) or 35 U.S.C. § 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. § 112, the applicant), regards as the invention.
Claims 1-8 are rejected under 35 U.S.C. § 101 because the claimed invention is directed to judicial exception, an abstract idea, and it has not been integrated into practical application. The claims further do not recite significantly more than the judicial exception.
Claims 1-8 are rejected under 35 U.S.C. § 102(a)(2) as being anticipated by US 2022/0043951 A1 Ho, Chian-min Richard et al. [herein “Ho”].
This action is made non-Final.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed on December 16, 2022 fails to comply with 37 CFR 1.98(a)(2), which requires a legible copy of each cited foreign patent document; each non-patent literature publication or that portion which caused it to be listed; and all other information or that portion which caused it to be listed. It has been placed in the application file, but the information referred to therein has not been considered.
Drawings
Figure 1 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
Pg. 3 Ln. 27, which cites “constrains”, should be “constraints”. Also see Pg. 5 Ln. 29 and Pg. 14 Ln. 11 which include the same.
Pg. 10 Ln. 13, which cites “API”, should be “application programming interface (API)”.
Appropriate correction is required.
Claim Objections
Claims 1-8 are objected to because of the following informality: recitations of elements with a previous recitations. For example, claim 1, “a reinforcement learning agent (120)” on Pg. 1 Ln. 21, is improper because there has been a previous recitation of “a reinforcement learning agent (120)” on Pg. 1 Ln. 14-15. For the purpose of examination, “a reinforcement learning agent (120)” will be interpreted as “[[a]] the reinforcement learning agent (120)”. Claim 4, having similar limitations of claim 1, is also objected. Similarly, the following are objected under similar rationale:
Claim 1, “a simulation result” on Pg. 2 Ln. 1 should be “[[a]] the simulation result”. Claim 4, having similar limitations of claim 1, is also objected.
Claim 4, “a reinforcement learning environment” on Pg. 2 Ln. 27 should be “[[a]] the reinforcement learning environment”. Claim 6, having similar limitations of claim 4, is also objected.
All claims dependent on an objected base claim are objected based on their dependency.
Appropriate correction is required.
Claims 1-8 are objected to because of the following informality: recitations of elements with no previous recitations. For example, claim 1, “the semiconductor elements” on Pg. 2 Ln. 5 is improper because there has been no previous recitation of “the semiconductor elements”. For the purpose of examination, “the semiconductor elements” will be interpreted as “[[the]] semiconductor elements”. Claim 6, having similar limitations of claim 1, is also objected. Similarly, the following are objected under similar rationale:
Claim 6, “the steps” on Pg. 3 Ln. 22, should be “[[the]] steps”.
Claim 7, “the design data” on Pg. 5 Ln. 3 should be “the semiconductor design data”.
All claims dependent on an objected base claim are objected based on their dependency.
Appropriate correction is required.
Claims 1-8 are objected to because of the following informality: Claim 1, “constrains” on Pg. 1 Ln. 10 should be “[[constrains]] constraints”. Claim 6, having similar limitations of claim 1, is also objected. All claims dependent on an objected base claim are objected based on their dependency.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. § 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. § 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. § 112(f) or pre-AIA 35 U.S.C. § 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. § 112(f) or pre-AIA 35 U.S.C. § 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. § 112(f) or pre-AIA 35 U.S.C. § 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. § 112(f) or pre-AIA 35 U.S.C. § 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. § 112(f) or pre-AIA 35 U.S.C. § 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. § 112(f) or pre-AIA 35 U.S.C. § 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. § 112(f) or pre-AIA 35 U.S.C. § 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. § 112(f) or pre-AIA 35 U.S.C. § 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. § 112(f) or pre-AIA 35 U.S.C. § 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Regarding claim 1, such claim limitation is the “a simulation engine (110)”, “a reinforcement learning agent ( 120)”, and “a design data portion (130)”, and such claim limitation is the “a reinforcement learning environment construction portion (111)” and “a simulation portion (112)” in claim 4. Claims 2-5 will also be interpreted based on their claim dependencies.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. § 112(f) or pre-AIA 35 U.S.C. § 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. § 112(f) or pre-AIA 35 U.S.C. § 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. § 112(f) or pre-AIA 35 U.S.C. § 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. § 112(f) or pre-AIA 35 U.S.C. § 112, sixth paragraph.
There is no corresponding structure in the discloser for performing the claimed functions of the above limitations interpreted under 112(f). Therefore, the disclosure is devoid of any clear structure that performs the functions in the claims.
Claim Rejections - 35 U.S.C. § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. § 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. § 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-5 are rejected under 35 U.S.C. § 112(a) or 35 U.S.C. § 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 1, the original disclosure lacks structure for “a simulation engine (110) configured to analyze”, “a reinforcement learning agent (120) configured to perform”, and “a design data portion (130) configured to provide” as well as “a reinforcement learning environment construction portion (111) configured to analyze” and “a simulation portion (112) configured to perform” in claim 4 and does not disclose the corresponding structure, material, or acts for performing the respective claimed functions and to clearly link the structure, material, or acts to the function. The disclosure is devoid of any structure that performs the function in the claim. Therefore, the claim fails to comply with the written description requirement and is rejected under 35 U.S.C. § 112(a) or pre-AIA 35 U.S.C. § 112, first paragraph (see MPEP § 2181). Claims 2-5, which are dependent on claim 1, are similarly rejected. Therefore, the applicant may:
Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. § 112(f) or pre-AIA 35 U.S.C. § 112, sixth paragraph;
Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. § 132(a));
Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. § 132(a)); or
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. § 132(a)); or
Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR § 1.75(d) and MPEP § 608.01(o) and 2181.
Claim Rejections - 35 U.S.C. § 112(b)
The following is a quotation of 35 U.S.C. § 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. § 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-5 and 8 are rejected under 35 U.S.C. § 112(b) or 35 U.S.C. § 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. § 112, the applicant), regards as the invention.
Claim 1 limitation “a simulation engine (110) configured to analyze”, “a reinforcement learning agent (120) configured to perform”, and “a design data portion (130) configured to provide” as well as “a reinforcement learning environment construction portion (111) configured to analyze” and “a simulation portion (112) configured to perform” in claim 4 invokes 35 U.S.C. § 112(f) or pre-AIA 35 U.S.C. § 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The disclosure is devoid of any structure that performs the function in the claim. Therefore, the claim fails to comply with the written description requirement and is rejected under 35 U.S.C. § 112(a) or pre-AIA 35 U.S.C. § 112, first paragraph (see MPEP § 2181). Claims 2-5, which are dependent on claim 1, are similarly rejected. Therefore, the applicant may:
Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. § 112(f) or pre-AIA 35 U.S.C. § 112, sixth paragraph;
Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. § 132(a));
Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. § 132(a)); or
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. § 132(a)); or
Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR § 1.75(d) and MPEP § 608.01(o) and 2181.
Claim 8 recites “a step of converting the simulation data in step a) to an extensible Markup Language (XML) file to be used through a web” in Ln 20-21. This phrase renders the claim indefinite, because it merely recites a use without any steps delimiting the use (See MPEP § 2173.05(q), “Attempts to claim a process without setting forth any steps involved in the process generally raises an issue of indefiniteness under 35 U.S.C. § 112(b) or pre-AIA 35 U.S.C. § 112, second paragraph”).
Claim Rejections - 35 U.S.C. § 101
35 U.S.C. § 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-8 are rejected under 35 U.S.C. § 101 because the claimed invention is directed to judicial exception, an abstract idea, and it has not been integrated into practical application. The claims further do not recite significantly more than the judicial exception. Examiner has evaluated the claims under the framework provided in the 2019 Patent Eligibility Guidance published in the Federal Register 01/07/2019 and has provided such analysis below.
Step 1:
Claims 1-5 are directed to an apparatus and fall within the statutory category of a machine; and claims 6-8 are directed to a method and fall within the statutory category of a process. Therefore, “Are the claims to a process, machine, manufacture or composition of matter?” Yes.
In order to evaluate the Step 2A inquiry “Is the claim directed to a law of nature, a natural phenomenon or an abstract idea?” we must determine, at Step 2A Prong 1, whether the claim recites a law of nature, a natural phenomenon or an abstract idea and further whether the claim recites additional elements that integrate the judicial exception into a practical application.
Step 2A Prong 1:
Claims 1 and 6: The limitations of:
“analyze object information comprising a semiconductor element and a standard cell based on design data comprising semiconductor netlist information”,
“generate simulation data constituting a reinforcement learning environment having specific constrains configured with regard to individual analyzed objects”,
“perform simulation regarding disposition of the semiconductor element and the standard cell based on an action received from a reinforcement learning agent (120) and state information comprising disposition information of the semiconductor element and the standard cell to be used for reinforcement learning”,
“provide reward information calculated based on connection information of the semiconductor element and the standard cell according to a simulation result as feedback regarding decision making by the reinforcement learning agent (120)”,
“perform reinforcement learning based on state information and reward information received from the simulation engine (110), thereby determining an action so as to optimize disposition of the semiconductor element and the standard cell”,
“generates, as reward information, distances by considering semiconductor element sizes according to a simulation result and provides the reward information to the reinforcement learning agent (120)”, and
“determines an action through learning using a reinforcement learning algorithm such that the semiconductor elements are disposed in optimal positions, by reflecting the reward information in distances from already disposed semiconductor elements, positional relation, and lengths of wires connecting semiconductor elements and standard cells” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper. For example, the limitations can be performed as the following:
a person can mentally determine or draw with pen and paper, from a netlist of an initial semiconductor design, the type of semiconductor component and standard cell, such as a transistor and the “AND” functional logic block, respectively, and their connections,
a person can mentally define or draw with pen and paper that the maximum length of wire connecting the type of semiconductor component and standard cell in a semiconductor wiring diagram, such as a transistor and the “AND” functional logic block, respectively, for which will be performed simulations and trials to reach an objective through reinforcement learning,
a person can mentally determine or draw with pen and paper the new voltage drop between the transistor and functional logic block after receiving an instruction from reinforcement learning to move the elements closer to each other with respect to an initial location of each of these elements on a circuit board used in the reinforcement learning,
a person can mentally determine or draw with pen and paper a result of the simulation such as that if initial voltage drop in the initial semiconductor design is greater than the new voltage drop as result of receiving an instruction from reinforcement learning to move the elements closer to each other, then the distance between the elements should continue to be decreased, instituting a positive feedback for the instruction; otherwise, the distance between the elements should continue to be increased, instituting a negative feedback for the instruction,
a person can mentally determine or draw with pen and paper that if the feedback value on the instruction to move the elements is positive then the instruction is desirable, otherwise the instruction to move the elements and resultant placement is not desirable,
a person can mentally determine or draw with pen and paper a result of the simulation such as that if initial voltage drop in the initial semiconductor design is greater than the new voltage drop as result of receiving an instruction from reinforcement learning to move the elements closer to each other, then the distance between the elements should continue to be decreased, instituting a positive feedback for the instruction; otherwise, the distance between the elements should continue to be increased but not to exceed the maximum length of wire constraint, instituting a negative feedback for the instruction, and
a person can mentally determine or draw with pen and paper that if the feedback value on the instruction to move the elements is positive then the instruction is desirable, and otherwise the instruction to move the elements and resultant placement is not desirable thus moving elements closer to each other or further provides for optimal positioning of the elements and length of wire connecting the elements.
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea under Prong I step 2A.
Therefore, yes, claims 1 and 6 recite judicial exceptions. The claims have been identified to recite judicial exceptions, Step 2A Prong 2 will evaluate whether the claims are directed to the judicial exception.
Step 2A Prong 2:
Claims 1 and 6: The judicial exception is not integrated into a practical application. In particular, the claims recite the following additional elements: “An apparatus for reinforcement learning for semiconductor element position optimization based on semiconductor design data, the apparatus comprising: a simulation engine (110) configured to…, a reinforcement learning agent (120) configured to…, a design data portion (130) configured to…” which is merely a recitation of generic computing components and functions being used as a tool to implement the judicial exception (see MPEP § 2106.05(f)) with the broadest reasonable interpretation, which does not integrate a judicial exception into elements. Further, the following additional elements of “request optimization information for at least one semiconductor element disposition”, “provide design data comprising semiconductor netlist information to the simulation engine (110)”, “design data comprising semiconductor netlist information is uploaded” which are merely a recitation of insignificant extra-solution data gathering and data outputting activities (see MPEP § 2106.05(g)) which does not integrate a judicial exception into practical application. The insignificant extra-solution activities are further addressed below under step 2B as also being Well-Understood, Routine, and Conventional (WURC).
Therefore, “Do the claims recite additional elements that integrate the judicial exception into a practical application?” No, these additional elements do not integrate the abstract idea into a practical application and they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
After having evaluated the inquires set forth in Steps 2A Prong 1 and 2, it has been concluded that claims 1 and 6 not only recite a judicial exception but that the claims are directed to the judicial exception as the judicial exception has not been integrated into practical application.
Step 2B:
Claims 1 and 6: The claims do not include additional elements, alone or in combination, that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements amount to no more than generic computing components which do not amount to significantly more than the abstract idea. Further, the insignificant extra-solution data gathering, record update, and data transmission activities are also Well-Understood, Routine and Conventional (see MPEP § 2106.05(d)(II), “The courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. i. Receiving or transmitting data over a network, ii. Performing repetitive calculations, iii. Electronic recordkeeping, iv. Storing and retrieving information in memory”).
Therefore, “Do the claims recite additional elements that amount to significantly more than the judicial exception?” No, these additional elements, alone or in combination, do not amount to significantly more than the judicial exception. Having concluded the analysis within the provided framework, claims 1 and 6 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Regarding claims 2 and 7, they recite an additional limitation of “wherein the design data is a semiconductor data file comprising CAD data or netlist data”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper. For example, a person can mentally determine or draw with pen and paper, from a netlist of an initial semiconductor design, the type of semiconductor component and standard cell, such as a transistor and the “AND” functional logic block, respectively, and their connections.
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea under Prong I step 2A.
Regarding claim 3, it recites an additional element recitation of “wherein the simulation engine ( 110) has an application program additionally installed for web-based visualization” is merely a recitation of generic computing components and functions being used as a tool to implement the judicial exception (see MPEP § 2106.05(f)) and/or a field of use/technological environment (see MPEP § 2106.05(h)) which does not integrate a judicial exception into practical application. Further, this claim does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional element amounts to significantly more, this claim also fails both Step 2A prong 2, thus this claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, claim 3 does not recite patent eligible subject matter under 35 U.S.C. § 101.
Regarding claim 4, it recites additional limitations of:
“analyze object information comprising semiconductor elements and standard cells based on design data comprising semiconductor netlist information”,
“generate simulation data constituting a reinforcement learning environment and specific constraints with regard to individual objects”,
“perform simulation regarding disposition of semiconductor elements and standard cells based on actions received from the reinforcement learning agent (120)”,
“calculate reward information based on connection information of the semiconductor elements and the standard cells according to a simulation result as feedback regarding decision making by the reinforcement learning agent (120) and state information comprising disposition information of semiconductor elements and standard cells to be used for reinforcement learning”, and
“generate, as the reward information, distances by considering semiconductor element sizes according to the simulation result”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper. For example, the limitations can be conducted as the following:
a person can mentally determine or draw with pen and paper, from a netlist of an initial semiconductor design, the type of semiconductor component and standard cell, such as a transistor and the “AND” functional logic block, respectively, and their connections,
a person can mentally define or draw with pen and paper that the maximum length of wire connecting the type of semiconductor component and standard cell in a semiconductor wiring diagram, such as a transistor and the “AND” functional logic block, respectively, for which will be performed simulations and trials to reach an objective through reinforcement learning,
a person can mentally determine or draw with pen and paper the new voltage drop between the transistor and functional logic block after receiving an instruction from reinforcement learning to move the elements closer to each other with respect to an initial location of each of these elements on a circuit board used in the reinforcement learning,
a person can mentally determine or draw with pen and paper a result of the simulation such as that if initial voltage drop in the initial semiconductor design is greater than the new voltage drop as result of receiving an instruction from reinforcement learning to move the elements closer to each other, then the distance between the elements should continue to be decreased, instituting a positive feedback for the instruction; otherwise, the distance between the elements should continue to be increased, instituting a negative feedback for the instruction, and
a person can mentally determine or draw with pen and paper a result of the simulation such as that if initial voltage drop in the initial semiconductor design is greater than the new voltage drop as result of receiving an instruction from reinforcement learning to move the elements closer to each other, then the distance between the elements should continue to be decreased, instituting a positive feedback for the instruction; otherwise, the distance between the elements should continue to be increased but not to exceed the maximum length of wire constraint, instituting a negative feedback for the instruction.
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea under Prong I step 2A.
Furthermore, regarding claim 4, it recites additional element recitation of “wherein the simulation engine (110) comprises: a reinforcement learning environment construction portion (111) configured to… and a simulation portion (112) configured to” is merely a recitation of generic computing components and functions being used as a tool to implement the judicial exception (see MPEP § 2106.05(f)) which does not integrate a judicial exception into practical application. Further, the additional element recitations of “request the reinforcement learning agent (120), based on the simulation data, to provide optimization information for at least one semiconductor element disposition” and “provide the reward information to the reinforcement learning agent (120)” are merely an insignificant extra-solution data gathering and data outputting activities (see MPEP § 2106.05(g)) which does not integrate a judicial exception into practical application. Further, the insignificant extra-solution data gathering, record update, and data transmission activities are also Well-Understood, Routine and Conventional (see MPEP § 2106.05(d)(II), “The courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. i. Receiving or transmitting data over a network, ii. Performing repetitive calculations, iii. Electronic recordkeeping, iv. Storing and retrieving information in memory”). Further, this claim does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional element amounts to significantly more, this claim also fails both Step 2A prong 2, thus this claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, claim 4 does not recite patent eligible subject matter under 35 U.S.C. § 101.
Regarding claim 5, it recites an additional limitation of “wherein the reward information is calculated based on connection information of semiconductor elements and standard cells”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper. For example, a person can mentally determine or draw with pen and paper a result of the simulation such as that if initial voltage drop in the initial semiconductor design is greater than the new voltage drop as result of receiving an instruction from reinforcement learning to move the elements closer to each other, then the distance between the elements should continue to be decreased, instituting a positive feedback for the instruction; otherwise, the distance between the elements should continue to be increased, instituting a negative feedback for the instruction.
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea under Prong I step 2A.
Regarding claim 8, it recites an additional limitation of “a step of converting the simulation data in step a) to an extensible Markup Language (XML) file to be used through a web”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper. For example, a person can mentally generate or draw with pen and paper extensible Markup Language (XML) file containing the maximum length of wire connecting the type of semiconductor component and standard cell.
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea under Prong I step 2A.
Therefore, having concluded the analysis within the provided framework, claims 1-8 do not recite patent eligible subject matter and are rejected under 35 U.S.C. § 101 because the claimed invention is directed to judicial exception, an abstract idea, that has not been integrated into a practical application. The claims further do not recite significantly more than the judicial exception. Claims 2-5 and 7-8 are also rejected for incorporating the deficiency of their dependent claims 1 and 6, respectively.
Claim Rejections - 35 U.S.C. § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. § 102 and 103 (or as subject to pre-AIA 35 U.S.C. § 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. § 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8 are rejected under 35 U.S.C. § 102(a)(2) as being anticipated by US 2022/0043951 A1 Ho, Chian-min Richard et al. [herein “Ho”].
As per claim 1, Ho teaches “An apparatus for reinforcement learning for semiconductor element position optimization based on semiconductor design data.” (Para. 0020, “The system 100 generates, as output, a final computer chip floorplan 152 that places some or all of the nodes in the netlist data 102 at a respective position on the surface of the computer chip. That is, the final computer chip floorplan 152 identifies a respective position on the surface of the computer chip for some or all of the nodes in the netlist data 102 and, therefore, for the integrated circuit components that are represented by the node” [An apparatus for semiconductor element position optimization based on semiconductor design data]. Para. 0032, “In order for the score distributions 124 generated by the neural network 110 to result in a high-quality floorplan, the system 100 trains the node placement neural network 110 through reinforcement learning to maximize a reward function” [An apparatus for reinforcement learning for semiconductor element position optimization]. Further see Para. 0017-0020 and 0032-0035. The examiner has interpreted that a system that generates a computer chip floorplan for nodes of a netlist when trained through reinforcement learning to maximize a reward function as an apparatus for reinforcement learning for semiconductor element position optimization based on semiconductor design data.)
Ho teaches “the apparatus comprising: a simulation engine (110) configured to analyze object information comprising a semiconductor element and a standard cell based on design data comprising semiconductor netlist information, generate simulation data constituting a reinforcement learning environment having specific constrains configured with regard to individual analyzed objects”. (Para. 0032, “In order for the score distributions 124 generated by the neural network 110 to result in a high-quality floorplan, the system 100 trains the node placement neural network 110 through reinforcement learning to maximize a reward function” [reinforcement learning environment]. Para. 0018, “The system 100 receives netlist data 102 for a computer chip, i.e., a very large-scale integration (VLSI) chip, that is to be manufactured and that includes a plurality of integrated circuit components, e.g., transistors, resistors, capacitors, and so on” [object information comprising a semiconductor element based on design data comprising semiconductor netlist information]. Para. 0019, “The netlist data 102 is data describing the connectivity of the integrated circuit components of the computer chip. In particular, the netlist data 102 specifies a connectivity on the computer chip among a plurality of nodes that each correspond to one or more of a plurality of integrated circuit components of the computer chip. That is, each node corresponds to a respective proper subset of the integrated circuit components, and those subsets do not overlap. In other words, the netlist data 102 identifies, for each of the plurality of nodes, which other nodes (if any) the node needs to be connected to by one or more wires in the manufactured computer chip. In some cases, the integrated circuit components have already been clustered in clusters, e.g., by an external system or by using an existing clustering technique, and each node in the netlist data represents a different one of the clusters”. Para. 0021, “As one example, the netlist data 102 can identify three types of nodes: macros, clusters of standard cells, and ports. The system 100 can determine the placements for macros and clusters of standard cells, while the port placements can be fixed or can be determined by another system based on the placements determined” [object information comprising a standard cell based on design data comprising semiconductor netlist information]. Para. 0026-0027, “The system generates an input representation for the particular time step and processes the input representation using the node placement neural network 110. The input representation can also optionally include (e.g., as part of the current node data) netlist features that characterize the netlist of nodes, e.g., characterize the connectivity between the nodes that is specified in the netlist data 102. For example, the input representation may characterize for, one or more of the nodes, one or more other of the nodes to which that node is connected according to the netlist. In particular, the input representation may specify some or all of the nodes of the netlist to which the node to be placed at the particular time is connected according to the netlist, e.g., at least the one(s) of those nodes that have already been placed at time steps preceding the particular time step” [the apparatus comprising: a simulation engine (110) configured to analyze object information and generate simulation data constituting a reinforcement learning environment having specific constrains configured with regard to individual analyzed objects]. Further see Para. 0019-0029. The examiner has interpreted that a system that generates an input representation that includes netlist features of node connectivity at a particular time and that trains, through reinforcement learning, for node placement of integrated circuit components and clusters of standard cells of a computer chip as the apparatus comprising: a simulation engine (110) configured to analyze object information comprising a semiconductor element and a standard cell based on design data comprising semiconductor netlist information, generate simulation data constituting a reinforcement learning environment having specific constrains configured with regard to individual analyzed objects.)
Ho teaches “request optimization information for at least one semiconductor element disposition”. (Para. 0032-0033, “the system 100 trains the node placement neural network 110 through reinforcement learning to maximize a reward function. As one example, the system 100 can train the neural network 110 through reinforcement learning to determine trained values of the network parameters, and then after the training has completed, generate the initial floorplan 122 by generating a floorplan using the neural network 110 and in accordance with the trained values of the network parameters”. Para. 0092, “The system determines, using a reinforcement learning technique, an update to the current values of the network parameters”. Further see Para. 0032-0033, 0047-0048, and 0092-0095. The examiner has interpreted that using reinforcement learning to update the value of network parameters for the training of generating a floorplan using the node placement neural network as request optimization information for at least one semiconductor element disposition.)
Ho teaches “perform simulation regarding disposition of the semiconductor element and the standard cell based on an action received from a reinforcement learning agent (120) and state information comprising disposition information of the semiconductor element and the standard cell to be used for reinforcement learning”. (Para. 0032-0033, “the system 100 trains the node placement neural network 110 through reinforcement learning to maximize a reward function. As one example, the system 100 can train the neural network 110 through reinforcement learning to determine trained values of the network parameters, and then after the training has completed, generate the initial floorplan 122 by generating a floorplan using the neural network 110 and in accordance with the trained values of the network parameters”. Para. 0036, “During the training, the system 100 repeatedly generates candidate floorplans using the neural network 110, evaluates the value of the reward function for the generated candidate floorplan by evaluating the characteristics that are measured by the reward functions, and adjusts the values of the network parameters based on the value of the reward function”. Para. 0082-0085, “The system generates a candidate floorplan using the node placement neural network and in accordance with current values of the network parameters (step 402) as described above with reference to FIG. 2 The system evaluates the reward function to determine a reward for the generated candidate floorplan (step 404). As described above, the reward function generally measures the quality of the floorplans generated using the node placement neural network. More specifically, the reward function, i.e., measures certain characteristics of the generated floorplans that, when optimized, result in a chip that is manufactured using the generated floorplan exhibiting good performance, e.g., in terms of one or more power consumption, heat generation, and timing performance”. Further see Para. 0019-0029, 0032-0036, and 0082-0085. The examiner has interpreted that measuring the characteristics and quality of the floor plans generated using the node placement neural network during the training using reinforcement learning in accordance with current values as perform simulation regarding disposition of the semiconductor element and the standard cell based on an action received from a reinforcement learning agent (120) and state information comprising disposition information of the semiconductor element and the standard cell to be used for reinforcement learning.)
Ho teaches “provide reward information calculated based on connection information of the semiconductor element and the standard cell according to a simulation result as feedback regarding decision making by the reinforcement learning agent (120)”. (Para. 0032-0033, “the system 100 trains the node placement neural network 110 through reinforcement learning to maximize a reward function. As one example, the system 100 can train the neural network 110 through reinforcement learning to determine trained values of the network parameters, and then after the training has completed, generate the initial floorplan 122 by generating a floorplan using the neural network 110 and in accordance with the trained values of the network parameters” [provide reward information as feedback regarding decision making by the reinforcement learning agent (120)]. Para. 0035, “Generally, the reward function measures a quality of the floorplans generated using the node placement neural network 110, i.e., measures certain one or more characteristics of the generated floorplans that, when optimized, result in a chip that is manufactured using the generated floorplan exhibiting good performance, e.g., in terms of one or more of: power consumption, heat generation, and timing performance” [provide reward information calculated according to a simulation result]. Para. 0087, “The reward function can include a wire length measure, i.e., a term that measures wire length, that is higher when the wire length between nodes on the surface of the chip is shorter. For example, the wire length can be the Manhattan distance or other distance measure between all of the adjacent nodes on the surface of the chip” [reward information calculated based on connection information of the semiconductor element and the standard cell]. Further see Para. 0032-0036 and 0083-0087. The examiner has interpreted that training a neural network through reinforcement learning to generate a floor plan that maximizes a reward function including wire length between nodes on a chip and a measurement of the characteristics and quality of the floor plans generated as provide reward information calculated based on connection information of the semiconductor element and the standard cell according to a simulation result as feedback regarding decision making by the reinforcement learning agent (120).)
Ho teaches “a reinforcement learning agent (120) configured to perform reinforcement learning based on state information and reward information received from the simulation engine (110), thereby determining an action so as to optimize disposition of the semiconductor element and the standard cell”. (Para. 0032-0033, “the system 100 trains the node placement neural network 110 through reinforcement learning to maximize a reward function. As one example, the system 100 can train the neural network 110 through reinforcement learning to determine trained values of the network parameters, and then after the training has completed, generate the initial floorplan 122 by generating a floorplan using the neural network 110 and in accordance with the trained values of the network parameters”. Para. 0036, “During the training, the system 100 repeatedly generates candidate floorplans using the neural network 110, evaluates the value of the reward function for the generated candidate floorplan by evaluating the characteristics that are measured by the reward functions, and adjusts the values of the network parameters based on the value of the reward function”. Para. 0082-0085, “The system generates a candidate floorplan using the node placement neural network and in accordance with current values of the network parameters (step 402) as described above with reference to FIG. 2 The system evaluates the reward function to determine a reward for the generated candidate floorplan (step 404). As described above, the reward function generally measures the quality of the floorplans generated using the node placement neural network. More specifically, the reward function, i.e., measures certain characteristics of the generated floorplans that, when optimized, result in a chip that is manufactured using the generated floorplan exhibiting good performance, e.g., in terms of one or more power consumption, heat generation, and timing performance”. Further see Para. 0019-0029, 0032-0036, and 0082-0085. The examiner has interpreted that training through reinforcement learning in accordance with current values a node placement neural network to maximize a reward function during training to adjusting parameters as a result of a reward that measures the characteristics and quality of the floor plans generated by the neural network as a reinforcement learning agent (120) configured to perform reinforcement learning based on state information and reward information received from the simulation engine (110), thereby determining an action so as to optimize disposition of the semiconductor element and the standard cell.)
Ho teaches “a design data portion (130) configured to provide design data comprising semiconductor netlist information to the simulation engine (110)”. (Para. 0017-0018, “The floorplan generation system 100 is an example of a system implemented as computer programs on one or more computers in one or more locations in which the systems, components, and techniques described below are implemented. The system 100 receives netlist data 102 for a computer chip, i.e., a very large-scale integration (VLSI) chip, that is to be manufactured and that includes a plurality of integrated circuit components, e.g., transistors, resistors, capacitors, and so on” [design data comprising semiconductor netlist information to the simulation engine (110)]. Para. 0102, “Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices” [e.g., a design data portion (130) configured to provide design data]. Further see Para. 0017-0021 and 0101-0103. The examiner has interpreted that a computer that receives data from a storage device including netlist data for a computer chip to generate a floorplan as a design data portion (130) configured to provide design data comprising semiconductor netlist information to the simulation engine (110).)
Ho teaches “wherein the simulation engine (110) generates, as reward information, distances by considering semiconductor element sizes according to a simulation result and provides the reward information to the reinforcement learning agent (120)”. (Para. 0032-0033, “the system 100 trains the node placement neural network 110 through reinforcement learning to maximize a reward function. As one example, the system 100 can train the neural network 110 through reinforcement learning to determine trained values of the network parameters, and then after the training has completed, generate the initial floorplan 122 by generating a floorplan using the neural network 110 and in accordance with the trained values of the network parameters” [provide reward information to the reinforcement learning agent (120)]. Para. 0035, “Generally, the reward function measures a quality of the floorplans generated using the node placement neural network 110, i.e., measures certain one or more characteristics of the generated floorplans that, when optimized, result in a chip that is manufactured using the generated floorplan exhibiting good performance, e.g., in terms of one or more of: power consumption, heat generation, and timing performance” [provide reward information according to a simulation result]. Para. 0087, “The reward function can include a wire length measure, i.e., a term that measures wire length, that is higher when the wire length between nodes on the surface of the chip is shorter. For example, the wire length can be the Manhattan distance or other distance measure between all of the adjacent nodes on the surface of the chip” [wherein the simulation engine (110) generates, as reward information, distances by considering semiconductor element sizes]. Further Para. 0091, “The reward function can include one or more terms that measure the area of the floorplan, i.e., that are higher when the area taken up by the floorplan is lower” [generates, as reward information, distances by considering semiconductor element sizes]. Further see Para. 0032-0036, 0083-0087, and 0091. The examiner has interpreted that training a neural network through reinforcement learning to generate a floor plan that maximizes a reward function including wire length between nodes on a chip and a measurement of the characteristics and quality of the floor plans generated and including area of the floorplan as wherein the simulation engine (110) generates, as reward information, distances by considering semiconductor element sizes according to a simulation result and provides the reward information to the reinforcement learning agent (120).)
Ho teaches “wherein the reinforcement learning agent (120) determines an action through learning using a reinforcement learning algorithm such that the semiconductor elements are disposed in optimal positions, by reflecting the reward information in distances from already disposed semiconductor elements, positional relation, and lengths of wires connecting semiconductor elements and standard cells.” (Para. 0032-0033, “the system 100 trains the node placement neural network 110 through reinforcement learning to maximize a reward function. As one example, the system 100 can train the neural network 110 through reinforcement learning to determine trained values of the network parameters, and then after the training has completed, generate the initial floorplan 122 by generating a floorplan using the neural network 110 and in accordance with the trained values of the network parameters” [wherein the reinforcement learning agent (120) determines an action through learning using a reinforcement learning algorithm by reflecting the reward information]. Para. 0055, “The system also tracks the density of the positions on the chip, i.e., of the squares in the grid. In particular, the system maintains a density value for each position that indicates the degree to which that position is occupied. When a node has been placed at a given position, the density value for that position is set equal to one (or to a different maximum value that indicates that the position is fully occupied). When no node has been placed at the given position, the density value for that position indicates the number of edges that pass through the position.” Para. 0071, “the system can assign the node to the position having the highest score in the modified score distribution or sample a position from the modified score distribution, i.e., so that each position has a likelihood of being selected that is equal to the likelihood and then assign the node to the sampled position” [such that the semiconductor elements are disposed in optimal positions and position relation]. Para. 0036, “During the training, the system 100 repeatedly generates candidate floorplans using the neural network 110, evaluates the value of the reward function for the generated candidate floorplan by evaluating the characteristics that are measured by the reward functions, and adjusts the values of the network parameters based on the value of the reward function” [reflecting the reward information in distances from already disposed semiconductor elements]. Para. 0087, “The reward function can include a wire length measure, i.e., a term that measures wire length, that is higher when the wire length between nodes on the surface of the chip is shorter. For example, the wire length can be the Manhattan distance or other distance measure between all of the adjacent nodes on the surface of the chip” [lengths of wires connecting semiconductor elements and standard cells]. Further see Para. 0032-0036, 0055, 0071, and 0083-0087. The examiner has interpreted that training a neural network through reinforcement learning to adjust parameters used to generate floor plans that maximizes a reward function including wire length between nodes on a chip and tracks the density of the position of the chip to have the highest score based on sampled position of the node placed as wherein the reinforcement learning agent (120) determines an action through learning using a reinforcement learning algorithm such that the semiconductor elements are disposed in optimal positions, by reflecting the reward information in distances from already disposed semiconductor elements, positional relation, and lengths of wires connecting semiconductor elements and standard cells.)
As per claim 2, Ho teaches “wherein the design data is a semiconductor data file comprising CAD data or netlist data.” (Para. 0018, “The system 100 receives netlist data 102 for a computer chip, i.e., a very large-scale integration (VLSI) chip, that is to be manufactured and that includes a plurality of integrated circuit components, e.g., transistors, resistors, capacitors, and so on” [wherein the design data is a semiconductor data file comprising netlist data]. Para. 0019, “The netlist data 102 is data describing the connectivity of the integrated circuit components of the computer chip. In particular, the netlist data 102 specifies a connectivity on the computer chip among a plurality of nodes that each correspond to one or more of a plurality of integrated circuit components of the computer chip. That is, each node corresponds to a respective proper subset of the integrated circuit components, and those subsets do not overlap. In other words, the netlist data 102 identifies, for each of the plurality of nodes, which other nodes (if any) the node needs to be connected to by one or more wires in the manufactured computer chip. In some cases, the integrated circuit components have already been clustered in clusters, e.g., by an external system or by using an existing clustering technique, and each node in the netlist data represents a different one of the clusters”. Para. 0021, “As one example, the netlist data 102 can identify three types of nodes: macros, clusters of standard cells, and ports. The system 100 can determine the placements for macros and clusters of standard cells, while the port placements can be fixed or can be determined by another system based on the placements determined” [object information comprising a standard cell based on design data comprising semiconductor netlist information]. Further see Para. 0018-0021. The examiner has interpreted that a system that receives netlist data for a computer chip to generate a floorplan as wherein the design data is a semiconductor data file comprising netlist data.)
As per claim 3, Ho teaches “wherein the simulation engine (110) has an application program additionally installed for web-based visualization.” (Para. 0054, “The image 202 depicts the position, the connectivity, and, optionally, the size of the nodes that have already been placed on the chip” [visualization]. Para. 0101, “The processes and logic flows described in this specification can be performed by one or more programmable computers executing one or more computer programs to perform functions by operating on input data and generating output” [wherein the simulation engine (110) has an application program additionally installed for visualization]. Para. 0104, “a computer can interact with a user by sending documents to and receiving documents from a device that is used by the user; for example, by sending web pages to a web browser on a user's device in response to requests received from the web browser”. Para. 0107, “Embodiments of the subject matter described in this specification can be implemented in a computing system that includes a back end component, e.g., as a data server, or that includes a middleware component, e.g., an application server, or that includes a front end component, e.g., a client computer having a graphical user interface, a web browser, or an app through which a user can interact with an implementation of the subject matter described in this specification, or any combination of one or more such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication, e.g., a communication network. Examples of communication networks include a local area network (LAN) and a wide area network (WAN), e.g., the Internet” [for web-based visualization]. Further see Para. 0017-0018, 0054, and 0101-0104. The examiner has interpreted that a system for generating a floorplan that depicts the positions of nodes for chip through the execution of computer programs that can send web pages to a web browser over the Internet to be viewed on a client’s graphical user interface as wherein the simulation engine (110) has an application program additionally installed for web-based visualization.)
Re Claim 4, it is a system claim, having similar limitations of claim 1. Thus, claim 4 is also rejected under the similar rationale as cited in the rejection of claim 1.
As per claim 5, Ho teaches “wherein the reward information is calculated based on connection information of semiconductor elements and standard cells.” (Para. 0087, “The reward function can include a wire length measure, i.e., a term that measures wire length, that is higher when the wire length between nodes on the surface of the chip is shorter. For example, the wire length can be the Manhattan distance or other distance measure between all of the adjacent nodes on the surface of the chip” [wherein the reward information is calculated based on connection information of semiconductor elements and standard cells]. Further see Para. 0032-0036 and 0083-0087. The examiner has interpreted that generating a reward function including wire length between nodes on a chip as wherein the reward information is calculated based on connection information of semiconductor elements and standard cells.)
Re Claim 6, it is a method claim, having similar limitations of claim 1. Thus, claim 6 is also rejected under the similar rationale as cited in the rejection of claim 1.
Re Claim 7, it is a method claim, having similar limitations of claim 2. Thus, claim 7 is also rejected under the similar rationale as cited in the rejection of claim 2.
As per claim 8, Ho teaches “a step of converting the simulation data in step a) to an extensible Markup Language (XML) file to be used through a web.” (Para. 0101, “The processes and logic flows described in this specification can be performed by one or more programmable computers executing one or more computer programs to perform functions by operating on input data and generating output”. Para. 0098, “A computer program, which may also be referred to or described as a program, software, a software application, an app, a module, a software module, a script, or code, can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages; and it can be deployed in any form, including as a stand alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A program may, but need not, correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data, e.g., one or more scripts stored in a markup language document, in a single file dedicated to the program in question, or in multiple coordinated files, e.g., files that store one or more modules, sub programs, or portions of code”. [e.g., a step of converting the simulation data in step a) to an extensible Markup Language (XML) file]. Para. 0104, “a computer can interact with a user by sending documents to and receiving documents from a device that is used by the user; for example, by sending web pages to a web browser on a user's device in response to requests received from the web browser”. Para. 0107, “Embodiments of the subject matter described in this specification can be implemented in a computing system that includes a back end component, e.g., as a data server, or that includes a middleware component, e.g., an application server, or that includes a front end component, e.g., a client computer having a graphical user interface, a web browser, or an app through which a user can interact with an implementation of the subject matter described in this specification, or any combination of one or more such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication, e.g., a communication network. Examples of communication networks include a local area network (LAN) and a wide area network (WAN), e.g., the Internet” [to be used through a web]. Further see Para. 0098-0104. The examiner has interpreted that a system for generating a floorplan through the execution of computer programs that is stored in a markup language document to be sent to a web browser over the Internet as a step of converting the simulation data in step a) to an extensible Markup Language (XML) file to be used through a web.)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2021/0334445 A1 et al. Goldie; Anna Darling teaches a method for generating a computer chip placement from a netlist and having a neural network learn through reinforcement learning scores based on the positions of elements.
US 2023/0153492 A1 Park; Jinwoo et al. teaches a method for automating a semiconductor design based on training a neural network model to place semiconductor elements in a canvas in an order by a large size based on the feature information and the logical design information and rewards from reinforcement learning.
Mirhoseini, Azalia, Anna Goldie, Mustafa Yazgan, Joe Wenjie Jiang, Ebrahim Songhori, Shen Wang, Young-Joon Lee et al. "A graph placement methodology for fast chip design." Nature 594, no. 7862 (2021): 207-212 teaches of an automatic generation of chip floorplans based on key metrics, including power consumption, performance, chip area, and wire length using reinforcement learning.
Examiner’s Note: The examiner has cited particular columns and line numbers in the reference that applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. In the case of amending the claimed invention, the applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for the proper interpretation and also to verify and ascertain the metes and bound of the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Simeon P Drapeau whose telephone number is (571)-272-1173. The examiner can normally be reached Monday - Friday, 8 a.m. - 5 p.m. ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ryan Pitaro can be reached on (571) 272-4071. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SIMEON P DRAPEAU/ Examiner, Art Unit 2188
/RYAN F PITARO/ Supervisory Patent Examiner, Art Unit 2188